Resolution of Encoding Conflicts by
Signal Insertion and Concurrency
Reduction based on STG Unfoldings
V. Khomenko, A. Madalinski and A. Yakovlev
University of Newcastle upon Tyne
Signal Transition Graph (STG)
Bus
d
dsr
dsw
dtack
VME Bus
Controller
dsr+
dtack-
d-
lds-
lds
ldtack
Device
Data Transceiver
lds+
ldtack-
ldtack+
d+
dsr-
dtack+
2
Encoding conflicts
pairs of semantically different states with the same
binary encoding
 not distinguishable at the circuit level
 encoding conflicts have to be resolved before we can
proceed with synthesis
Transformations:
 signal insertion: introduces additional internal signal
(‘memory’) helping to trace the current state
 concurrency reduction: introduces additional ordering
constraints making some of the conflicting states
unreachable
 both are needed to explore a larger design space!

3
Example: CSC conflict
01000
dtack-
dsr+
00000
10000
lds+
ldtack-
ldtack-
01010
dtack00010
lds01110
ldtackdsr+
10100
10010
ldsldsdtackdsr+
M’’
00110 10110
ldtack+
M’
10110
d+
ddsr-
01111
dtack+
11111
10111
4
CSC resolution: signal insertion
dtack-
010000
ldtack-
dsr+
000000
ldtack-
lds011100
000100
100001
lds+
ldtack-
dtack010100
csc+
100000
dsr+
101001
100100
ldsldsdtackdsr+
M’’
101100
001100
ldtack+
M’
d-
csc011110
011111
dsr111111
101101
d+
dtack+
101111
5
CSC resolution: concurrency reduction
01000
dtack-
dsr+
00000
10000
lds+
ldtack-
ldtack-
01010
dtack00010
lds01110
ldtackdsr+
10100
10010
ldsldsdtackdsr+
M’’
00110 10110
ldtack+
M’
10110
d+
ddsr-
01111
dtack+
11111
10111
6
Framework for visualisation & interactive
resolution of encoding conflicts

manual vs. automatic resolution of coding
conflicts



automatic  can produce sub-optimal solutions
manual  crucial for finding good (low-latency,
compact & elegant) synthesis solutions
interactivity is good!
visualisation concepts:
 emphasise essential information
 avoid information overload
7
STG unfolding



partial order model
infinite acyclic net, simple structure
finite complete prefix





finite initial part of unfolding
contains all the reachable states
alleviates state space explosion problem
more visual then state graphs
proven efficient for model checking
8
State Graphs vs. Unfoldings
dtack01000
ldtack-
dsr+
10000
00000
ldtackdtack-
ldtackdsr+
01010
00010
10010
lds-
ldsdtack-
ldsdsr+
01110
00110
lds+
10110
ldtack+
10110
d+
d-
dsr01111
11111
dtack+
10111
dsr+
e2
lds+
e3
ldtack+
core e4
10100
M’’
e1
M’
d+
e5
dtack+
e6
e7
dsr-
e9
lds-
e11
ldtack-
e12
d-
M’
dtack-
e8
e
dsr+10
lds+
M’’
9
Visualisation of conflicts: Height map



cores often overlap
high-density areas are good candidates for
signal insertion
analogy with topographic maps
Core1
Core2
Core3
A1
A2
A3
10
Height map: an example
Highest
peak
csc+
Core map
Height map
11
Resolution of encoding conflicts
Signal insertion:



insert t+ in a core
t- must be added outside
the core preserving
consistency
inserted transitions must
not trigger an input signal
t-
t+
Core
12
Concurrency reduction

addition of causal constraint, i.e. a new place
u1
u2
t
(non-input)
Add a token if needed
13
Resolution of encoding conflicts
Forward concurrency reduction:

bringing forward the ending point of concurrency

‘dragging’ f into the core
14
Resolution of encoding conflicts
Backward concurrency reduction:


delaying starting point of concurrency
‘dragging’ f into the core
15
Resolution of encoding conflicts
Concurrency reduction: an example
p’
backward
forward
backward
inputs: b,c,f; outputs: a,d,e
inputs: a,b; outputs: c,d,e
16
Overview of the resolution process
phase 2
concurrency
reduction
signal
insertion
phase 1
17
Cost function
cost = α1· + α2·logic – α3·core

: estimated delay caused by transformation

logic: estimated increase in complexity of logic

core: number of eliminated cores,

αi: parameters chosen by the designer
Calculated on the original unfolding prefix
18
Validity


signal insertion: well-developed, e.g. weak
bisimulation
concurrency reduction: more challenging, e.g.:



not even language-equivalent
events can become dead
introduction/disappearance of deadlocks
19
Validity aspects

I/O interface preservation
the interface between circuit and its environment
should be preserved


conformation


no “wrong” behaviour should be introduced
liveness
no “interesting” behaviour should be completely
eliminated


technical restrictions

boundedness, speed-independence, etc.
20
Validity notion


natural to use partial order framework when
speaking about concurrency reduction!
plan:


define a “valid realisation” relation on partial
order analog of traces (processes)
define “valid realisation” relation on systems
21
Validity notion: processes

can easily eliminate silent actions (e.g. internal
signals) preserving causality – abstraction
a
b
a
b
d
c
d

c
22
Validity notion: processes


step 1: increasing concurrency of inputs
step 2: decreasing concurrency of outputs
23
Validity notion: processes

step 1: increasing concurrency of inputs
i1
o
i1

i2
o
i2
step 2: decreasing concurrency of outputs
o1
i
o2
o1
o2
i
24
Validity notion: processes
i1
o
i1
i2
o
o1
i1
i2
o
o1
i
o2
i
o1
o2
o1
i1
i2
i2
o2
i1
i2
o1
o2
o2
i
o1
o2
i1
i2
25
Validity notion: systems

valid realisation:
(original)
e
E
(transformed)
E’
(original)
E
(transformed) e’
E’
26
Validity notion: systems
i1
i2
i2
i1
o1
-1
-1
o2
o
o
o
-1
i1
i2
o1
o2
o2
o1
…
o
o
…
o
27
Case study: AD converter controller
concurrency reduction
# causal constraint cost
1 start   Lr 
2 ready   Lr 
-3
-3
  Ar  -2

 1
4 start  Ar
3 ready
signal insertion
#
phase 1
phase 2
cost
6
|| Laf+ to Lr-
->ready-
-1
7
Laf+ ->
->ready-
0
8
->Ar-
->ready-
0
9
-> Lr-
->ready-
1
10
Laf+ ->
start- ->
1
11
Laf+ ->
|| ready+ to ready-
1
Core map
28
Conclusions



combined framework for resolution of encoding
conflicts based on cores in the STG unfolding
larger design space – exploit the area/delay
trade-off
novel validity condition
Future work



more automation
improving cost function
performing transformation directly on the
unfolding prefix rather than the STG
29