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DIGITAL LOGIC DESIGN
Lecture #13: Digital Comparators
Digital Comparators
 Comparator: A circuit that compares two
binary words and indicates whether they
are equal
 Magnitude comparator: Interprets its
inputs as signed or unsigned numbers and
indicates their arithmetic relationship
(greater or less than)
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Example Comparator Use
 Devices are enabled by comparing a “device
select” word with a predetermined “device ID”
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Equality Comparators
 1-bit comparator
• Active-high output
(DIFF) asserted if the
inputs are different
1/4 74x86
A0
B0
1
3
DIFF
2
U1
EQ_L
 4-bit comparator
• The DIFF output is
asserted if any of the
input pairs are different
74x86
A0
B0
A1
B1
A2
B2
A3
B3
1
3
DIFF0
2
U1
4
5
6
DIFF1
U1
9
8
DIFF
DIFF2
10
U1
12
11
DIFF3
EQ_L
13
U1
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2
4-Bit Magnitude Comparator
 Two input numbers to compare, 4 bits each: A=A3A2A1A0 ; B=B3B2B1B0
 Three outputs, reporting “greater than”, “less than”, and “equal”, respectively
A3, B3
Compared Inputs
A2, B2
A1, B1
A3 > B3
A0, B0
Outputs
“A > B” “A < B” “A = B”
x
x
x
1
0
1
A3 < B3
x
x
x
0
1
0
A3 = B3
A2 > B2
x
x
1
0
0
A3 = B3
A2 < B2
x
x
0
1
0
A3 = B3
A2 = B2
A1 > B1
x
1
0
0
A3 = B3
A2 = B2
A1 < B1
x
0
1
0
A3 = B3
A2 = B2
A1 = B1
A0 > B0
1
0
0
A3 = B3
A2 = B2
A1 = B1
A0 < B0
0
1
0
A3 = B3
A2 = B2
A1 = B1
A0 = B0
1
0
0
A3 = B3
A2 = B2
A1 = B1
A0 = B0
0
1
0
A3 = B3
A2 = B2
A1 = B1
A0 = B0
0
0
1
Note “x” (don’t care) notation.
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4-Bit Magnitude Comparator
 Input A=A3A2A1A0 ; B=B3B2B1B0
 Case A = B : A3=B3, A2=B2, A1=B1, A0=B0
xi = (AiBi) = Ai·Bi + Ai·Bi
XNOR = (AiBi) = (Ai·Bi+ Ai·Bi)
= (Ai+Bi)·(Ai+Bi)
= Ai·Ai + Ai·Bi + Ai·Bi + Bi·Bi
= Ai·Bi + Ai·Bi
–
Output: x3·x2·x1·x0
 Case A > B :
–
Output:
A3·B3 + x3·A2·B2 + x3·x2·A1·B1 +
x3·x2·x1·A0·B0
 Case A < B :
–
Output:
A3·B3 + x3·A2·B2 + x3·x2·A1·B1+
x3·x2·x1·A0·B0
XNOR
A3
x3
B3
A2
x2
B2
(A<B)
A1
x1
B1
A0
x0
(A>B)
B0
(A=B)
X
Y
(XY)
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Iterative Combinational Circuits
 General structure: n identical modules
–
For problems that can be solved by an iterative algorithm:
1. Set C0 to its initial value and set i to 0
2. While i < n repeat:
a) Use Ci an PIi to determine the values of POi and Ci+1
b) Increment i a
primary inputs
cascading
input
PI0
PI
C0
CI
C1
module CO
PI
CI
module CO
PO
PIn–1
cascading
output
PI1
PI
Cn–1
C2
CI
PO
module CO
Cn
PO
boundary
inputs
boundary
outputs
PO0
POn–1
PO1
primary outputs
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An Iterative Comparator Circuit
 (a) module for one bit
(a)
 (b) complete circuit
X
Y
CMP
– Comparing two n-bit values X and Y:
1. Set EQ0 to 1 and set i to 0
2. While i < n repeat:
EQO
EQI
a) If EQi is 1 and Xi equals Yi, set EQi+1 to 1
Else set EQi+1 to 0
b) Increment i
EQO = (A  B) · EQI
 Slow because the cascading signals
need time to “ripple” from left to right
X0
Y0
X1
Y1
X2
X(N–1) Y(N–1)
Y2
(b)
X
1
EQI
Y
CMP
EQ1
EQO
X
EQI
Y
CMP
EQ2
EQO
X
EQI
Y
CMP
EQ3
EQO
X
EQ(N–1)
EQI
Y
CMP
EQN
EQO
first input
has to be 1
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4
4-bit Comparator 74x85
 Outputs:
– Greater-than output (AGTBOUT)
– Less-than output (ALTBOUT)
– Equal output (AEQBOUT)
2 ALTBIN
3
4
 Cascading inputs:
10
– AGTBIN, ALTBIN, AEQBIN
9
 Cascading inputs and the outputs are arranged
12
11
in a 1-out-of-3 code, since normally exactly one
input and output should be asserted
13
14
15
1
74x85
ALTBOUT 7
AEQBIN
AEQBOUT
AGTBIN
A0
B0
A1
B1
AGTBOUT
6
5
A2
B2
A3
B3
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12-bit Comparator using 74x85s
AGTBOUT = (A>B) + (A=B) · AGTBIN
AGTBOUT = (A=B) · AEQBIN
AGTBOUT = (A<B) + (A=B) · ALTBIN
XNOR
(A>B) = A3·B3 + (A3B3) · A2·B2 +
(A3B3) · (A2B2) · A1· B1 +
(A3B3) · (A2B2) · (A1B1) · A0·B0
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5
8-bit Magnitude Comparator
 74x682
–
–
Does not have cascading inputs
(unlike 74x85)
Does not provide a “less than”
output
Compares equality
using 4 XNOR gates
PEQQ_L
74x682
2
3
4
5
6
7
8
P0
Q0
P1
Q1
P2
Q2
P3
19
PEQ Q
9
11
12
13
Q3
P4
Q4
P5
1
PGTQ_L
Compares if
P[7–0] > Q[7–0]
PGT Q
14
15
16
17
18
Q5
P6
Q6
P7
Q7
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Arithmetic Conditions from 74x682
 Not-provided conditions
PNEQ
can be implemented as a
function of outputs
PEQQ_L and PGTQ_L

74x04
1
2
PEQQ
U2
74x04
4
PGTQ
U2
74x682
74x00
1
3
PEQQ
2
19
PGEQ
U3
PGTQ
PLEQ
1
1
74x08
3
2
U1


PLTQ
U4
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