Digital Logic: Boolean
Algebra and Gates
Textbook Chapter 3
CMPE12 – Summer 2008
Basic Logic Gates
CMPE12 – Summer 2008 – Slides by ADB
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1
Truth Table
„
„
„
The most basic
representation of a logic
function
Lists the output for all
possible input
combinations
How many rows of the
truth table needed?
Inputs
Outputs
AB…
XY…
2#inputs
CMPE12 – Summer 2008 – Slides by ADB
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Truth Table: Inverter
„
„
Inverted signals are
denoted with an overbar
Or with a prime symbol
‹ A’
CMPE12 – Summer 2008 – Slides by ADB
Input
Output
A
Y = A’
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Truth Table: AND Gate
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„
„
„
The result of an AND
operation is 1 if and only
if all inputs are 1
Depict AND by the
multiplication symbol
‹ A·B
Or by lumping the signals
together
‹ AB
We don’t really build
these gates…
Inputs
Output
A B
Y=A·B
CMPE12 – Summer 2008 – Slides by ADB
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Truth Table: OR Gate
„
„
The result of an OR
operation is 1 if and only
if any inputs are 1
Depict OR by the
addition symbol
‹ A+B
CMPE12 – Summer 2008 – Slides by ADB
Inputs
Output
A B
Y=A+B
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3
About the Little Circle…
„
The little circle is what inverts
CMPE12 – Summer 2008 – Slides by ADB
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Sum of Products
„
„
„
How do you get from a truth table to a logic
expression?
Sum of products is standard way of
synthesizing simple circuits
Procedure:
1. Find the rows with the ‘1’ output
2. Write the product-form expression for the inputs
in that row (0=inverted, 1=normal)
3. Combine the products in step 2 into a sum (OR
the results of step 2)
CMPE12 – Summer 2008 – Slides by ADB
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4
Sum of Products
A
B
Y
0
0
0
0
1
1
1
0
1
1
1
0
1. Find the rows with the ‘1’
output
2. Write the product-form
expression for the inputs
in that row (0=inverted,
1=normal)
3. Combine the products in
step 2 into a sum (OR
the results of step 2)
CMPE12 – Summer 2008 – Slides by ADB
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De Morgan’s Laws
„
„
“Break the line, change the sign”
Two laws:
A’ + B’ = (AB)’
‹ A’ B’ = (A+B)’
‹
CMPE12 – Summer 2008 – Slides by ADB
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5
De Morgan’s Laws
(A + B)’ = A’B’
conversely
(AB)’ = A’ + B’
“Break the line, change the sign”
A B
A+B
A A+B
A
B
A·B
0 0
0 1
1 0
1 1
CMPE12 – Summer 2008 – Slides by ADB
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De Morgan’s Laws
(A + B)’ = A’B’
conversely
(AB)’ = A’ + B’
“Break the line, change the sign”
A B
AB
A AB
A
B
A+B
0 0
0 1
1 0
1 1
CMPE12 – Summer 2008 – Slides by ADB
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6
De Morgan’s Laws
„
„
In other words…
Push the bubbles through!
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De Morgan’s Laws and SOP
„
Generate equivalent circuits
NAND/NAND
‹ NOR/NOR
‹
„
We prefer NAND/NAND circuits
Same transistor count as NOR
‹ NANDs are faster
‹
CMPE12 – Summer 2008 – Slides by ADB
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7
Masking
„
„
„
Want to look only at certain bits of a binary word
Use a mask to remove the uninteresting bits
Example:
CMPE12 – Summer 2008 – Slides by ADB
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Axioms of Boolean Algebra
„
„
„
„
„
„
„
„
„
0·0=
1+1=
1·1=
0+0=
0·1=1·0=
1+0=0+1=
1+0=0+1=
if x = 0 then x’ =
if x = 1 then x’ =
CMPE12 – Summer 2008 – Slides by ADB
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8
Single-Variable Theorems
„
„
„
„
„
„
„
„
„
x·0=
x+1=
x·1=
x+0=
x·x=
x+x=
x · x’ =
x + x’ =
(x’)’ =
CMPE12 – Summer 2008 – Slides by ADB
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Properties of Boolean Algebra
„
„
„
Commutative
‹ x · y =
‹ x + y =
Associative
‹ x · (y · z) =
‹ x + (y + z) =
Distributive
‹ x · (y + z ) =
‹ x + y · z =
CMPE12 – Summer 2008 – Slides by ADB
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Properties of Boolean Algebra
„
„
„
Absorption
‹ x + x · y =
‹ x · (x + y) =
Combining
‹ x · y + x · y’ =
‹ (x + y) · (x + y’) =
De Morgan’s Laws
‹ (x · y)’ =
‹ (x + y)’ =
„
Other
‹ x + x’·y =
‹ x · (x’ + y) =
CMPE12 – Summer 2008 – Slides by ADB
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Logic Minimization
A
B
C
Y
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
0
CMPE12 – Summer 2008 – Slides by ADB
„
Example
22
10
Last time…
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More Than Two Inputs?
„
AND and OR gates can take any number of
inputs
AND gives 1 if all inputs are 1
‹ OR gives 1 if any input is 1
‹
„
NAND?? NOR??
‹
Not associative!
CMPE12 – Summer 2008 – Slides by ADB
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11
Two-Way Multiplexer: Logic Symbol
CMPE12 – Summer 2008 – Slides by ADB
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Two-Way Multiplexer: Sum of Products
2-way multiplexer: the
output is equal to one of the
two inputs, based on a
selector
CMPE12 – Summer 2008 – Slides by ADB
S
A
B
Y
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
0
1
1
1
1
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Uses of a Multiplexer
„
Select which input to use
Select which computed value to pass to the next
stage of a computation (or to place on bus)
„
The main point:
„
‹
A multiplexer is a selector
CMPE12 – Summer 2008 – Slides by ADB
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Four-Way Multiplexer
„
n-bit selector and 2 n inputs, one output
‹ output
„
equals one of the inputs, depending
on selector
“Four-to-one mux”
CMPE12 – Summer 2008 – Slides by ADB
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Two-to-Four Decoder
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„
n inputs, 2 n outputs
‹ exactly one output is 1
for each possible input
pattern
Generates a walkingones pattern
CMPE12 – Summer 2008 – Slides by ADB
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Binary Addition and Half-Adder
„
„
„
„
„
0+0=0
0+1=1
1+0=1
1 + 1 = ...
Bigger addition example:
CMPE12 – Summer 2008 – Slides by ADB
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A half-adder is…
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14
One-Bit Full Adder
A B Cin Cout
0 0
0
0 0
1
0 1
0
0 1
1
1 0
0
1 0
1
1 1
0
1 1
1
S
CMPE12 – Summer 2008 – Slides by ADB
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Four-Bit Full Adder
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Recommended exercises: combinational
circuits
„
„
„
„
„
Ex 3.5, 3.6, 3.7, 3.8, 3.9
Ex 3.11, 3.12, 3.18
Ex 3.20, 3.22, 3.23, 3.24 with TA/Tut
Ex 3.30, 3.31, 3.35
Ex 3.44
CMPE12 – Summer 2008 – Slides by ADB
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Combinational vs. Sequential
Two types of “combination” locks
4 1 8 4
Combinational
Success depends only on
the values, not the order in
which they are set.
CMPE12 – Summer 2008 – Slides by ADB
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20
30
15
5
10
Sequential
Success depends on
the sequence of values
(e.g, R-13, L-22, R-3).
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16
Combinational vs. Sequential
„
Combinational circuit
Always gives the same output for a given set of
inputs
‹ Example: Adder always generates sum and
carry, regardless of previous inputs
‹
„
Sequential circuit
Remembers previous input
‹ Output depends on state and input
‹
CMPE12 – Summer 2008 – Slides by ADB
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Feedback and Memory
„
What if…
You connected an OR gate back to itself?
‹ You connected an AND gate back to itself?
‹
CMPE12 – Summer 2008 – Slides by ADB
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The Set Latch: Set Once
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The Reset Latch: Reset Once
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Set-Reset (SR) Latch
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„
„
„
Two inputs: Set and Reset
Start with both inputs at 1 (memory)
Set to 0 one of the two inputs at a time to store
a value
The transition 00 → 11 generates an undefined
output
CMPE12 – Summer 2008 – Slides by ADB
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Set-Reset (SR) Latch
CMPE12 – Summer 2008 – Slides by ADB
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D-Latch
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„
„
„
D-latch (D for data) is a gated RS latch
Used to store a single data bit
Two inputs: D (data) and WE (write enable)
Q follows D when WE=1; when WE=0, Q is the
latched value
D
WE
D Q
Q
E
Ck
CMPE12 – Summer 2008 – Slides by ADB
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D-Latch: Timing Diagram
1
Ck
D
WE
Ck
D Q
Q
0
time
E
1
WE
0
time
1
D
0
time
1
Q
0
CMPE12 – Summer 2008 – Slides by ADB
time
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D-Flip-Flop
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„
„
„
Two D-latches hooked together
Connect one latch to the inverted clock
D-flip-flop is edge-triggered (changes only on
the edge of the clock)
Also called “edge-triggered d-latch”
D
WE
D Q
Q
E
Ck
CMPE12 – Summer 2008 – Slides by ADB
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D-Flip Flop: Timing Diagram
1
Ck
0
D
WE
D Q
E
Q
time
1
WE
0
Ck
time
1
D
0
time
1
Q
0
CMPE12 – Summer 2008 – Slides by ADB
time
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Flip-Flops in a Pipeline
D
WE
D Q
D Q
E
E
Ck
CMPE12 – Summer 2008 – Slides by ADB
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D-Flip Flops in a Pipeline: Timing Diagram
1
Ck
0
D
WE
D Q
D Q
E
E
time
1
WE
0
Ck
time
1
D
Q
0
time
1
Q1
0
time
1
0
CMPE12 – Summer 2008 – Slides by ADB
time
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Register
„
„
A register stores a multi-bit value
Common WE which latches the n-bit value
CMPE12 – Summer 2008 – Slides by ADB
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Memory
Now that we know how to store bits,
we can build a memory – a logical k × m array of stored
bits.
Address Space:
number of locations
(usually a power of 2)
k = 2n
locations
•
•
•
Addressability:
number of bits per location
(e.g., byte-addressable)
m bits
CMPE12 – Summer 2008 – Slides by ADB
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22 x 3 Memory
word select
address
word WE
input
bits
write
enable
address
decoder
output bits
CMPE12 – Summer 2008 – Slides by ADB
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22 x 3 Memory
1
Ck
0
time
1
WE
0
time
1
A[1:0]
01
0
11
01
00
time
1
D[2:0]
0
CMPE12 – Summer 2008 – Slides by ADB
time
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State Machine
The basic type of sequential circuit
‹ Combines
combinational logic with storage
‹ “Remembers” state, and changes output (and
state) based on inputs and current state
State Machine
Inputs
Combinational
Logic Circuit
Outputs
Storage
Elements
CMPE12 – Summer 2008 – Slides by ADB
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Representing Multi-bit Values
„
Bits are numbered from right (the 0th bit) to left
(the n-1th bit)
‹
„
Just a convention
Range is denoted with brackets
D[a:b] denotes bit a to bit b, inclusive, from left
to right
‹ You may also see A<14:9>, especially in
hardware block diagrams
‹
„
Example:
‹
D = 0101001101010101
CMPE12 – Summer 2008 – Slides by ADB
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Representing Multi-bit Values
„
Example:
‹ D = 0101001101010101
bit
15
10
4
0
D =
0
10100
110101 0101
D[14:10]
D[3:0]
CMPE12 – Summer 2008 – Slides by ADB
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LC-3 Architecture Sneak Preview
CMPE12 – Summer 2008 – Slides by ADB
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LC-3 Data Path
Combinational
Logic
Storage
State Machine
CMPE12 – Summer 2008 – Slides by ADB
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Recommended exercises on Sequential
Circuits
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„
„
Ex 3.19
Ex 3.21, 3.34, 3.35
Ex 3.40, 3.41, 3.43
CMPE12 – Summer 2008 – Slides by ADB
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