The Layered Protocol Wrappers:
A Solution to Streamline Networking
Functions to Process ATM Cells, AAL5
Frames, IP Packets, and UDP Datagrams
Florian Braun, Henry Fu
Washington University
Applied Research Lab
Supported by: NSF ANI-0096052
and Xilinx Corp.
http://www.arl.wustl.edu/arl/projects/fpx/wrappers/
[email protected], [email protected]
The Layered Protocol Wrappers
Florian Braun, Henry Fu
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The Layered Protocol Wrappers
• The Layered Protocol Wrappers Library
– A circuit that streamline the networking
functions to process ATM cells, AAL5 frames,
IP packets, and UDP datagrams
– A layered design that consists different
processing circuit in each layer
– Allows application to be implemented at a level
where important details are exposed and
irrelevant details are hidden
The Layered Protocol Wrappers
Florian Braun, Henry Fu
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Basic Concept of the Protocol Wrappers
Application
Wrapper
Wrapper
The Layered Protocol Wrappers
Florian Braun, Henry Fu
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Overview of the Protocol Wrappers
• The Protocol Wrappers is composed of four
circuits:
– Cell Processor processes raw ATM cells
between network interfaces
– Frame Processor processes variable length
AAL5 frames
– IP Processor processes IP packets
– UDP Processor sends and receives UDP
datagrams
The Layered Protocol Wrappers
Florian Braun, Henry Fu
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Overview of the Layered Protocol Wrappers
Interfaces to Off-Chip Memories
Application-level
Hardware Module
Data
Input
Data
Output
UDP Processor
IP Processor
Frame Processor
Cell Processor
The Layered Protocol Wrappers
Florian Braun, Henry Fu
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The Cell Processor
• The Cell Processor handles ATM Cells, and
provides valid ATM Cells control signals to the
cell level application or the Frame Processor
•
•
•
•
Checks the HEC and drops erroneous cells
Dispatch cells to application or bypass
Handles control cells
Recomputes HEC for outgoing cells
The Layered Protocol Wrappers
Florian Braun, Henry Fu
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The Cell Processor (More)
• Data Flow inside the Cell Processor
HEC
Dispatch
Check
App or
Frame
Processor
HEC
Set
Control
Cells
The Layered Protocol Wrappers
Florian Braun, Henry Fu
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The Frame Processor
• The Frame Processor handles AAL5 frames
and provides valid AAL5 frame control signals
to the application or the IP Processor
–
–
–
Detects AAL5 frame boundaries
Handles CRC
Segments data into cells
The Layered Protocol Wrappers
Florian Braun, Henry Fu
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The Frame Processor (More)
• Data Flow inside the Frame Processor
Frame
AAL5CRC
Detection
The Layered Protocol Wrappers
App or IP
Processor
Cell
Segment
ation
Florian Braun, Henry Fu
AAL5CRC
9
The IP Processor
• The IP Processor handles IP packets and
provides valid IP packet control signals to the
application or the UDP Processor
•
•
•
•
•
•
Verify IP version
Check Header Checksum for application
Drop packet if the Header Checksum fails
Decrease TTL field (ev. ICMP msg)
Signal start of payload (SOP)
Recompute Header Checksum
The Layered Protocol Wrappers
Florian Braun, Henry Fu
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The IP Processor (More)
• Data Flow inside the IP Processor
IP Detect
+
Checksum
TTLDec
The Layered Protocol Wrappers
App or UDP
Processor
Checksum
Florian Braun, Henry Fu
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The IP Processor (More)
• The IP Packet is encapsulated by a ATM Cell
ATM Header
Ver HL ToS
Fragment
TTL Proto Checksum
Source IP address
IP Header
IPID
Packet Length
Destination IP address
Payload
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Florian Braun, Henry Fu
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The UDP Processor
• The UDP Processor handles UDP datagrams
and provide valid UDP datagram signal to the
application
• Check for protocol ID (17)
• Signal start of datagram (SOD)
• Handle UDP checksum
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Florian Braun, Henry Fu
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The UDP Processor (More)
• Data Flow inside the UDP Processor
UDP
Detect
The Layered Protocol Wrappers
App or UDP
Processor
Set
Checksum
Florian Braun, Henry Fu
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The UDP Processor (More)
• The UDP Datagram is encapsulated by a IP
Packet inside an ATM Cell
ATM Header
Ver HL ToS
IPID
Packet Len
Fragment
IP Header
TTL Proto
Checksum
Source IP address
Destination IP address
Src Port
Dest Port
Length
Checksum
UDP Header
Payload
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Florian Braun, Henry Fu
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Synthesis Results
• Required Space and Speed of the Layereed
Protocol Wrappers
Space/LUTs
Cell Processor
Speed/MHz
781
125
Frame Processor
1251
116
IP Processor
1009
109
550
114
UDP Processor
The Layered Protocol Wrappers
Florian Braun, Henry Fu
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Performance Results
Delay for short packages
Delay for long packages
Input
Input
Output
Output
Cell
Processor
4
6
4
6
Frame
Processor
21
22
10
31
IP
Processor
UDP
Processor
36
39
24
197
39
44
27
202
The Layered Protocol Wrappers
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The Layered Protocol Wrappers Package
• The Protocol Wrappers Package
– Detailed Information
• http://www.arl.wustl.edu/arl/projects/fpx/wrappers
– Downloadable TAR File
• http://www.arl.wustl.edu/arl/projects/fpx/wrappers/wrappers.tar
– Technical Report
• http://www.arl.wustl.edu/arl/projects/fpx/wrappers/wucs-01-10.pdf
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Florian Braun, Henry Fu
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Contents of the Layered Protocol Wrappers
• Access the Protocol Wrappers Package
– Cell Processor
• cellwrapper.vhdl, the VHDL instantiation file
• cellproc_sim.vhd, the VHDL simulation file
• cellproc.edn, the EDIF Macro synthesis file
– Frame Processor
• framewrapper.vhdl, the VHDL instantiation file
• frameproc_sim.vhd, the VHDL simulation file
• frameproc.edn, the EDIF Macro synthesis file
The Layered Protocol Wrappers
Florian Braun, Henry Fu
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Contents of the Protocol Wrappers Package
– IP Processor
• ipwrapper.vhdl, the VHDL instantiation file
• ipproc_sim.vhd, the VHDL simulation file
• ipproc.edn, the EDIF Macro synthesis file
– UDP Processor
• udpwrapper.vhdl, the VHDL instantiation file
• udpproc_sim.vhd, the VHDL simulation file
• udpproc.edn, the EDIF Macro synthesis file
– COREGEN Components
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Combining Multiple Processors
• Cell Processor only
Cell Processor
• Cell + Frame Processors
Frame Wrapper
• Cell + Frame + IP Processors
IP Wrapper
• Cell + Frame + IP + UDP Processors
UDP Wrapper
The Layered Protocol Wrappers
Florian Braun, Henry Fu
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Wrappers Example: An UDP Application
UDP Wrapper
Input
UDP
Application
Output
UDP Processor
IP Processor
Frame Processor
Cell Processor
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Florian Braun, Henry Fu
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Building an UDP Application
• The user only needs to handle input signals
from the UDP Wrapper
– Input Signals:
•
•
•
•
•
•
D_MOD_IN (data input)
DataEn_MOD_IN (data enable)
SOF_MOD_IN (start of frame)
SOD_MOD_IN (start of datagram)
EOF_MOD_IN (end of frame)
TCA_MOD_IN (congestion control)
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Building an UDP Application (More)
• Similarly, the user only needs to handle output
signals to the UDP Wrapper
– Output Signals:
•
•
•
•
•
•
D_OUT_MOD (data output)
DataEn_OUT_MOD (data enable)
SOF_OUT_MOD (start of frame)
SOD_OUT_MOD (start of datagram)
EOF_OUT_MOD (end of frame)
TCA_OUT_MOD (congestion control)
The Layered Protocol Wrappers
Florian Braun, Henry Fu
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Building an UDP Application (More)
• Other important input signals
– CLK
• Clock signal for module
• 100 MHz
– Reset_l
• Synchronous reset
• Low for 1 clock cycle to reset state machines
• Set by reconfiguration logic
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Florian Braun, Henry Fu
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Explanation of Control Signals
• SOF_MOD_IN + SOF_OUT_MOD
– High for 1 clock cycle during first ATM header
word
– Signals start of a new AAL5 frame
– Note: HEC is not sent after this signal
• EOF_MOD_IN + EOF_OUT_MOD
– High during 1 clock cycle of last payload word
of datagram
– Followed by the two trailer words of the AAL5
frame
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Florian Braun, Henry Fu
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Explanation of Control Signals (More)
• DataEn_MOD_IN + DataEn_OUT_MOD
– High during valid payload data
– High during trailer words (after EOF)
• SOD_MOD_IN + SOD_OUT_MOD
– High for 1 clock cycle during first word of UDP
header
– UDP payload starts after two valid payload
words (check Data Enable)
– Not enabled if not a UDP packet
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Florian Braun, Henry Fu
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Explanation of Control Signals (More)
• D_MOD_IN + D_OUT_MOD
– 32 bit wide data bus
• TCA_MOD_IN + TCA_OUT_MOD
– TCA signal is high when data can be accepted,
low if no data should be sent
– Wrappers back-propagate TCA to the NID
– Data in pipeline will still be forwarded (~cell
time)
– IP wrapper has big packet buffer for outgoing
data
The Layered Protocol Wrappers
Florian Braun, Henry Fu
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Diagram of Input Signals
CLK
A A
I
I
I
I
I U U D D D D D -
-
A A D D D D D D D P P P F F -
-
A -
I
I
I
I
I U U D D D D D -
-
-
-
SOC
Data
-
D D D D D D D F F -
-
-
-
Cell Level
Data
SOF
IP Level
Frame Level
DataEn
EOF
SOP/
SOD
A ATM Header
I
-
U UDP Header
Don't care
IP Header
The Layered Protocol Wrappers
D Payload Data
P
Padding
F Frame Trailer
Florian Braun, Henry Fu
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Wrapper Example: A Pass-through Circuit
• The Protocol Wrappers Example Package
– Visit
• http://www.arl.wustl.edu/arl/projects/fpx/fpx_kcpsm/
– Download the package
• Right click on WrapperExample.tar.gz
• Save it to h:\
– Start Cygwin Bash Shell
• Engineering > FPGA Tools > Cygwin Bash Shell
The Layered Protocol Wrappers
Florian Braun, Henry Fu
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Wrappers Example: A Pass-through Circuit
– Extract the tar file
•
•
•
•
cd /cygdrive/h/
gunzip WrapperExample.tar.gz
tar xvf WrapperExample.tar
cd WrapperExample
– Examine the content of the package
•
•
•
•
WrapperExample/sim/, simulation directory
WrapperExample/syn/, synthesis directory
WrapperExample/vhdl/, vhdl source directory
WRapperExample/wrappers/, Wrappers directory
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Input / Output Signals of the Module
ENTITY ExampleModule IS
PORT (
-- Clock & Reset
clk
: in STD_LOGIC;
reset_l : in STD_LOGIC;
Enable
Clock
Cell
CellOutput
&
&
Input
Reset
Ready
Interface
-- 100MHz global clock
-- Synchronous reset, asserted-low
-- Enable & Ready
-- Handshake for module reconfiguration.
enable_l : in STD_LOGIC;
-- Asserted low
ready_l : out STD_LOGIC;
-- Asserted low
-- Cell Input Interface
soc_mod_in
: in STD_LOGIC;
d_mod_in
: in STD_LOGIC_VECTOR(31 downto 0);
tca_mod_in
: out STD_LOGIC;
-- Cell Output Interface
soc_out_mod
: out STD_LOGIC;
d_out_mod
: out STD_LOGIC_VECTOR(31 downto 0);
tca_out_mod
: in STD_LOGIC;
-- Start of cell
-- 32-bit data
-- Transmit cell available
-- Start of cell
-- 32-bit data
-- Test Data Output
test_data
: out STD_LOGIC_VECTOR(31 downto 0));
end ExampleModule;
The Layered Protocol Wrappers
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Input / Output Signals of the UDP Wrapper
component udpwrapper
CLK
Reset_l
Enable_l
Ready_l
port (
: in
: in
: in
: out
std_logic;
std_logic;
std_logic;
std_logic;
-----
clock
reset
enable
ready
Coming
Going
Coming
Going
toFrom
from
To
Cell
Cell
Application
Interface
Interface
Input
Interface
Interface
SOC_MOD_IN
D_MOD_IN
TCA_MOD_IN
: in std_logic;
-- start of cell
: in std_logic_vector (31 downto 0); -- data
: out std_logic;
-- transmit cell available
D_OUT_APPL
DataEn_OUT_APPL
SOF_OUT_APPL
EOF_OUT_APPL
SOD_OUT_APPL
TCA_OUT_APPL
:
:
:
:
:
:
out
out
out
out
out
in
std_logic_vector
std_logic;
-std_logic;
-std_logic;
-std_logic;
-std_logic;
--
(31 downto 0); -- data to appl
data enable
start of frame
end of frame
start of datagram
congestion control
D_APPL_IN
DataEn_APPL_IN
SOF_APPL_IN
EOF_APPL_IN
SOD_APPL_IN
TCA_APPL_IN
:
:
:
:
:
:
in
in
in
in
in
out
std_logic_vector
std_logic;
-std_logic;
-std_logic;
-std_logic;
-std_logic;
--
(31 downto 0); -- data from appl
data enable
start of frame
end of frame
start of datagram
congestion control
SOC_OUT_MOD
D_OUT_MOD
TCA_OUT_MOD
end component;
: out std_logic;
-- start of cell
: out std_logic_vector (31 downto 0); -- data
: in std_logic);
-- transmit cell available
The Layered Protocol Wrappers
Florian Braun, Henry Fu
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Input / Output Signals of the ExampleApp
component ExampleApp
port (
CLK
: in
Reset_l
: in
Application only
needs to handle
UDP signals
std_logic;
std_logic;
-- clock
-- reset
D_MOD_IN
DataEn_MOD_IN
SOF_MOD_IN
EOF_MOD_IN
SOD_MOD_IN
TCA_MOD_IN
:
:
:
:
:
:
in
in
in
in
in
out
std_logic_vector (31 downto 0); -- data
std_logic;
-- data enable
std_logic;
-- start of frame
std_logic;
-- end of frame
std_logic;
-- start of datagram
std_logic;
-- congestion control
D_OUT_MOD
DataEn_OUT_MOD
SOF_OUT_MOD
EOF_OUT_MOD
SOD_OUT_MOD
TCA_OUT_MOD
:
:
:
:
:
:
out
out
out
out
out
in
std_logic_vector (31 downto 0); -- data
std_logic;
-- data enable
std_logic;
-- start of frame
std_logic;
-- end of frame
std_logic;
-- start of datagram
std_logic);
-- congestion control
end component;
The Layered Protocol Wrappers
Florian Braun, Henry Fu
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Implementation of the ExampleApp
• Examine the “exampleapp.vhd”
– A flip-flop that passes data and control signals
through
– Can be extended to implement other more
complex network control functions
– Will be used as the framework for the coming
ROT13 exercise
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Florian Braun, Henry Fu
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Simulating the ExampleApp
• Modelsim is used to simulate the ExampleApp
– Go to the simulation directory
• cd WrapperExample/sim/
– Compile the module and start Modelsim
• Make compile
• Make sim
– In Modelsim main window, type:
• do testbench.do
• run 3000
The Layered Protocol Wrappers
Florian Braun, Henry Fu
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Simulating the ExampleApp (More)
• The input data at the line card level
The Layered Protocol Wrappers
Florian Braun, Henry Fu
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Simulating the ExampleApp (More)
• The input data at the UDP Wrapper level
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Florian Braun, Henry Fu
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Simulating the ExampleApp (More)
• The input data at the application level
The Layered Protocol Wrappers
Florian Braun, Henry Fu
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Simulating the ExampleApp (More)
• The output data at the application level
The Layered Protocol Wrappers
Florian Braun, Henry Fu
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Simulating the ExampleApp (More)
• The output data at the UDP Wrapper level
The Layered Protocol Wrappers
Florian Braun, Henry Fu
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Simulating the ExampleApp (More)
• The output data at the line card level
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Florian Braun, Henry Fu
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Conclusion
• In this Layered Protocol Wrappers Example
– Shows the components of the UDP Wrapper
– Shows the function of the UDP Wrapper
– Shows how to instantiate and use the UDP
Wrapper
– Examines the control signals at various levels
of data processing
– Sets up the framework for ROT13 exercise
The Layered Protocol Wrappers
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