EE 319K
Introduction to Microcontrollers
Lecture 1: Introduction,
Embedded Systems, Product
Life-Cycle, ARM Programming
Erez, Gerstlauer, Janapa Reddi, Telang, Tiwari, Valvano, Yerraballi
1-1
Agenda
Course Description
Book, Labs, Equipment
Grading Criteria
Expectations/Responsibilities
Prerequisites
Embedded Systems
Microcontrollers
Product Life Cycle
Analysis, Design, Implementation, Testing
Flowcharts, Data-Flow and Call Graphs
ARM Architecture
Programming
Integrated Development Environment (IDE)
1-2
Useful Info
•
•
No labs this week!
Lab lectures start this Friday
•
•
•
Office hours: see Canvas for most recent?
TAs have office hours too
•
•
2/23 7–8:30 (15%) 4/6 7–8:30 (20%) Final TBD (25%)
Most of the learning is in the labs
•
•
•
•
They are not there to do your work for you
One course == common exams and HW
•
•
F 4–5, M 6:30–7:30 and 7:30-8:30 (ECJ 1.202)
10 labs 30% of grade
HW is important too so 10% for motivation
Read the book and lab manual!
Canvas, Piazza, and
users.ece.utexas.edu/~valvano/Volume1/
1-3
Action Items
• Come introduce yourselves
• Take stock of resources
• Class Website (Volume1)
• Piazza for class discussions
• Email to reach TAs+Me
• E-Book: Search “Valvano e-book”
• Order board
• Install SW
• Read Chapters 1 & 2 of book
1-4
DOs and DON’Ts
DO
DON’T
•Read
•Don’t cheat!
• Book, lab, datasheets
•Try before seeking help
•Follow Piazza/Canvas
•Discuss material with
others
•Homework (not labs) in
groups
•Consult the web
•Track due dates
•Never look at
another student’s
code (current or
previous)
•Don’t let your partner
do all the work
•Don’t copy software
from book or web
without attribution
•Don’t expect
handholding
1-5
EE306 Recap: Digital Logic
+3.3V
p-type
A p-type n-type ~A
0 V active off +3.3V
+3.3V off active 0V A
gate
n-type
gate
source
drain
~A
drain
source
~A
A
74HC04
A
0
1
~A
1
0
 AND, OR, NOT
 Flip flops
 Registers
Positive logic:
True is higher voltage
False is lower voltage
Negative logic :
True is lower voltage
False is higher voltage
1-6
EE306, Also
• Problem solving
• Programming
• Debugging
1-7
EE302 Recap: Ohm’s Law
V=I*R
I=V/R
R=V/I
Voltage = Current * Resistance
Current = Voltage / Resistance
Resistance = Voltage / Current
I = 3.7mA
I
V
R
•P = V * I
•P = V2 / R
•P = I2 * R
Battery
V=3.7V
Power = Voltage * Current
Power = Voltage2 / Resistance
Power = Current2 * Resistance
R = 1k
Resistor
1 amp is 6.241×1018
electrons per second =
1 coulomb/sec
1-8
Embedded System
Medical
Automotive
Communications
Military
 Embedded Systems are
everywhere
 Ubiquitous, invisible
 Hidden (computer inside)
 Dedicated purpose
 Microprocessor
Industrial
Comsumer
Embedded system
Microcontroller
LM3S or TM4C
Processor
I/O Ports
RAM
ROM
Bus
ADC
Electrical,
mechanical,
chemical,
or
optical
devices
DAC
Analog
signals
 Intel: 4004, ..8080,..
x86
 Freescale: 6800, ..
9S12,.. PowerPC
 ARM, DEC, SPARC, MIPS,
PowerPC, Natl. Semi.,…
 Microcontroller
 Processor+Memory+
I/O Ports (Interfaces)
1-9
Microcontroller
 Processor – Instruction Set + memory + accelerators
 Ecosystem
 Memory
 Non-Volatile
o ROM
o EPROM, EEPROM, Flash
 Volatile
o RAM (DRAM, SRAM)
 Interfaces
 H/W: Ports
 S/W: Device Driver
 Parallel, Serial, Analog, Time
 I/O
 Memory-mapped vs. I/O-instructions (I/O-mapped)
1-10
Texas Instruments TM4C123
Cortex M4
Systick
System Bus Interface
NVIC
GPIO Port A
PA7
PA6
PA5/SSI0Tx
PA4/SSI0Rx
PA3/SSI0Fss
PA2/SSI0Clk
PA1/U0Tx
PA0/U0Rx
PC7
PC6
PC5
PC4
PC3/TDO/SWO
PC2/TDI
PC1/TMS/SWDIO
PC0/TCK/SWCLK
Eight
UARTs
Four
I2Cs
Four
SSIs
CAN 2.0
GPIO Port C
GPIO Port D
USB 2.0
Twelve
Timers
JTAG
Six
64-bit wide
GPIO Port E
PE5
PE4
PE3
PE2
PE1
PE0
GPIO Port B
ADC
2 channels
12 inputs
12 bits
Advanced High Performance Bus
PB7
PB6
PB5
PB4
PB3/I2C0SDA
PB2/I2C0SCL
PB1
PB0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
GPIO Port F
Two Analog
Comparators
Two PWM
Modules
ARM Cortex-M4
+ 256K EEPROM
+ 32K RAM
+ JTAG
+ Ports
+ SysTick
+ ADC
+ UART
PF4
PF3
PF2
PF1
PF0
Advanced Peripheral Bus
1-11
LaunchPad Switches and LEDs
R1 0
Serial
R29
+5
0
USB
R25
0
R9
0
R10 0
TM4C123 PF0
PF4
R13 0
PA1
PA0
Green
PB1
PD5
R12
PD4
PF3
PB0
0
PD0
R11
PF2
PB6
0
PD1
R2
PF1
PB7
0
5V
Blue
330
330
Red
330
SW1
SW2
DTC114EET1G
 The switches on the LaunchPad
Negative logic
Require internal pull-up (set bits in PUR)
 The PF3-1 LEDs are positive logic
1-12
I/O Ports and Control Registers
Read from port address
n
n
Processor
DQ
n
GPIO_PORTF_DATA_R
n
Input/Output Port
Write to port address
GPIO_PORTF_DIR_R
Direction bits
n
1 means output
DQ
0 means input
Bus
Write to port direction register
The input/output direction of a bidirectional port
is specified by its direction register.
GPIO_PORTF_DIR_R
, specify if
corresponding pin is input or output:
 0 means input
 1 means output
1-13
I/O Ports and Control Registers
Address
7
6
5
4
3
2
1
0
Name
400F.E608
-
-
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
SYSCTL_RCGCGPIO_R
4002.53FC
-
-
-
DATA
DATA
DATA
DATA
DATA
GPIO_PORTF_DATA_R
4002.5400
-
-
-
DIR
DIR
DIR
DIR
DIR
GPIO_PORTF_DIR_R
4002.5420
-
-
-
SEL
SEL
SEL
SEL
SEL
GPIO_PORTF_AFSEL_R
4002.551C
-
-
-
DEN
DEN
DEN
DEN
DEN
GPIO_PORTF_DEN_R
• Initialization (executed once at beginning)
1. Turn on clock in SYSCTL_RCGCGPIO_R
2. Wait two bus cycles (two NOP instructions)
3. Unlock PF0 (PD7 also needs unlocking)
4. Set DIR to 1 for output or 0 for input
5. Clear AFSEL bits to 0 to select regular I/O
6. Set PUE bits to 1 to enable internal pull-up
7. Set DEN bits to 1 to enable data pins
• Input/output from pin
6. Read/write GPIO_PORTF_DATA_R
1-14
Product Life Cycle
• Specifications
• Constraints
Requirements
Constraints
Design
Analyze
the
problem
• Block diagrams
• Data flow graphs
Development
New requirements
New constraints
Deployment
Done
Testing
• Hardware
• Software
Implementation(Real)
Analysis (What?)
Hardware, Software
Requirements ->
Specifications
Testing (Works?)
Design (How?)
Validation:Correctness
High-Level: Block Diagrams
Performance: Efficiency
Engineering: Algorithms,
Maintenance (Improve)
Data Structures, Interfacing
1-15
Data Flow Graph
Lab 8: Position Measurement System
Position Voltage
0 to 2 cm 0 to +3.3V
Position
Sensor
Sample
0 to 4095
ADC
hardware
Sample
0 to 4095
ADC
driver
SysTick
ISR
SysTick
hardware
LCD
display
LCD
driver
Mailbox
main
Fixed-point
0 to 2.000
1-16
Call Flow Graph
Position Measurement System
SysTick
ISR
main
SysTick
init
ADC
driver
SysTick
hardware
ADC
hardware
LCD
driver
LCD
hardware
1-17
Structured Programming
Common Constructs (as Flowcharts)
Sequence
Conditional
While-loop
Block 1
Block 2
Parallel
Fork
Join
Block 1
Block 2
Distributed
Block
Interrupt-driven concurrent
Trigger
main
interrupt
main1
main2
Init1
Init2
Init
Body1
Body2
Body
Return from
interrupt
1-18
Flowchart
Toaster oven:
Cook
main
Output heat
is on
Input from
switch
Start
Not pressed
Input toast
temperature
Pressed
Cook
Too cold
toast < desired
toast  desired
Output heat
is off
return
Coding in assembly and/or high-level language (C)
1-19
Flowchart

Example 1.3. Design a flowchart for a system that performs two independent
tasks. The first task is to output a 20 kHz square wave on PORTA in real time
(period is 50 ms). The second task is to read a value from PORTB, divide the
value by 4, add 12, and output the result on PORTD. This second task is repeated
over and over.
main
A
Input n from B
PORTB
n = (n/4)+12
C
Output n to
PORTD
D
Clock
PORTA =
PORTA^1
<
E
>
void SysTick_Handler(void){
PORTA = PORTA^0x01;
E
}
>
void main(void){
unsigned long n;
while(1){
n = PORTB;
n = (n/4)+12;
PORTD = n;
}
}
A
B
C
D
1-20
ARM Cortex M4-based System
System bus
Microcontroller
ARM® CortexTM-M
processor
Input
ports
PPB
Internal
peripherals
Advanced
High-perf
Bus
Instructions
Flash ROM
ICode bus
DCode bus
Output
ports
Data
RAM
 ARM Cortex-M4 processor
 Harvard architecture
 Different busses for instructions and data
1-21
ARM Cortex M4-based System
 RISC machine
 Pipelining effectively provides single cycle operation for many instructions
 Thumb-2 configuration employs both 16 and 32 bit instructions
CISC
Many instructions
Instructions have varying lengths
Instructions execute in varying times
Many instructions can access memory
In one instruction, the processor can both
 read memory and
 write memory
Fewer and more specialized registers.
 some registers contain data,
 others contain addresses
Many different types of addressing modes
RISC
Few instructions
Instructions have fixed lengths
Instructions execute in 1 or 2 bus cycles
Few instructions can access memory
 Load from memory to a register
 Store from register to memory
No one instruction can both read and write
memory in the same instruction
Many identical general purpose registers
Limited number of addressing modes
 register,
 immediate, and
 indexed.
1-22
ARM ISA: Thumb2 Instruction Set
 Variable-length instructions
ARM instructions are a fixed
length of 32 bits
Thumb instructions are a fixed
length of 16 bits
Thumb-2 instructions can be
either 16-bit or 32-bit
 Thumb-2 gives approximately 26%
improvement in code density over
ARM
 Thumb-2 gives approximately 25%
improvement in performance over
Thumb
1-23
ARM ISA: Registers, Memory-map
General
purpose
registers
Stack pointer
Link register
Program counter
Condition Code Bits
N negative
Z zero
V overflow
C carry
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13 (MSP)
R14 (LR)
R15 (PC)
Indicates
Result is negative
Result is zero
Signed overflow
Unsigned overflow
256k Flash
ROM
32k RAM
0x0000.0000
0x0003.FFFF
0x2000.0000
0x2000.7FFF
I/O ports
0x4000.0000
0x400F.FFFF
Internal I/O
PPB
0xE000.0000
0xE004.1FFF
TI TM4C123
Microcontroller
1-24
LC3 to ARM - Data Movement
LEA R0, Label
;R0 <- PC + Offset to Label
ADR R0,Label or LDR R0,=Label
LD
R1,Label
LDR R0,=Label
LDRH R1,[R0]
LDR R1,R0,n
; R1 <- M[PC + Offset]
; Two steps: (i) Get address into R0
; (ii) Get content of address [R0] into R1
; R1 <- M[R0+n]
LDRH R1,[R0,#n]
LDI
R1,Label
; R1 <- M[M[PC + Offset]]
; Three steps!!
ST R1,Label
LDR R0,=Label
STRH R1,[R0]
STR R1,R0,n
; R1 -> M[PC + Offset]
; Two steps: (i)Get address into R0
; (ii) Put R1 contents into address in R0
; R1 -> M[R0+n]
STRH R1,[R0,#n]
STI R1,Label
; R1 -> M[M[PC + Offset]]
; Three steps!!
1-25
LC3 to ARM – Arithmetic/Logic
ADD R1, R2, R3
ADD R1,R2,R3
ADD R1,R2,#5
ADD R1,R2,#5
AND R1,R2,R3
AND R1, R2, R3
; R1 <- R2 + R3
; 32-bit only
; R1 <- R2 + 5
; 32-bit only, Immediate is 12-bit
; R1 <- R2 & R3
; 32-bit only
AND R1,R2,#1
AND R1, R2, #1
; R1 <- Bit 0 of R2
; 32-bit only
NOT R1,R2
; R1 -> ~(R2)
EOR R1,R2,#-1
; -1 is 0xFFFFFFFF,
; so bit XOR with 1 gives complement
1-26
LC3 to ARM – Control
BR Target
; PC <- Address of Target
B Target
BRnzp Target
; PC <- Address of Target
B Target
BRn Target
BMI Target
BRz Target
; PC <- Address of Target if N=1
; Branch on Minus
; PC <- Address of Target if Z=1
BEQ Target
BRp Target
; PC <- Address of Target if P=1
No Equivalent
BRnp Target
; PC <- Address of Target if Z=0
BNE Target
BRzp Target
BPL Target
BRnz Target
; PC <- Address of Target if N=0
; Branch on positive or zero (Plus)
; PC <- Address of Target if P=0
No Equivalent
1-27
LC3 to ARM – Subs,TRAP,Interrupt
JSR Sub
BL Sub
JSRR R4
BLX R4
RET
BX LR
JMP R2
BX R2
TRAP x25
; PC <- Address of Sub, Return address in R7
; PC<-Address of Sub, Ret. Addr in R14 (Link Reg)
; PC <- R4, Return address in R7
; PC <-R4, Return address in R14 (Link Reg)
; PC <- R7 (Implicit JMP to address in R7)
; PC <- R14 (Link Reg)
; PC <- R2
; PC <- R14 (Link Reg)
; PC <- M[x0025], Return address in R7
SVC #0x25 ; Similar in concept but not implementation
RTI
BX LR
; Pop PC and PSR from Supervisor Stack…
; PC <- R14 (Link Reg) [same as RET]
1-28
ARM is a Load-Store machine
Code to set (to 1) bit 5 of memory address x400FE608
SYSCTL_RCGCGPIO_R EQU
0x400FE608
; EQU psedo-op allows use of
; symbolic name to represent a constant
LDR R1, =SYSCTL_RCGCGPIO_R
; R1 holds x400FE608
LDR R0, [R1]
; R0 holds contents of
; location x400FE608
ORR R0, R0, #0x20
; bit5 of R0 is set to 1
STR R0, [R1]
; write R0 contents back to
; location x400FE608
1-29
SW Development Environment
Editor
Source code
KeilTM uVision®
Start
; direction register
LDR R1,=GPIO_PORTD_DIR_R
LDR R0,[R1]
ORR R0,R0,#0x0F
; make PD3-0 output
STR R0, [R1]
Start
Debug
Session
Simulated
Microcontroller
Processor
Memory
I/O
Build Target (F7)
Object code
0x00000142
0x00000144
0x00000146
0x0000014A
4912
6808
F040000F
6008
Address Data
Download
Real
Microcontroller
Start
Debug
Session
Processor
Memory
I/O
1-30