WEEK #10
Synthesis of Sequential Logic
Prepared by SITI ZARINA MD NAZIRI
Sources: SLIDES FROM RIZALAFANDE, CILETTI
SYNTHESIS OF SEQUENTIAL LOGIC – DESIGN
OPTIONS
DESIGN OPTIONS FOR SEQUENTIAL LOGIC
User Defined Primitives (UDPs)
Behaviors with Timing Controls
Instantiated Library Register Cells
Instantiated Modules
SYNTHESIZED SEQUENTIAL FUNCTIONAL UNITS
Sequential UDPs
Edge-Triggered Flip-Flops
Latches
Explicit FSMs
Implicit FSMs
Mealy-Moore Machines
SYNTHESIS OF SEQUENTIAL UDPs
• When using UDPs, synthesis tool must first
recognize the input (either value (for a latch)
or edge transition (for a flip-flop)) which
controls the datapath through the primitive
• Sequential UDP must have only one control
signal (either clock or enable pin)
• May also contain asynchronous control
signals (for set or reset)
SYNTHESIS OF SEQUENTIAL UDPs
module jk_flop (q, clk, j, k, clr);
output q;
input
clk, j, k, clr;
jk_udp (q, clk, j, k, clr);
endmodule
primitive jk_udp (clk, q, j, k, clr);
output q;
input
clk, j, k, clr;
reg q;
Synthesis result
table
// clk j k
? ? ?
f 0 0
f 0 1
f 1 0
f 1 1
f 1 1
r ? ?
? * ?
? ? *
? ? ?
endtable
endprimitive
clr
0
1
1
1
1
1
?
?
?
*
:
:
:
:
:
:
:
:
:
:
q
?
?
?
?
0
1
?
?
?
?
Synthesize as DFF
with additional logics
Example: J-K Flip Flop
next
: 0;
: -;
: 0;
: 1;
: 1;
: 0;
: -;
: -;
: -;
: -;
SYNTHESIS OF LATCHES
• Level-sensitive (latched) behavior is
characterized by an output which affected by
input only while a control signal is asserted
• At other times, the input is ignored and the
output remains its residual value
• Latches inferred by the synthesis tool when it
detects an incomplete ‘if’ statement in a
behavior
SYNTHESIS OF LATCHES
Example:
Unwanted latch
Incomplete statement
based on 3 inputs
Latch results from
incomplete case statement
Synthesis result
SYNTHESIS OF EDGE-TRIGGERED FLIP-FLOPS
• Register variable will be synthesized as
the output of a flip-flop when its value is
assigned synchronously with the edge of a
signal
• If the event control expression is sensitive to
the edge of more than one signal, an ‘if’
statement must be the first statement in the
behavior
• The control signal (reset or set) must be
declared explicitly in the branches of the ‘if’
statement (e.g. decode the reset condition
first), whereas the synchronizing signal
declared implicitly in the branches
SYNTHESIS OF EDGE-TRIGGERED FLIP-FLOPS
module jk_flop_1 (j, k, clock, rst, q, qb);
input j, k, clock, rst;
output q, qb;
reg q;
assign qb = ~q;
always @ (posedge rst or posedge clock)
begin
if (rst == 1'b1) q = 1'b0; else // rst first
Synthesis result
if (j == 1'b0 && k == 1'b0) q = q; else
if (j == 1'b0 && k == 1'b1) q = 1'b0; else
if (j == 1'b1 && k == 1'b0) q = 1'b1; else
if (j == 1'b1 && k == 1'b1) q = ~q;
end
endmodule
case {j, k}
Both cases generates the
2'b00: q = q;
same synthesis product
2'b01: q = 1'b0;
2'b10: q = 1'b1;
2'b11: q = ~q;
end
Example: J-K Flip
Flop
SYNTHESIS OF EDGE-TRIGGERED FLIP-FLOPS
module D_reg4a (Data_in, clock, reset, Data_out);
input [3:0] Data_in;
input clock, reset;
output [3:0] Data_out;
reg [3:0] Data_out;
always @ (posedge reset or posedge clock)
begin
if (reset == 1'b1) Data_out <= 4'b0;
else Data_out <= Data_in;
end
endmodule
Synthesis
result
Example: 4-bit Parallel Load Data Register
REGISTERED COMBINATIONAL LOGIC
• When cyclic behavior that implements
combinational logic is changed to be
sensitive to clock, the outputs of the logic
will be registered
• These new outputs will be taken from DFF
which then synchronize with the clock signal
Variables assigned value within a
synchronous behavior will be registered
REGISTERED COMBINATIONAL LOGIC
module reg_and (a, b, c, clk, y);
input a, b, c, clk;
output y;
reg y;
Combinational logic operation
which is sensitive to clock
always @ (posedge clk)
begin
y <= a & b & c;
end
endmodule
Synthesis result
Example: ‘And’ gate with registered output
REGISTERED COMBINATIONAL LOGIC
module mux_reg (a, b, c, d, y, select, clock);
input [7:0] a, b, c, d;
output [7:0] y;
input [1:0] select;
reg [7:0] y;
always @(posedge clock)
case (select)
0: y <= a; // non-blocking
1: y <= b; // same result with =
2: y <= c;
3: y <= d;
default y <= 8'bx;
endcase
endmodule
Synthesis result
Example: Multiplexer with registered output
REGISTERED COMBINATIONAL LOGIC
Circuit synthesized by
synthesis tool
8 DFF as output registers
for each 4-channel mux
Example:
Multiplexer with
registered output
SHIFT REGISTERS AND COUNTERS
• Synthesis tools easily synthesize a
variety of counters and shift registers from
Verilog behavioral descriptions
• The physical size of an ASIC that is
synthesized from Verilog is not necessarily
proportional to the size of the source code,
e.g:
always @ (posedge clock)
begin
data_register <= data_bus;
end
data_register could be
a single bit or a 32-bit
register
SHIFT REGISTERS AND COUNTERS
module Shift_reg4 (Data_out, Data_in, clock, reset);
input Data_in, clock, reset;
output Data_out;
NOTE:
reg [3:0] Data_reg;
In this example the register
variable is used (referenced),
assign Data_out = Data_reg[0];
through concatenation, before
it is assigned value in the
always @ (negedge reset or posedge clock)
synchronous behavior. This
begin
will synthesize to a flip flop.
if (reset == 1'b0) Data_reg <= 4'b0;
else Data_reg <= {Data_in, Data_reg[3:1]};
end
endmodule
Example: 4-bit Shift Register
SHIFT REGISTERS AND COUNTERS
Example:
4-bit Ripple Counter
NOTE:
c0, c1, and c2 are used to
provide a scalar variable to
the event control expressions
SHIFT REGISTERS AND COUNTERS
Example: 4-bit Ripple Counter (cont..)
Structure
Synthesize
circuit
SYNTHESIS OF FINITE STATE MACHINES (FSM)
• Most often used constructs in
specifying sequential logic
• Remember? Moore & Mealy machines..
Mealy
Moore
SYNTHESIS OF FSM
General rules to be followed in synthesizing FSM:
• States
– Coded & declared as parameters  allow the use of symbolic
names for states & assigning them to state variables
• Next state (NS) logics
– Combinatorial block specified either in combinatorial
‘always’ block or function, contains case statements –
specify every branch with next state
• State registers
– Specified in separate ‘always’ block which must be clocked
– Only statement is the assignment for NS on active clock
edge
• Output logic
– Can be specified either together with NS logic or separate
block (latter is better in terms of readability & synthesis)
SYNTHESIS OF FSM
Synthesis tools can synthesize 2
styles of FSM descriptions:
• EXPLICIT FSM
– Specify a sequence of states
– State register holds encoded representation of
the state
– Explicit assignments to state register to control
state sequence
• IMPLICIT FSM
– Specify an evolution of states
– No explicit state register
– The activity flow within the behavior implies the
sequence of states
SYNTHESIS OF FSM
Example: Speed Controller
SYNTHESIS OF FSM – Explicit FSM
Example: Speed Controller
SYNTHESIS OF FSM – Implicit FSM
Example: Speed Controller
SYNTHESIS OF FSM – Alternative
Example: Speed Controller
SYNTHESIS OF FSM – Explicit vs Implicit
Explicit FSM
Implicit FSM
Explicit State
Register
Yes
No
State
Encoding
Yes
No
Sequence of
State
Specified
Implicit
Sequence
Control
Explicit
assignment to
state register
Specified by
procedural
flow
SYNTHESIS OF FSM – State Encoding
• State encoding produced by a synthesis tool
might not be optimal
• User intervention might be necessary
• Consider alternative styles for encoding, userselected or tool selected.
• Simple binary codes: Use a minimal number of FFs but may not
lead to optimal realization of a state machine's combinational
logic
• Gray codes: Two adjacent codes differ by only one bit
Benefits:
– Reduced simultaneous switching of adjacent signals
– Minimal transitions through intermediate states (multiple flops
transitions would have intermediate state transitions and possible
output glitches)
• Johnson Codes: Expanded code, but adjacent (next) codes
differ by only one bit
SYNTHESIS OF FSM – One-Hots
• One-hot code example:
`define state_0 3'b001
`define state_1 3'b010
`define state_2 3'b100
• Use ‘if’ statement to decode state (the ‘case’
statement implicitly references all of the registers to
decode the state)
• One-hot codes assign a register bit for every state
• Tradeoffs:
– Reduced complexity of decoding logic offsets area cost of
the additional flip-flops
• Speed not dependent on decoding logic
• Easy to modify the design – state codings are
uncoupled
• Use in FPGA-based designs (fixed D-flop resources)
• Caution: Cover the all-zero state in the STG
RESETS
• Recommended: Use Reset signal in
design to drive a system to a known initial
state (either asynch/sync)
• Procedural continuous assignment statement
(PCA) (assign .. deassign) support
description of reset signal
– Some vendors require reset to be
implemented using ‘if’ statement
• If reset conditions are not complete at each
clock, synthesizer will synthesize additional
(wasted) logic
RESETS
always @(negedge clock or negedge
reset or posedge set)
always @ (posedge clk or posedge reset or negedge set)
if (reset ==1) q = 0; // asynchronous branch
else if (set == 0) q = 1; // asynchronous branch
else q = data; // No additional clock delays are allowed
// in the synchronous branch.
NOTE: This style cannot be used for implicit
FSMs that have more than one event control
expression. This style is less efficient for
simulation than the assign ... deassign style.
RESETS
Synthesis result with
partial reset/load
- More logics generated
Synthesis result with full
reset/load
- Reduced logics
Example: Moore machine sequence detector (Ex. 9.22 in Ciletti)
SYNTHESIS OF GATED CLOCKS
• Recommended practice: Avoid using gated
clocks because it leads to timing problems
 skew the clock path & pulsewidth problem
• FF is recommended to be triggered only by a
non-gated clock signal & a reset signal
(synch/asynch)
• However, the usage of gated clock on CMOS
ASICs can lead to low power ASICs design
SYNTHESIS OF GATED CLOCKS
Module best_gated_clk (clk, reset, data_gate,data, Q)
input clk, reset, data, data_gate;
output Q;
reg Q;
always @ (posedge clk or negedge reset)
if (reset == 0)
Q = 0;
else if (data_gate)
Q = data;
endmodule
Synthesizable gated clock
• The code will multiplex the data with the output of
FF
– Data_gate asserted – data is routed to input of FF
– Data_gate de-asserted – output of FF unchange
DESIGN PARTITIONS & HIERARCHICAL
STRUCTURES
• Partitioning: dividing circuits into small
functional units (using top-down approach)
• Advantages of partitioning
– Improve synthesis result
– Shorten optimization cycle
– Simplify synthesis process (5k-10k gates)
• Group functional-related logic into a partition
– Synthesis tool will able to exploit opportunities for
sharing logic
– Module used in multiple places in design should
be optimized separately & instantiated as needed
• Improves efficiency in terms of area & CPU time
DESIGN PARTITIONS & HIERARCHICAL
STRUCTURES
• Group registers & their logics in a partition
– Control logic can be implemented efficiently
– Placing logic into single module allows synthesis
tool to exploit common logic
• Module boundaries in Verilog
– Only hierarchical boundaries in Verilog
– Synthesis tools have variety options handling the
hierarchy
– E.g. all module instances are flattened into parent
module (done by most tools)
DESIGN PARTITIONS & HIERARCHICAL
STRUCTURES
• Synthesis tools
– Can preserve contents of module on instance
basis or preserve the underlying hierarchical
substructure
– Interactive tool allow designer to partition & repartition design
– Reducing scope of synthesis process will reduces
the tools’ logic optimization ability
– Tools cannot share logic between modules whose
boundaries have been preserved
DESIGN PARTITIONS & HIERARCHICAL
STRUCTURES
• Partition mixing
– Partition of design should not co-locate logics
with conflicts in optimizing objectives
• Logics which is optimized for speed should not be mixed
with logics which is optimized for area
• Clocks, i/o pads, JTAG (i.e. boundary scan)
registers should not be included in design
that is to be synthesized
– Add after synthesis
– i/o pads, clocks – not synthesizable
– Clock – may result skew & other timing issue
SUMMARY
• Verilog supports variety descriptive styles
that synthesize into sequential logic
• Latches are result of incomplete decode of behavior
synthesis
• Behaviors with no timing controls & which
completely decode their inputs will synthesized into
combinational logic
• Register variables referenced before they are
assigned value will synthesize in hardware storage
element
• Register variables referenced in assignment outside
behavior will synthesize to storage element
• Not all constructs in Verilog can be synthesize, & not
all construct are supported by synthesis tool vendors