High Performance Logic Devices
2nd Advanced Course on Diagnostics and Data Acquisition
Bernardo Brotas Carvalho
[email protected]
Instituto de Plasmas e Fusão Nuclear
Instituto Superior Técnico
Lisbon, Portugal
http://www.ipfn.ist.utl.pt
B.B. Carvalho | Lisbon, February 16, 2009 | Diagnostics & Data Acquisition
Programmable logic devices
• Some history
• Digital Logic Circuits (state machines,
controllers, counters, registers, and
decoders, etc..)
• Lots of SSI (small-scale integration)
chips (7400-series parts)
2
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
PROM as Combinatorial Circuits
Address Lines
(input)
a0
a1
a2
Data Lines
(outputs)
1 0 1 0 0 1 1 0
0 0 1 1 1 1 0 0
1 0 1 0 0 1 1 1
b0
b1
b2
Example:
(a2, a1, a0 ) = (010) ->b0 = 1
Have to decode ALL the input combinations. Very inefficient
3
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xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
Programmable Array Logic (PAL)
Are the basis of some of the newer,
more sophisticated architectures
Fixed-OR, programmable-AND Plane
a0
X
a1
X
b0
X
X
Example:
b0 =F(a1, a0) = a1. a0 + a1. a0
4
PLA had TWO two levels of programmable logic
an AND plane and an OR plane
(more expense to manufacturing and
poor speed performance)
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
PAL Configurations
•PAL16L8 = 8 combinational outputs
•PAL16R8 = 8 registered outputs
•PAL16V8 = 8 “variable” outputs
PAL 16R4 Block Diagram
5
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xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
PAL Programming Languages
PALASM
TITLE video ; shift register
CHIP video PAL20V8
CK /LD D0 D1 D2 D3 D4 D5 D6 D7 CURS GND NC REV Q7 Q6 Q5 Q4
Q3 Q2 Q1 Q0 /RST VCC (PAL pins in numerical order starting with
pin 1 )
STRING Load 'LD*/REV*/CURS*RST' ; load data (Comment )
STRING LoadInv 'LD*REV*/CURS*RST' ; load inverted of data
STRING Shift '/LD*/CURS*/RST' ; shift data from MSB to LSB
EQUATIONS
/Q0 := /D0*Load+D0*LoadInv:+:/Q1*Shift+RST (Registered assignment )
Q6
= D1 + /D2
(Combinatorial assignment )
6
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
PAL Programming Languages
•
ABEL (Advanced Boolean Expression Language)
module MUX4
title '4:1 MUX'
MyDevice device 'P16L8' ;
@ALTERNATE
"inputs
A, B, /P1G1, /P1G2 pin 17,18,1,6 "LS153 pins 14,2,1,15
P1C0, P1C1, P1C2, P1C3 pin 2,3,4,5 "LS153 pins 6,5,4,3
P2C0, P2C1, P2C2, P2C3 pin 7,8,9,11 "LS153 pins 10,11,12,13
"outputs
P1Y, P2Y pin 19, 12 "LS153 pins 7,9
equations
P1Y = P1G*(/B*/A*P1C0 + /B*A*P1C1 + B*/A*P1C2 + B*A*P1C3);
P1Y = P1G*(/B*/A*P1C0 + /B*A*P1C1 + B*/A*P1C2 + B*A*P1C3);
end MUX4
7
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
SPLD Programming Cycle
8
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Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
Programming PALs
• PROM ( blow fuses permanently)
• E-PROM (UV erasable PROM)
• Specialized/universal device programmer
9
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
Complex Programmable Logic Devices (CPLDs)
I/O
I/O
I/O
I/O
PAL (eg 22V10)
Internal structure of a CPLD
CPLDs provide logic capacity
up to the equivalent of about 50 typical
SPLD devices
Typical I/O Block
10
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B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
FPGA Architecture
Logic
Block
A bunch of simple, configurable logic
blocks arranged in an array with
interspersed switches that can
rearrange the interconnections
between the logic blocks
Interconnection
Resources
Additionally, clock circuitry for driving
the clock signals to
each logic block, and additional logic
resources such as ALUs, memory, and
Decoders or full microprocessors
Switch
Matrix
11
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
Simplified view of a FPGA Logic Cell
16-bit SR
16x1 RAM
a
b
c
d
e
4-input
LUT
y
mux
flip-flop
q
clock
clock enable
set/reset
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
12
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
LUT (Look-Up Table) Functionality
x1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x1
x2
x3
x4
y
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
LUT
y
x1 x2 x3 x4
x1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
y
0
1
0
0
0
1
0
1
0
1
0
0
1
1
0
0
• Look-Up tables
are primary
elements for
logic
implementation
• Each LUT can
implement any
function of 4
inputs
x1 x2
y
y
13
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
Basic I/O Block Structure
D Q
EC
Three-State
FF Enable
Clock
SR
Three-State
Control
Set/Reset
D Q
EC
Output
FF Enable
Output Path
SR
Direct Input
FF Enable
Registered
Input
Q
D
EC
Input Path
SR
14
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
IOB Functionality
• IOB provides interface between the
package pins and CLBs
• Each IOB can work as uni- or bi-directional
I/O
• Outputs can be forced into High
Impedance
• Inputs and outputs can be registered
– advised for high-performance I/O
• Inputs can be delayed
15
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
PLD Programming Technologies
EPROM “AND” GATE
SRAM
Anti-Fuse
FPGA
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name | Place,
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xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
Logic Capacities of PLD
Built-in PowerPC® Hard processor
Virtex-II
1000
Virtex-II
3000
Spartan-3
1000
Spartan-3
1000
Virtex-5
LX30
Virtex-5
LX30
Gates
1 million
3 million
1 million
2 million
-
-
FlipFlops
10,240
28,672
15,360
40,960
19,200
28,800
LUTs
10,240
28,672
15,360
40,960
19,200
28,800
Multipliers
40
96
24
40
32
48
Block
RAM
(kb)
720
1728
432
720
1152
1728
Present FPGA Resource Specifications for
XILINX Families
~1995
17
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
Major FPGA vendors
SRAM-based FPGAs
Xilinx Inc.
– www.xilinx.com
Altera Corp.
– www.altera.com
Atmel Corp.
– www.atmel.com
Lattice Semiconductor Corp.
– www.latticesemi.com
Antifuse and flash-based FPGAs
Actel Corp.
– www.actel.com
QuickLogic Corp. – www.quicklogic.com
18
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xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
The Programmable Marketplace
Q1 Calendar Year 2005
PLD Segment
Actel
Lattice
5% 7%
FPGA Sub-Segment
Xilinx
QuickLogic: 2%
Other: 2%
58%
33%
51%
31%
Altera
Xilinx
Altera
11%
All Others
Two dominant suppliers, indicating a maturing market
Source: Company reports
Latest information available; computed on a 4-quarter rolling basis
19
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
Benefits of FPGA Technology
• Performance (hardware parallelism, )
• Time to market (Commercial off-the-shelf
(COTS) hardware)
• Cost
• Reliability (No OS. Deterministic hardware
dedicated to every task)
• Long-term maintenance
20
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
Applications of FPGAs
• Digital signal processing, software-defined
radio, aerospace, Defense system,
medical imaging, computer vision, speech
recognition, cryptography, bioinformatics,
computer hardware emulation
• glue logic for PCBs
• Full systems on chips (SoC)
• High performance computing (FFT or
Convolution, massive parallelism)
21
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
Timing Characteristics of
Combinational Circuits
• Combinational Circuits Are
Characterized by Propagation Delays
• through logic components (gates, LUTs)
• through interconnects (routing delays)
LUT
tp LUT
LUT
LUT
tp routing
Total propagation delay through combinational logic
22
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
Timing Characteristics of Combinational
Circuits (2)
• Total Propagation Delay of Logic
Depends on the Number of Logic
Levels and Delays of Logic
Components
• Number of logic levels is the number of
logic components (gates, LUTs) the signal
propagates through
• Routing Delays Depend on:
• Length of interconnects
• Fanout
23
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
Timing Characteristics of
Combinational Circuits (3)
• Fanout – Number of Inputs Connected
to One Output
• Each inputs has its capacitance
• Fast switching of outputs with high fanout
requires higher currents and strong
drivers
LUT
LUT
LUT
24
LUT
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
Timing Characteristics of
Combinational Circuits (4)
• In Current Technologies Routing
Delays Make 45-65% of the Total
Propagation Delays
25
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
Timing Characteristics of
Sequential Circuits (1)
• Timing Features of Flip-flops
• Setup time tS – minimum time the input
has to be stable before the rising edge of
the clock
• Hold time tH – minimum time the input has
to be stable after the rising edge of the
clock
• Propagation delay tP – time to propagate
input to output after the rising edge of the
clock
26
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
Timing Characteristics of
Sequential Circuits (2)
Input D must remain
stable during
this interval
D
clk
Q
Input D can freely
change during
this interval
clk
D
tS
tH
Q
tP
27
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
FPGA Design Flow
Register Transfer
Level
http://www.bitsim.com/fpga-design-flow.htm
28
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Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
Hardware description languages
•
•
•
•
29
Verilog
VHDL
System C
System Verilog
“Low Level” ( assembly)
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
Introduction to VHDL
• Developed at the US Department of
Defense
• Strongly-typed and is not case sensitive.
• IEEE standard 1076-1987
• Allows to describe both the behavior of the
required system AND the respective
Testbench
30
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
VHDL CODE examples
-- (this is a VHDL comment)
-- import std_logic from the IEEE library
library IEEE;
use IEEE.std_logic_1164.all;
Inputs
-- this is the entity
entity ANDGATE is
port (
IN1 : in std_logic;
IN2 : in std_logic;
OUT1: out std_logic);
end ANDGATE;
architecture
Outputs
architecture RTL of ANDGATE is
begin
OUT1 <= IN1 and IN2;
end RTL;
31
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Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
MUX in VDHL
-- template 1:
X <= A when S = '1' else B;
-- template 2:
with S select X <= A when '1' else
B;
-- template 3:
process(A,B,S)
begin
case S is
when '1' => X <= A;
when others => X <= B;
end case;
end process;
32
-- template 4:
process(A,B,S)
begin
if S = '1' then
X <= A;
else
X <= B;
end if;
end process;
-- template 5 - 4:1 MUX, where S is a 2-bit
std_logic_vector :
process(A,B,C,D,S)
begin
case S is
when "00" => X <= A;
when "01" => X <= B;
when "10" => X <= C;
when others => X <= D; -- or when "11"
end case;
end process;
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
Counter Example
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all; -- for the unsigned type
entity counter_example is
generic ( WIDTH : integer := 32);
port (
CLK, RESET, LOAD : in std_logic;
DATA : in unsigned(WIDTH-1 downto 0);
Q : out unsigned(WIDTH-1 downto 0));
end entity counter_example;
architecture RTL of counter_example is
signal cnt : unsigned(WIDTH-1 downto 0);
begin
process(RESET, CLK)
begin
if RESET = '1' then
cnt <= (others => '0');
elsif rising_edge(CLK) then
if LOAD = '1' then
cnt <= DATA;
else
cnt <= cnt + 1;
end if;
end if;
end process;
Q <= cnt;
end architecture RTL;
33
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
Hierarchical design
VHDL allows a hierarchy of entities containing components.
At each level VHDL allows multiple architectures and multiple
configurations for each entity.
Top Design
Component 1
Component 2
Component 3
34
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
Hierarchical design in VHDL
• Hierarchical design:
architecture STRUCT of INC is
signal X,Y,S,C : bit;
component HALFADD (defined in HALFADD.vhdl)
port(A,B : in bit;
SUM, CARRY : out bit);
end component;
begin
U1: HALFADD port map (X,Y,S,C);(instance)
-- other statements
end STRUCT;
35
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data
36
name | Place,
Month Acquisition
xx, 2007 | Event
B.B. Carvalho | Lisbon, February 17, 2009 |Author’s
Diagnostics
& Data