ECE 4480/5480 Computer Architecture and Design
Spring 2015
Midterm
Name: _____________________solution__________________(print please)
1. Using the five-stage pipelined MIPS processor without any forwarding function, we run the
following program on this pipelined processor. We also assume that the control unit is able to
stall the pipelined processor upon detection of a hazard. Register read takes one clock cycle and
the register write takes one clock cycle.
Instruction no
1
2
3
4
sub $2, $1, $3
add $11, $2, $5
lw $7, 100($11)
sw $7, 100($8)
Fill in the following table, using F, D, E, M, W, and S to represent instruction fetch, decoding,
execution, memory access, write back and stall the processor.
Clock cycles are denoted as c1, c2, … etc. Program starts at c1
C1
F
C2
D
F
C3
E
D
F
C4
M
S
D
F
C5
W
S
S
D
C6
C7
C8
C9
C10 C11 C12 C13 C14 C15 C16 C17
D
S
S
E
S
S
M
S
S
W
S
S
D
S
E
S
M
S
W
S
D
E
M
W
For the same program, now it is running on a pipelined processor with complete forwarding
function. Fill in the following table using F, D, E, M, W, S. The hazard detection unit and
forwarding unit can resolve data hazard.
C1
F
C2
D
F
C3
E
D
F
C4
M
E
D
F
C5
W
M
E
D
C6
C7
C8
C9
W
M
S
W
E
M
W
C10 C11 C12 C13 C14 C15 C16
Identify the forwarding path used by the above program in the figure shown on next page
If there is a stall, caused by data hazard,
(a). Explain why the forwarding function cannot resolve this data hazard
For loads immediately followed by stores (memory to memory copies) can avoid a stall by
adding forwarding hardware from MEM/WB pipeline register to the date memory input.
We need a forwarding unit and a MUX to the memory access stage.
(b) Propose a new addition to the datapath to resolve the data hazard, if there is a solution.
2. For the MIPS datapath shown below, several lines are marked with “X”. For each one:
• Describe in words the negative consequence of cutting this line relative to the working,
unmodified processor.
• Provide an example of code that will fail
• Provide an example of code that will still work
X, numbered 1: CAN NOT write to register file. This means that R-type and any instruction with write
back to register file will fail.
add $11, $10, $9 - will fail
sw $10, 0($12) - still not fail
X, numbered 2: Forwarding of the first operand fails
add $10, $11, $12
add $8, $10, $4 ---- fail
add $10, $11, $12
add $8, $9, $10 - works, forwarding the second operand correctly
X, numbered 3. Jumping to a branch target does not work
addi $10, $zero, 2
addi $11, $zero, 2
beq $10, $11, exit ----- will not work
addi $10, $zero, 12
addi $11, $zero, 20
beq $10, $11, exit ---- still work
3. A machine has a 44-bit address bus, with each addressable item being a byte. The cache
memory is a four-way set associative organization. Each block has 64 bytes and 128 sets in the
cache.
(a) Show how the 44-bit physical address is treated in performing a cache reference (i.e., tag,
index, offset)
Each block has 64 bytes -- block offset 6 bits
128 sets -- set index 7 bits
Tag = 44 – 6 -7 = 31 bits
(b) How many bits are required to hold the cache data? How Many bits are required to hold the
cache tag?
Cache data: 128 × 4 × 64 = 32768 bytes = 262144 bits
Cache tag = 128 × 4 × 31 = 15872 bits
(c) What is the fewest number of bits per set required to implement a true LRU replacement
policy?
Each set has 4 ways. In other words 4 blocks per set. Using LRU we need to keep track of which
way (i.e., which block) is the least recently used.
We can use 2 bits per way to represent
00
most recently used
01
second most recently used
10
second least recently used
11
least recently used
Each way has 2 bits, 4 way/set, each set needs 8 bits for LRU.
4.
TLB
Hit
Page Cache Possible or
table
Impossible
Hit
Miss
possible
short explanation
Miss Hit
Hit
possible
Miss Hit
Miss
possible
Miss Miss
Miss
possible
Hit
Miss
Miss
impossible
TLB is a subset of page table
Hit
Miss
Hit
impossible
TLB is a subset of page table
Miss Miss
Hit
impossible
Cache is a subset of main memory