A Backside Via Process For Thermal Resistance Improvement Demonstrated Using GaAs HBTs
J.S. Kofol, B.J.F. Lin, M. Mieminski, A. Kim, A. Armstrong, R. VSn Tug
Hewlett Packard Laboratories, Palo Alto, California
and
Microwave Technology Division, Santa Rosa, California
of
Hewlett-Packard Company, Palo Alto, California, 94304
ABSTRACT
We report a method for reducing the operating temperature of
GaAslAlGaAs HBTs to acceptable levels, while maintaining the
compact device layout needed for high frequency operation. A
structure, called Backside Thermal Via, is formed by selectively
etching nearly all of the GaAs from the back side of the wafer in
photolithographically patterned regions, directly under the heat
sources, until a five micron membrane of GaAs remains. Gold is
then plated onto the membrane. For one particular transistor design,
a greater than 50% reduction of the thermal resistance has been
measured. Models suggest that even greater improvement in
thermal properties will be obtained as device active area increases.
INTRODUCTION
GaAs has a thermal conductivity disadvantage compared with
silicon--the thermal conductivity ratio, K
[ ~kl/i&~
,!,]
being
approximately 2.3 at typical operating temperatures (1).
Heterojunction Bipolar Transistors (HBTs) are particularly vulnerable
to excess temperature rise on low-conductivity semiconductors since
speed performance expectations often require that they be operated
at high dissipation power densities. Furthermore, HET power
dissipation per unit emitter length is typically greater than FET
dissipation per unit gate width, making the HBT comparatively less
effective in spreading heat close to the device.
Design strategies for controlling temperature rise usually
include spreading out the heat sources and/or reducing the
dissipation power density by careful selection of bias point. Both of
these techniques usually extract a speed-performance penalty and
threaten the advantages of GaAs over Silicon.
Structures for reducing thermal resistance of active devices on
the chip have been devised by process engineers (2-4). In this work
a processing technique for aggressively improving the thermal
resistance is demonstrated. The structure, called Backside Thermal
Via (BTV), is shown schematically in Figure 1.
STRUCTUREANDPROCESS
In the BTV process, the wafer is selectively thinned until a
membrane of GaAs only 5pm thick remains. The backside via holes
thus created are then back-filled with plated gold. BTVs as small as
150pm and as large as 600pm on a side have been fabricated. The
minimum achievable dimension is limited by the ability to fill the via
with plated gold. The larger vias at 600pm do not seem to have
reached the upper limit of the technique.
An additional feature is a through-chip ground via processed
from the top side of the wafer through the 5pm thick GaAs
membrane as shown in Figure 2. This ground via, called "Top
Ground," consumes an area only 30pm square on the top of the
chip. This represents a IO-fold reduction in consumed area
compared with more conventional through-chip grounding structures
(5). As an added advantage, the reduced size of the structure
shortens the path length to ground, reducing the inductance.
The top side of the wafer is processed first, including MBE
growth and fabrication of HBTs, resistors, capacitors,
interconnection. scribe and scratch overcoat protection. Only two
modifications are made to the normal topside fabrication in order to
accommodate the B N process. First, epitaxial layers are added
underneath the usual HBT layers as shown in Table 1. The
functions of these additional layers are to: 1) provide selective etch
stopping during backside etching, 2) separate topside circuit
elements from BTV metal for AC isolation and 3) DC isolate buried
subcollector layers from BTV ground. Second, to provide the
optional through-chip ground, a via hole 15pm square is nonselectively wet-etched approximately 5pm deep from the topside of
the chip all the way through the epitaxy. The Top Ground via hole is
then covered over with metalization.
After top side processing is completed, the wafer is backlapped and polished to a thickness of 100pm. Backside thermal via
holes are then selectively Reactive-Ion Etched (RIE) through the
GaAs wafer, stopping on the 500nm AlGaAs MBE layer buried 5pm
beneath the top surface of the wafer. Conditions of the He:CCI,F,
R E were chosen with consideration for etch rate, etch profile, and
wafer heating. The 100pm etch requires about two hours. After
etching, a flash coating of metal is deposited as a plating base and a
150pm thick gold layer is plated onto the wafer, completely filling the
etched thermal vias. The gold is then backlapped flat.
THERMAL PERFORMANCE, MEASUREMENTS AND MODELS
Thermal resistance was measured on transistors having six
different layout geometries. A plan view of the location and size of
the emitters of each of the six layouts, labeled " A through "F", is
shown in Figure 3. Wafers processed with and without BTV were
measured and compared to directly evaluate the effectiveness of the
BTV. Wafers processed without the BTV were lapped to a thickness
of 1OOpm and plated with gold.
A measurement of the thermal resistance of each transistor
used Vbe (at constant IC) as a thermometer to indicate the
temperature of the emitter-base junction. The thermometer was
calibrated by measuring Vbe Vs chuck temperature at constant bias
dissipation power. Then, thermal resistance was determined from
the measured relationship between junction temperature (indicated
by Vbe at constant IC) and bias dissipation power (varied by setting
Vcb). The accuracy of the technique depends upon the assumption
that changes in Vbe resulting from varying Vcb are due solely to
changes in the junction temperature. For many bipolar transistors,
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GaAs IC Symposium 267
this assumption may be poor due to the Early effect. However,
estimates suggest that the Early effect has not affected the outcome
of our measurements because of the high ( N ~ = - 2 x l O ~ ~ c and
m-~)
abrupt base doping of our HBTs.
Measurements were made at low dissipation power.
Temperature rise due to power dissipation was typically less than
15OC, thus minimizing potential complications due to the temperature
dependence of the thermal resistivity of GaAs. All measurements
were made at chuck temperatures ranging from I O o to 35OC.
Results of the comparison of thermal resistance of transistors
with and without BTV over the range of transistor designs " A
through "F" (Figure 3) are shown in Figure 4. The ratio of thermal
resistance with BTV to thermal resistance without BTV is plotted for
each design as a function of total emitter area. The same ratio for
each design, calculated using a finite-element Poisson solver, is also
shown. In Figure 5, the measured thermal resistance is plotted
against the calculated thermal resistance for each transistor design
on BTV. The agreement between theory and experiment in both
figures is excellent.
Figure 6 plots the expected junction temperature for each of the
six transistor designs with and without BTV at a dissipation power
density of 2.5mW/pm2. This corresponds to a typical desired bias
dissipation of JC=5x1O4A/cm2 and Vce=5V.
The heat sink
temperature is assumed to be 75OC, a typical value for many
applications. A maximum specified junction temperature of 15OoC is
also typical, but may vary greatly depending on reliability
expectations. Both temperatures are indicated on the plot. Notice
that the BTV becomes increasingly critical for achieving thermal
design objectives as the device area increases above 50pm2.
Notice, too, by comparing the junction temperatures of two devices
with equal junction areas, "C" and " D , that area is not the only
important factor. Layout geometry is also very important.
Another benefit of the BTV is suggested by Figure 7. Here we
plot the maximum junction temperature calculated for two different
transistors, with and without BTV, each having a total junction area
of 400pm2. Each transistor is formed by paralleling 81 smaller
transistors of equal area laid out on a regular 9-by-9 grid. The total
power dissipation for the array is 1.OWatt at a power density of
2.5mW per pm2 of junction area. The figure shows the maximum
junction temperature as a function of the width ot the array. This can
be visualized as plotting the maximum junction temperature as we
stretch the 9-by-9 array to greater and greater dimensions, all the
while maintaining each element of the array at a constant size and
constant power. From Figure 7, it can be inferred that using the BTV
results in a factor of 13 reduction of consumed chip area in this
scenario where we have assumed a 75OC heat sink and a 150°C
maximum allowable junction temperature. Furthermore, since
interconnection parasitics depend on interconnection distance,
Figure 7 is a first step in understanding the parasitic interconnection
benefits of the BTV.
It is no accident that a regular array of minimum-geometry
(2.2~2.2~171)
devices was chosen as the example in Figure 7. We
believe that for power devices of large active area, where optimum
thermal design is critical, this configuration will be very attractive.
The temperature rise at any point within the junction of a large
transistor can be thought of as having two components: a selfheating component caused by heat being dissipated at the point of
measurement, and a mutual-heating component caused by heat
being dissipated by neighboring junctions. Transistor design using
arrays of minimum-geometry devices minimizes the mutual-heating
component. The advantage of the array approach to transistor
design increases substantially as the transistots total junction area
increases.
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268 GaAs IC Symposium
Figure 8 illustrates the underlying thermal advantage of the
BTV for a large transistor constructed from an array of parallelinterconnected minimum-geometry devices. Here we plot the
calculated temperature rise along the surface of the chip caused by
a sinale 2.2x2.2pm transistor dissipating ImW. Two curves,
representing results for transistors with and without BTV, are shown.
For distances less than l.lpm from the center of the transistor, the
curves of Figure 8 represent the junction temperature within the
minimum-geometry device. Note from the figure that using the BTV
reduces the temperature rise within the junction of a single minimumgeometry transistor by a modest 13%. However, at 5pm from
center, Figure 8 shows that the BTV has reduced the mutual heating
by a factor of 2. At 20pm from center, the BTV has reduced the
mutual heating more than IO-fold. Herein lies the fundamental
advantage of the BTV: The €ITV dramatically reduces the thermal
coupling between heat sources separated from each other by
distances greater than the thickness of the 5-micron GaAs
membrane.
Figure 9 illustrates the effectiveness of the BTV in reducing the
temperature rise in arrays of even modest numbers of elements.
Here we plot the calculated surface temperature of device "0"(a 3x3
(See Figure 3.) Notice that the
element array) along the line QQ.
surface temperature between the elements of the array recovers to
within 10°C of the 75OC heat sink temperature for the device with
BTV, even though the transistor elements are separated by only
13.3 pn. On the other hand, without BTV, the surface temperature
of the chip between array elements remains at 4OoC above the heat
sink, four times the rise calculated with BTV. The junction
temperature advantage of the BTV in this example is 3OoC, nearly all
of which comes from its advantage in reducing mutual heating.
DEVICE AND CIRCUIT RESULTS
Both discrete HBTs and HBT ICs have been fabricated on
BTVs. To date, we have observed no significant changes of the DC
performance of HBTs caused by the BTV other than changes
attributable to reduced device operating temperature. In addition,
the ft and fmax (measured by extrapolating the current gain and the
maximum available gain) of the minimum-geometry device on BTV
are typically 50 and 69GHz, respectively, when operated at Ic=3mA
and Vce=2V. These values are similar to those observed on devices
fabricated without BTV.
The BTV increases the capacitance between the subcollector
and substrate ground, Cc-sub. The size of the capacitance is
strongly dependent upon layout geometry. As an example, the value
of cc-sub of device "F" of Figure 3 with BTV is estimated as 100 ff.
This is only 15% of the value of the collector-base capacitance.
Adding the BTV increases the capacitance between
interconnection metalization and substrate ground.
As a
consequence, transmission lines may have increased loss and/or
reduced current-carrying capacity, but the seriousness of these
disadvantages are circuit specific and remain to be seen.
Small-scale ICs have been fabricated using BTV. One
example, a two-stage broadband amplifier gain block, has been
tested with and without BTV. The amplifier with BTV, dissipating
300mW, has measured gain and bandwidth of 10.0dB and 20.2GH2,
respectively. The gain-bandwidth product is 12% higher than for the
same amplifier without BTV. We attribute nearly half of the
improvement in gain-bandwidth product to a higher ft resulting
directly from lower junction temperature.
CONCLUSIONS
The Backside Thermal Via has been shown to significantly
reduce the thermal resistance of GaAs HBTs. Discrete transistors
and small-scale integrated circuits fabricated on top of the structure
have shown excellent performance. It is believed that designers will
find the B N to be a valuable aid in meeting their design objectives
for power, speed and reliability as they trade off layout area, junction
temperature and bias point.
TOP
Grou
Via
ce
I /
Thermal Via
(Plated Gold)
:;Sstrae
I
_I
ACKNOWLEDGMENTS
\
We wish to acknowledge Lovell Camnitz for useful discussions.
Backside
Scribe Lane
Figure 1. Backside thermal via cross-section with through-chip
grounding via.
REFERENCES
(1) S.M. Sze, Phvsics of Semiconductor Devices, p. 55, John Wiley
8 Sons, 1969.
(2) K. Sumitani, M. Komaru, et al., "A High Aspect Ratio Via Hole
Dry Etching Technology for High Power GaAs MESFET," 1989
Proc. GaAs IC Symposium, pp. 207-210.
(3) K. Okaniwa, T. Ishikawa, et al., "A Novel FET Structure of
Buried Plated Heat Sink for Superior High Performance GaAs
MMICs", 1990 Proc. GaAs IC Symposium, pp. 233-236.
(4) M. C. Driver, et al., "Monolithic Microwave Amplifiers Formed by
Ion Implantation into LEC Gallium Arsenide Substrates." IEEE
Trans. on Electron Devices, Vol. ED-28, No. 2, Feb. 1981, pp.
191-196.
Collector Metal
Figure 2. Detail of top ground cross-section.
(5) MMlC Design Rules, Hewlett-Packard Company, unpublished.
Table 1. MBE Modifications for BTV.
Layer
Description
Added
For
BTV?
Thickness
[nm]
Doping
Growth
Temperature
HBT
1000
Sub-collector
800
ND+
normal
normal
GaAs
Yes
500
0
low
GaAS
yes
2000
$
normal
A10.3Ga0.7As
Yes
500
$
normal
GaAs
Yes
300
0
normal
Substrate
500 pm
3 emitter fingers
2.2x6.6 um
1
1
1
1
1
5 emitter fingers
2.2x9.5 urn
.... ....
32 emitter fingers
2.2x2.2 um
Figure 3. Plan view of emitter layouts for transistors studied.
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GaAs IC Symposium 269
Rth: Measured vs Calculated
Six Different HBT Layouts on B l V
th-with BTVhh-without B N
For Six Different HBT Layout Geometries
F
Calculated
0.6
3
3
e
3
0.4
1.o
P
1
I--0.0
50
100
150
Total Emitter Area [U$
r"
200
1
Calculated Rth
jure 4. Ratio of thermal resistance with BTV to thermal resistan
khout BTV. (Transistor types "A'through "F" defined in Figure 3.)
pC/rnW
Iigure 5. Measured Vs calculated thermal resistance for device
types "A'through "F" on BTV.
EstimatedJunction Temperature
Simulated 1-Watt Transistor Array
heatsink=
7 9 C ; Dissipation = 2.5
9x9 array; Ae=400 um2; 2.5 m W / u d
220,
350
5
300
0
Q
250
E
F
200
C
150
I
"
h
602
!-Theas
tn
ik
5 0 6 5 1 6 0 T h e a t s i n k
Total Array Width [um]
Total Emitter Area [urn2]
gure 6. Estimated junction temperatures of transistors "A'throu
"F" under realistic dissipation assumptions, based on Rth
measurements.
-igure 7. Maximum junction temperature calculated for a power
transistor array of minimum-geometry devices dissipating 1 Watt, as
a function of lateral spreading of the array.
Surface Temperature Rise From a Single
Transistor "D"Surface Temperature
F 2.2x2.2 um HBT Dissipating 1 mW
-5
B
103
I
I
Ae=44 urn2; Dissipation=2.5 mW/um2
I
.o
Distance From HBT Center [um]
Figure 8. Surface temperature rise caused by a single minimumgeometry HBT. with and without BTV.
270 - GaAs IC Symposium
Distance from Array Center [um]
Figure 9. Temperature along the surface of a "D" type transistor
array with and without BTV.