Design of a Boost DC-DC Converter
for Energy Harvesting Applications
in 40nm CMOS Process
Jialue Wang
November 2014
Design of a Boost DC-DC Converter
.
for Energy Harvesting Applications
in 40nm CMOS Process
Master of Science Thesis
Jialue Wang
A thesis submitted to the Faculty of
Electrical Engineering, Mathematics and Computer Science
in partial fulfilment of the requirements for the degree of
Master of Science in Electrical Engineering
Delft University of Technology
Dated: November 16, 2014
Supervisor:
Thesis committee:
dr.ir. Wouter A. Serdijn
dr. Reza Lotfi
dr.ir. Henk Polinder
Ir. Cui Zhou
MSc. Gustavo Campos Martins
This thesis is confidential and cannot be made public until December 1, 2015.
Abstract
i
Abstract
DC-DC converters are critical building blocks in energy harvesting systems which are
applied to provide the energy for the implantable biomedical devices. They are required
to meet very strict specifications and consume as less power as possible. Therefore, their
power conversion efficiency and stability of the functionality in the varying environment
become the major considerations in this thesis project, the target of which is to design a
DC-DC converter for energy harvesting applications.
The conventional PWM control is not usually suitable for the DC-DC converters
applied in energy harvesting applications because of its bad stability and low power
conversion efficiency over wide input voltage and load current ranges. It is demonstrated
that the adaptive on-time/off-time (AOOT) control proposed in this thesis is an excellent
alternative to deal with the issue and the zero current switching (ZCS) adjustment
technique can be applied to improve further the performance of the DC-DC converter by
the fine tuning of the off-time.
In this thesis, a systematic design flow of a boost DC-DC converter has been
presented from the design of the power plant, to the selection of the most suitable control
technique, then to the transistor-level implementation and finally to the layout design.
Moreover, the circuitry of a boost DC-DC converter and the layout of its most parts have
been implemented in TSMC 40nm CMOS process. The post-layout simulation results
prove that the proposed boost DC-DC converter can generate a stable 1𝑉 output voltage
with very small ripples (< ~10𝑚𝑉) and achieve more than 90% (maximum about 95%)
power conversion efficiency over a wide input voltage range (0.35𝑉~0.65𝑉) and a wide
load current range (1𝑚𝐴~10𝑚𝐴).
Keywords: Boost DC-DC converter, Energy harvesting, Power conversion efficiency,
Adaptive on-time/off-time control, Zero current switching adjustment.
ii
Acknowledgement
iii
Acknowledgement
I am deeply grateful to the people who have, directly or indirectly, helped me during my
Master thesis project. Because of your help and supports, I can smoothly finish this
project.
First of all, I would like to express my sincere appreciation to my supervisor, Wouter
A. Serdijn who is really a very nice person. Without his help and supports, I cannot image
how I can pass through the most difficult time during this project. Although in most time,
he was extremely busy, he was still willing to spend a lot of time on guiding me. The
things I have learned from him are not only how to design a good circuit but also how to
be a good person.
Then, I would like to give my great thanks to Cui Zhou, who was my daily
supervisor at the Holst Center/imec. The most important thing she taught me is not the
practical skills in the circuit design but the ability of solving new problems independently.
This can be properly described by a Chinese proverb “shou ren yi yu, bu ru shou ren yi
yu”, that means, it would be better to teach a person how to catch fish than just to give
him some fish.
Moreover, I would like to thank the people in my team at the Holst Centre/imec. A
specific thank should be given to Kathleen Philips who provided me this opportunity to
being part of her talented team. Genuine thanks will be given to my dear colleagues, Bo
Liu, Xiongchuan (Coby) Huang, Ao Ba and Ming Ding for their daily help. My thanks
also go to the guys in the biomedical group at TU Delft, especially to the Ph.D. student
Yongjia Li. If I could list three supervisors, he would be the third one with no doubt.
Finally, I would like to express my greatest thanks and love to my parents. Your
everlasting love, care, encouragement and support throughout my life have been a source
of strength for me and have enabled me to get to this point.
iv
Contents
v
Contents
Abstract ................................................................................................................................ i
Acknowledgement ............................................................................................................. iii
Contents .............................................................................................................................. v
List of Figures .................................................................................................................... vii
List of Tables....................................................................................................................... xi
Chapter 1 ........................................................................................................................... 1
1.1 Background ............................................................................................................... 1
1.2 DC-DC Converter ..................................................................................................... 4
1.3 Research Objectives .................................................................................................. 7
1.4 Thesis Outline ........................................................................................................... 8
Chapter 2 ......................................................................................................................... 13
2.1 Basic Working Principle of the Boost DC-DC Converter ...................................... 13
2.2 Power Loss Mechanism .......................................................................................... 19
2.3 Preliminary Design of the Power Plant ................................................................... 22
Chapter 3 ......................................................................................................................... 33
3.1 Introduction to This Chapter ................................................................................... 33
3.2 PWM Control .......................................................................................................... 34
3.3 PFM Control ........................................................................................................... 41
3.4 Control Technique Applied in This Work............................................................... 44
3.5 Time Signal Generation .......................................................................................... 48
3.6 Zero Current Switching Adjustment ....................................................................... 51
Chapter 4 ......................................................................................................................... 59
4.1 Overview of This Chapter ....................................................................................... 59
4.2 Digital Logic Block ................................................................................................. 60
4.3 On-Time and Off-Time Generators ........................................................................ 65
4.4 Zero Current Switching Adjustment Blocks ........................................................... 70
vi
4.5 Comparator.............................................................................................................. 75
4.6 Reference Current Generator .................................................................................. 78
Chapter 5 ......................................................................................................................... 85
5.1 Overview of the Layout Design .............................................................................. 85
5.2 Layout Design of the Power Switches .................................................................... 87
5.3 Layout Design of the Current Mirror Array ............................................................ 93
5.4 Conclusions of the Layout Design .......................................................................... 95
Chapter 6 ......................................................................................................................... 99
6.1 Simulation Environment ......................................................................................... 99
6.2 Operation of the Converter in the Startup Phase ................................................... 100
6.3 Operation of the Converter in the Steady State ..................................................... 102
6.4 Responses of the Converter to Input Voltage and Load Current Variations ......... 106
Chapter 7 ........................................................................................................................ 109
7.1 Summary ............................................................................................................... 109
7.2 Contributions......................................................................................................... 109
7.3 Future Works......................................................................................................... 111
List of Figures
vii
List of Figures
1-1:
Implantable electronic devices in the biomedical application [1] [2] [3]………….1
1-2:
Energy harvesting techniques: (a) solar energy [5]; (b) kinetic energy [5]; (c)
thermoelectric energy [5]; (d) RF energy [6]…………………………………...…..3
1-3:
RF energy harvesting system used to charge the battery………………………..….3
1-4:
General application of a DC-DC converter in portable devices……………….…...4
1-5:
Schematic of a linear voltage converter [13]…………………………………....….5
1-6:
Schematic of a charge-pump DC-DC converter [13]…………………………....…6
1-7:
Schematic of an inductor-based boost DC-DC converter [13]……………….….…7
2-1:
Basic Inductor-based boost DC-DC converter…………………...……….………13
2-2:
Boost DC-DC converter in the on-time phase……………………….….......….…15
2-3:
Boost DC-DC converter in the off-time phase………………….……………..….15
2-4:
Timing diagram of main signals in a CCM boost converter…………………....…15
2-5:
Boost DC-DC converter in the dead-time phase……………………………….…16
2-6:
Timing diagram of the main signals in a DCM boost converter…………….….…16
2-7:
Asynchronous boost DC-DC converter……………………………………….…..18
2-8:
Switching waveforms of the transistor (a) in the best-case scenario; (b) in the
worst-case scenario…………………………………………………………...….21
2-9:
Waveform of the inductor current for the boost converter working in the boundary
of CCM and DCM………………………………………………………………..23
2-10:
Switching waveforms of the transistor (a) in the best-case scenario; (b) in the
worst-case scenario…..........................................................................................26
2-11:
Equivalent schematic model of the inductor “CLF7045T-1R0N”…………...…..28
2-12:
Equivalent schematic model of the capacitor “C0603JB0J223K030BC”……….29
3-1:
Boost DC-DC converter with a typical CCM VMC control……………...………34
3-2:
PWM signal generation by the PWM comparator……………………………..….35
3-3:
Compensation for the loop stability of a VMC boost DC-DC converter…………37
3-4:
Boost DC-DC converter with a typical CCM CMC control…………………...….38
viii
3-5:
Compensation for the loop stability of a CMC boost DC-DC converter…………38
3-6:
Subharmonic oscillation when duty cycle exceeds 50%.........................................39
3-7:
Slope compensation to eliminate the subharmonic oscillation.........................…...39
3-8:
DCM VMC boost DC-DC converter system [9]………………………………….40
3-9:
Buck DC-DC converter with hysteretic control [1]………………………….……42
3-10:
Timing diagram of the buck converter with hysteretic control……………….….42
3-11:
Buck DC-DC converter with COOT control [1]…………………………………43
3-12:
Timing diagram of the buck converter with (a) constant on-time (b) constant
off-time control…………………………………………………………………..43
3-13:
Boost DC-DC converter with an enhanced COOT control……………………...45
3-14:
Timing diagram of the boost converter with an enhanced COOT control……....46
3-15:
Control system is sensitivity to the noise at the node Vfb ……………………….46
3-16:
Boost DC-DC converter system with the filter cap…………………………...…47
3-17:
One approach to implement the time generators. [14]…………………………..49
3-18:
Timing diagram of main signals in the time generator. [14]…………………….49
3-19:
I-C time generator with DAC and sleep mode control [21]……………………..50
3-20:
Timing diagram of main signals in the time generator [21]……………………..50
3-21:
On-time generator and its working principle…………………………………….51
3-22:
Off-time generator and its working principle……………………………………51
3-23:
Boost converter with overly short off-time (a) and overly long off-time (b)……52
3-24:
Mechanism of the ZCS adjustment……………………………………………....53
3-25:
Entire boost DC-DC converter with AOOT control and ZCS adjustment………54
4-1:
Entire boost DC-DC converter system designed in this work………....…………59
4-2:
Operation flow chart of the boost DC-DC converter………………………..…...60
4-3:
Timing diagram of all signals………………………………………………….…61
4-4:
Schematic of the Digital Logic block……………………………………….……62
4-5:
First failure mechanism of the control system…………………………………...62
List of Figures
ix
4-6:
Operating model selection circuit………………………………………….....…63
4-7:
Timing diagram of quasi-CCM and DCM………………………...………….…63
4-8:
Timing diagram of S3 triggering and resetting……………………...…..….…...64
4-9:
S1 and S3 generating circuits………………………………………………..…...64
4-10:
Output of the boost converter short to the ground……………………….…....65
4-11:
Circuit implementation of the on-time and off-time generators……….….......65
4-12:
Different working phases of the on-time generator…………………….……..66
4-13:
Different working phases of the off-time generator………………………..….67
4-14:
Simulation results of the time generators with different channel length….......69
4-15:
Reset of nodes Vcon and Vcoff in the dead-time phase……………………....….69
4-16:
A D flip-flop 1-bit ADC…………………………………………………......…70
4-17:
Voltage detection for an overlong or insufficient off-time……………..……..71
4-18:
Current-mode DTC for the off-time calibration………………………….....…72
4-19:
System-level diagram of the ZCS adjustment block………………………......73
4-20:
Two current branches controlled by 2-bit binary digital code in the DAC….....74
4-21:
Seven current branches controlled by 7-bit unary digital code in the DAC.......75
4-22:
Comparator delay effect under (a) low load and (b) low load…………..…......76
4-23:
Schematic of the comparator…………………………………………………..77
4-24:
PTAT current source………………………………………………………........78
4-25:
Combination of a PTAT current source and a CTAT current source [4]….........80
4-26:
Final schematic of the reference current generator………………………….....81
5-1:
On-chip and off-chip parts of the boost DC-DC converter………………...….…85
5-2:
Layout of the entire on-chip part of the boost DC-DC converter………….....…..86
5-3:
Transistor with a large W/L in the simplest structure.……………………..…..…87
5-4:
Transistor with a smaller W/L in the finger structure…………………….....…....87
5-5:
Segmentation of the large power switch transistor………………………...…......88
5-6:
Unit cell of the power switch transistor…………………………….………….....88
x
5-7:
Currents flowing through the inductor and power switch transistors……..…….89
5-8:
Source and drain connection of a unit transistor………………………………...90
5-9:
5-layer metal wire, (a) cross-section view, (a) top view………………………....91
5-10:
Two topologies of the NMOS power switch transistor’s layout……………....92
5-11:
Final layout of the NMOS (a) and PMOS (b) power switches with buffers.....93
5-12:
General layout techniques for current mirrors………………………………...94
5-13:
Layout topology for the current mirrors in this work………………………....94
5-14:
General layout techniques for current mirrors………………………………...95
6-1:
The schematic of the test bench……………………………………………..…100
6-2:
Startup phase of the boost DC-DC converter…………………………………..101
6-3:
Waveforms of the boost DC-DC converter (Iload = 10mA)……………...........102
6-4:
Zoom-in waveforms of the boost DC-DC converter (Iload = 10mA)….…...….103
6-5:
Verification of the ZCS adjustment technique (Iload = 10mA)…………..…....104
6-6:
Waveforms of the boost DC-DC converter (Iload = 1mA)………………..........104
6-7:
Zoom-in waveforms of the boost DC-DC converter (Iload = 1mA)……..….....105
6-8:
Verification of the ZCS adjustment technique (Iload = 1mA)……………..…...105
6-9:
Responses of the boost converter to an input voltage variation………….…......106
6-10:
Responses of the boost converter to a load current variation………….….…107
List of Tables
xi
List of Tables
1-1 Specifications of this research…………………………………………………….…8
2-1 Parameters of the MOSFET power switches……………………………….…..…..25
2-2 Candidates of the inductors for the comparison…………………………………....27
2-3 Calculation results of the power losses with different inductors………………...…27
4-1 Parameters of the transistors in the on-time and off-time generators…………...….66
4-2 Power consumption of the on-time generator for different discharging currents..…67
4-3 Comparison between the current-mode DTC and the capacitor-mode DTC……….72
4-4 Parameters of the transistors in the DAC…………………………………………...75
4-5 Parameters of the transistors in this block…………………………………………..82
5-1 Comparison table of several low-power boost DC-DC converters…………………96
xii
Chapter 1
Introduction
1.1 Background
In the past few decades, due to the explosive growth of the microelectronics industry and
semiconductor technology, the electronic products, which are becoming not only smaller
and smaller but also more and more complex, have played a very important role in
shaping human society. The emergence of many electronic products has changed the
lifestyle of the human beings, such as the laptop or the mobile phone. The booming
development of electronic devices has promoted a lot to the advance of the biomedical
technology, which causes the situation that various kinds of implantable electronic
devices are currently being used to monitor, diagnose and treat the diseases for personal
healthcare, such as the neurostimulator (Figure 1-1.a) [1], the pacemakers (Figure 1-1.b)
[2] and the cochlear implant (Figure 1-1.c) [3].
(a)
(b)
(c)
Figure 1-1: Implantable electronic devices in the biomedical application [1] [2] [3].
It is common sense that any electronic device cannot operate without power. Hence,
the implantable biomedical devices need to be powered by some power supplies. In the
consideration of the volume and convenience, these devices generally use tiny batteries
assembled on the devices as the power source. But accordingly, a great challenge occurs,
2
Introduction
that is how the batteries can be replaced or recharged when the energy is depleted.
Obviously, it is quite difficult or even infeasible to replace the batteries of the biomedical
devices which have been implanted into the human body. Therefore, many efforts have
been made on exploring an efficient method to realize self-powered or self-rechargeable
power supplies for the implantable devices.
Energy harvesting technology provides a suitable solution to the issues mentioned
above. Although the earliest use of energy harvesting dates back to the windmill and the
waterwheel, the energy harvesting discussed afterwards refers to techniques which are
based on semiconductor technology and used for low-energy electronics. Energy
harvesting systems can capture ambient energy such as solar, thermal, kinetic or radiofrequency (RF) energy and transform the captured energy into the electrical domain so as
to charge the battery or directly power the implantable device. A brief introduction to four
most common existing harvesting techniques has been proposed in [4]. The four
harvesting techniques are solar energy harvesting, thermoelectric energy harvesting,
kinetic energy harvesting and RF energy harvesting.
All the energy harvesting techniques can be applied to supply power to implantable
biomedical devices. But the specific application will be restricted by some practical
limitations. For example, for solar energy harvesting (Figure 1-2.a) [5], the limited area of
the solar receiver and the low intensity of the light which can be received by the harvester
will make this technique not available for devices deeply implanted into the body or
under the skin. For kinetic energy harvesting (Figure 1-2.b) [5], since the motion or
activity made by some parts of the human body is weak, this technique is unsuitable for
devices which are implanted in a part of the human body without much motion. Moreover,
for thermoelectric energy harvesting (Figure 1-2.c) [5], to ensure a sufficient temperature
difference between two sides of the harvest, this technique is suitable for devices inlaid
on the skin, because one side of which can sense the temperature of human body and the
other side of which can sense the temperature of ambient air. Finally, for RF energy
harvesting (Figure 1-2.d) [6], since the power density of the RF signal that can be
received from a nearby base station is quite low (−12𝑑𝐵𝑚/𝑚2 ) [7], the feasible solution
is to use a dedicated RF source to supply enough power for the RF energy harvesting
system in the implantable devices [8]. The principle of this method is similar to that of
radio-frequency identification technology (RFID).
(a)
(b)
1.1 Background
3
(c)
(d)
Figure 1-2: Energy harvesting techniques: (a) solar energy [5];
(b) kinetic energy [5]; (c) thermoelectric energy [5]; (d) RF energy [6].
No matter of which kind of energy harvesting system, there is a common
phenomenon, that is, the output voltage of the energy harvester is generally too low to
provide the supply voltage for the battery. For current battery technology, it requires a
supply voltage at least around 1𝑉 to charge the battery. But as mentioned in [9] [10], for
body-wearable applications, the output voltage can only achieve about 100𝑚𝑉 for the
thermoelectric generators (TEG) and the output voltage of a single solar cell is just about
500𝑚𝑉 outdoors but becomes lower than 200𝑚𝑉 in dark office environment. For the
RF energy harvesting system with a single stage rectifier (voltage doubler), the results of
[11] show that, if the input power is about 0𝑑𝐵𝑚, the output voltage of the RF energy
harvester is just over 100𝑚𝑉. Although the output voltage of the RF energy harvester can
be raised by increasing the number of stages of the rectifier (voltage doubling circuit),
according to the conclusion made in [12], the RF-to-DC power conversion efficiency of a
multistage configuration will be worse than that of a single stage configuration. Therefore,
because of the bad power conversion efficiency, the number of stages of AC-DC
converters should be limited. Instead, a DC-DC converter whose efficiency can ideally
achieve 100% is applied to boost the small output voltage of the energy harvester to the
required level for charging the battery. Figure 1-3 shows a RF energy harvesting system
which can be used to charge the battery of implantable devices.
RF signal
RF
Receiver
Small
AC signal
Matching
Network
Small
DC signal
Rectifier
Target
DC signal
Boost DC-DC
Converter
Battery
Figure 1-3: RF energy harvesting system used to charge the battery.
4
Introduction
1.2 DC-DC Converter
The Direct-Current to Direct-Current (DC-DC) converter is an electronic circuit which
can convert a DC voltage into another DC voltage. It has been widely used in current
portable electronic devices for regulation of supply voltages. Since the current electronic
devices are generally constituted by several sub-circuits, each of which requires its own
supply voltage perhaps different from the voltage supplied by the battery or the external
supplier, a DC-DC converter can be used to realize the step-up or step-down conversion
of the supply voltage. Figure 1-4 shows the function of a DC-DC converter in a batteryoperated portable device, in which the battery voltage is converted into different voltages
for supplying different blocks in the device.
5V
3.6V
DC-DC Converter
Audio Amplifier
1.8V
ADC
1V
Digital Circut
Figure 1-4: General application of a DC-DC converter in portable devices.
In recent years, due to its characteristics, the DC-DC converter has also been widely
used in energy harvesting system to convert the voltage generated by the harvester to the
stable voltage required by the back-end circuit or battery. For the DC-DC converter in an
energy harvesting application, the power conversion efficiency which is equal to the
output power over the input power, is generally the most important consideration.
There are three fundamental methods that can be applied to achieve the DC-DC
voltage conversion. The first one is using linear voltage conversion on resistive dividers.
This kind of DC-DC converter is also named low-dropout regulator (LDO). The basic
operating principle of the linear voltage converter can be explained with the aid of an
example shown in Figure 1-5. The target voltage is obtained from the resistive divider
composed of a variable resistor (𝑅series ) and a constant resistor (𝑅load ). The control
circuit adjusts the value of the variable resistor so as to regulate the output voltage to the
desired value. For this kind of DC-DC converter, as the output voltage is generated by a
division of the input voltage, it can only achieve step-down voltage conversion. Another
drawback of this method is the poor power conversion efficiency. Since the excess power
is dissipated on the resistor (𝑅series), this method is inefficient compared to the other two
ones which will be introduced afterwards. Moreover, according to Equation 1.1 which is
1.2 DC-DC Converter
5
used to calculate the power conversion efficiency of the linear voltage converter shown in
Figure 1-5 [13], the efficiency will get even worse in the condition where the voltage
conversion ratio (𝑉out /𝑉in ) is small and the control current (𝐼c ) is high. However, because
the control circuit is relatively simple and neither any large inductors nor capacitors are
required, the implementation of this kind of DC-DC converter is comparatively simple
and area-saving. Therefore, the linear voltage convertor is well suitable for applications
with low requirements on the power conversion efficiency but high demand on design
simplification and area limitation.
𝜂=
𝑃out
𝑃in
=
𝑉out ∙𝐼o
𝑉in ∙(𝐼o +𝐼c )
(1.1)
Io
Rseries
Vout
Ic
Control
Loop
Vin
Vc
Rload
Figure 1-5: Schematic of a linear voltage converter [13].
The second approach to implement a DC-DC converter is using a switch-mode
charge-pump circuit to realize the step-up or step-down voltage conversion. In this kind
of DC-DC converter, there are some energy-storing capacitors and power switches. By
periodically turning on and off the power switches, the topology of the circuit is changed,
thus achieving the voltage conversion. Figure 1-6 shows the circuit and the operating
principle of a step-up charge-pump DC-DC converter. In the first phase (𝛷1 ), since the
flying capacitor 𝐶1 is connected to the input voltage source, the energy coming from the
input is stored in 𝐶1 . In the second phase (𝛷2 ), since the flying capacitor 𝐶1 is connected
to the load capacitor 𝐶2 , the energy stored in the flying capacitor 𝐶1 is delivered to the
load capacitor 𝐶2 . The output voltage of this DC-DC converter can be expressed by
Equation 1.2 [13].
𝑉out =
2𝑅L 𝑓sw 𝐶1
𝑉
1+𝑅L 𝑓sw 𝐶1 in
(1.2)
From the expression, it can be concluded that, if the item (2𝑅L 𝑓sw 𝐶1) is larger than 1, this
circuit can achieve a step-up voltage conversion. In the ideal case, as no quiescent power
dissipation exists in this kind of DC-DC converter (ignore the power consumption of the
control circuit), the power conversion efficiency of this converter can achieve
approximately 100% in the special case (the output voltage is double of the input voltage).
6
Introduction
But in reality, since the static and dynamic power losses of the power switches are in a
non-negligible level, and the complex control circuit which is required to control many
power switches will consume much power, the efficiency of this kind of converter cannot
be as perfect as expected. Although the power conversion efficiency of this kind of
DC-DC converter is generally better than that of the first method, in most case, it is worse
than that of the third method which will be discussed in the following.
Vout
Φ1
Vin
Φ2
C1
Cload
Rload
Φ2
Φ1
(a)
C1
Vin
C1
Cload
Rload
Vin
Cload
(b)
Rload
(c)
Figure 1-6: Schematic of a charge-pump DC-DC converter [13].
The third method to achieve the DC-DC voltage conversion is by means of a
combination of an inductor and a capacitor. This kind of DC-DC converter also belongs
to switch-mode DC-DC converters (inductor-based) whose operating principle is similar
to the charge-pump DC-DC converter. Through turning on and off the power switches in
the converter, the energy coming from the input voltage source is periodically stored in
the inductor and delivered to the load capacitor, thus achieving step-up or step-down
voltage conversion. Figure 1-7 shows the circuit and working principle of an inductorbased step-up (boost) DC-DC converter. In the first phase, when the power switch 𝑆1 is
closed and the power switch 𝑆2 is open, the current is charged in the inductor. In the next
phase, the power switch 𝑆1 is open and the power switch 𝑆2 is closed and the energy
stored in the inductor is delivered to the load capacitor. A detailed explanation of its
operating principle will be given in Section 2.1. As the inductor is a reactive component
as the capacitor, the charging and discharging of an ideal inductor also involves no energy
loss. Therefore, in the ideal case, the power conversion efficiency of the inductor-based
DC-DC converter can achieve 100% as well. However, since the number of the power
switches in an inductor-based DC-DC converter is generally half of that in a charge-pump
DC-DC converter, the power losses of the third method, which are mainly caused by the
1.2 DC-DC Converter
7
power switches and the control circuit, are less than those of the second method. Hence,
the power conversion efficiency of the inductor-based DC-DC converter is normally the
best among all the implementation methods. But as a trade-off, due to the use of a large
inductor which in most cases cannot be integrated on an IC, this method is more area
consuming than the other ones.
Vmid
L
Vin
Vout
S2
Cload
S1
Rload
(a)
L
Vmid
Vout
Cload
Vin
L
Vmid
Cload
Rload
Vin
(b)
Vout
Rload
(c)
Figure 1-7: Schematic of an inductor-based boost DC-DC converter [13].
After the above brief introduction of the properties of three fundamental methods to
implement the DC-DC converter, it can be seen that each method has its own advantages
and disadvantages. In order to choose the best one for a specific design of a DC-DC
converter, the designer should be well aware of which specification (power conversion
efficiency, area consumption, design simplification, etc.) is most important for the target
application and make the decision based on this. In this thesis, as the power conversion
efficiency is the primary specification, the inductor-based method is chosen for the boost
DC-DC converter designed in this work. If without specific notification, all the DC-DC
converters mentioned afterwards refer to the inductor-based DC-DC converter.
1.3 Research Objectives
This research was carried out in the Analog IC Design team of the Ultra-Low Power
Wireless System group at the Holst Centre/ imec in the Netherlands. The final target of
this work is to design a high power conversion efficient boost DC-DC converter which
can be used to convert the low voltage generated by the front-end energy harvester to a
high voltage for charging the back-end battery. Since the input voltage of the boost
DC-DC converter is derived from an energy harvesting system, it will vary in a range
8
Introduction
along with the variation of the input power received by the energy harvester. In addition,
the load battery requires a 1𝑉 supply voltage for charging and it can be charged in two
modes (fast/slow). In the fast charging mode, the battery can be considered equivalent to
a constant 10𝑚𝐴 load current source. In the slow charging mode, the battery can be
equivalent to a constant 1𝑚𝐴 load current source. According to the requirements
provided by our company, the design specifications can be listed in Table 1-1:
Table 1-1: Specifications of this research
Value
Input voltage (𝑉in )
0.4𝑉 ± 10%
Output voltage (𝑉out )
1𝑉
Output voltage ripple (𝑉ripple )
< 10𝑚𝑉
Load current (𝐼load )
10𝑚𝐴 (fast charging mode)
1mA (slow charging mode)
Power conversion efficiency (𝜂)
As high as possible
Chip area (A)
As small as possible
Since this is the first time to design a boost DC-DC converter for energy harvesting
application in our team, besides to design a specific circuit which can meet the
specifications, another important task of this research was to build up a systematic design
flow and analysis method of a DC-DC converter design, the aim of which is to provide a
guideline to our team for further design of any other types of DC-DC converters in other
applications. Therefore, in the following chapters, there will be a lot of discussion on how
to choose the best solution to a specific problem occurring in the entire design process
Although the target application of this boost DC-DC converter is RF energy
harvesting, after some slight adjustments of the parameters of the circuit system, this
boost DC-DC converter can actually be used for a wide application range.
1.4 Thesis Outline
This thesis is organized as follows. The basic operating principle and the main power loss
mechanisms of the boost DC-DC converter are introduced in Chapter 2. The preliminary
design of the power plant of the boost DC-DC converter including ways to determine the
values of the inductor and load capacitor as well as the sizes of the power switches is also
1.4 Thesis Outline
9
discussed in Chapter 2. In Chapter 3, general control techniques of the boost DC-DC
converter are discussed and the adaptive on-time/off-time (AOOT) control method with
zero current switching (ZCS) adjustment which is applied in this design is explained. The
detailed transistor-level implementation of the schematic of the boost DC-DC converter is
presented in Chapter 4 together with some important design considerations. The layout
design of the boost converter is described in Chapter 5, which mainly focuses on two
main parts of the circuitry, the MOS transistors used for power switches and the current
mirror array applied in the DAC for ZCS adjustment. The post-layout simulation results
of the boost DC-DC converter designed in this work are presented and discussed in
Chapter 6. Finally, a summary of this thesis project including the contributions,
conclusions and recommendations for future works is made in Chapter 7.
10
Introduction
Bibliography
[1] Chengyuan Wu, “Closed-Loop Stimulation for Epilepsy”, International Neuromodulation
Society,
Thomas
Jefferson
University
Hospital,
Department
of
Neurosurgery, Philadelphia, Pennsylvania, U.S.A, 2012.
URL: http://www.neuromodulation.com/fact_sheet_epilepsy
[2] Brian Olshansky, "Pacemakers and Defibrillators: Frequently Asked Questions,"
University of Iowa Hospitals and Clinics.
URL: http://www.uihealthcare.org/pacemakers-and-defibrillators-frequently-askedquestions
[3] "How Esteem Implants Work," North County Audiology.
http://www.northcountyaudiology.com/hearing-aid-products/esteem-hearing-device-i
mplants/how-esteem-implants-work/
[4] Luis Carlos Gutiérrez Lázaro, "Analysis and Design of MHz-range Wireless Power
Transfer Systems for Implantable Devices," MSc. Thesis, Delft University of
Technology, the Netherlands, 2013.
[5] Erick O. Torres, Gabriel A. Rincón-Mora, "Energy-harvesting chips and the quest for
everlasting life," EE/Times, June 2005.
URL: http://www.eetimes.com/document.asp?doc_id=1273025
[6] Harry Ostaffe, " A brief introduction to RF energy harvesting: what it is, what it does,
and how it enables wireless sensor networking applications," Sensors ONLINE, Oct.
2009.
[7] D. Bouchouicha, F. Dupont, M. Latrach, and L. Ventura, “Ambient RF energy
harvesting,” in IEEE Int. Conf. Renewable Energies Power Quality (ICREPQ’10), pp.
486–495, 2010.
[8] Huyen Le; Fong, N.; Luong, H.C., "RF energy harvesting circuit with on-chip antenna
for biomedical applications," Communications and Electronics (ICCE), 2010 Third
International Conference on, vol., no., pp.115,117, 11-13 Aug. 2010.
[9] Po-Hung Chen; Ishida, K.; Ikeuchi, K.; Xin Zhang; Honda, K.; Okuma, Y.; Ryu, Y.;
Takamiya, M.; Sakurai, T., "Startup Techniques for 95 mV Step-Up Converter by
Capacitor Pass-On Scheme and 𝑉TH -Tuned Oscillator With Fixed Charge
Programming," Solid-State Circuits, IEEE Journal of, vol.47, no.5, pp.1252,1260, May
Bibliography
11
2012.
[10] Po-Hung Chen; Xin Zhang; Ishida, K.; Okuma, Y.; Ryu, Y.; Takamiya, M.; Sakurai, T.,
"An 80 mV Startup Dual-Mode Boost Converter by Charge-Pumped Pulse Generator
and Threshold Voltage Tuned Oscillator With Hot Carrier Injection," Solid-State
Circuits, IEEE Journal of, vol.47, no.11, pp.2554,2562, Nov. 2012.
[11] Visser, H.J.; Vullers, R.J.M., "RF Energy Harvesting and Transport for Wireless
Sensor Network Applications: Principles and Requirements," Proceedings of the
IEEE, vol.101, no.6, pp.1410,1423, June 2013.
[12] Kotani, K.; Sasaki, A.; Ito, Takashi, "High-Efficiency Differential-Drive CMOS Rectifier
for UHF RFIDs," Solid-State Circuits, IEEE Journal of, vol.44, no.11, pp.3011,3018,
Nov. 2009.
[13] Wens, Mike, and Michiel Steyaert. Design and implementation of fully-integrated
inductive DC-DC converters in standard CMOS, Springer, 2011.
12
Introduction
Chapter 2
Basic Principle Analyses and
Preliminary Design
2.1 Basic Working Principle of the Boost DC-DC Converter
The boost DC-DC converter is applied to convert a low-level DC voltage into a highlevel quasi DC voltage. Quasi DC voltage means that the actual output of the boost
converter is a DC voltage along with a small AC voltage ripple. As the AC voltage ripple
is quite small compared to the DC voltage, the output of the boost converter is generally
considered to be a DC voltage. This is also the reason why it is named a DC to DC
converter. Figure 2-1 shows the basic circuit diagram of an inductor-based boost DC-DC
converter. In the boost converter, two power switches are alternatively opened and closed,
which periodically switches of the inductor between the input terminal and output
terminal, thus, achieving the function of boosting the voltage.
L
Vin
Vmid
SwL
SwH
Vout
Cload
Iload
Figure 2-1: Basic Inductor-based boost DC-DC converter.
Based on different waveforms of the inductor current, there are two conduction
modes for the boost converter, which are the continuous conduction mode (CCM) and the
discontinuous conduction mode (DCM), respectively. In CCM, there is always a positive
current existing in the inductor (The positive direction is defined as flowing from the
input terminal to the output terminal). In the ideal case of CCM, one of the power
switches is immediately turned open when the other one is turned closed, which means
14
Basic Principle Analyses and Preliminary Design
there is not a moment (dead time) when two power switches are simultaneously open. In
DCM, the current flowing through the inductor will go down to zero and stay in zero for
some while, which means there is a period of time (dead time) when the two power
switches will be both open.
Before analyzing the basic working principle of the boost DC-DC converter working
in CCM or DCM, some general assumptions should be made first. Based on these
assumptions, it will be easy to describe the waveforms of the boost converter. A detailed
theoretical analysis of this method has been provided in Erickson’s book [1], in which it
is named the small-ripple approximation method. The assumptions include:
(1) The converter operates in the steady state. This means that the system parameters
including the input voltage, output voltage and the load current are all constant. For the
boost converter, it also means that the start-up phase has been passed.
(2) The ripple of the output voltage is very small with respect to the average (DC)
value of the output voltage. It means that the output voltage is regarded as a DC voltage.
(3) All the components of the converter are ideal and lossless. It means that the
parasitic effects of the inductor, the capacitor and the MOS transistors are all ignored.
(4) The relationship between the voltage and the current for the inductor and the
capacitor are all linear. It means that the voltage across the inductor and the current
flowing out of the capacitor should always satisfy the basic equations:
𝑉L = 𝐿 ∙
𝑑𝑖L
𝑑𝑡
(2.1)
𝐼C = 𝐶 ∙
𝑑𝑣C
𝑑𝑡
(2.2)
Based on these assumptions, the working principle of the boost converter will be
explained as follows. When the low-side power switch (𝑆𝑤L ) is closed and the high-side
power switch (𝑆𝑤H ) is open, the converter works in the on-time phase. In this phase, the
structure and the waveforms of the converter are shown in Figure 2-2. As the middle
point of the converter is connected to ground, the voltage at this point (𝑉mid ) is zero.
According to Equation 2.1, the current flowing through the inductor (𝑖L ) increases by a
constant ratio, which is:
𝑑𝑖L
𝑑𝑡
=
𝑉in
𝐿
(2.3)
As for the output voltage of the converter (𝑉out), since the load capacitor is loaded with
a constant current source, the output voltage decreases by a constant ratio, which is:
𝑑𝑣out
𝑑𝑡
𝐼
= 𝐶load
load
(2.4)
After the on-time phase, the boost converter enters into the off-time phase, in which, the
low-side power switch (𝑆𝑤L ) is open and the high-side power switch (𝑆𝑤H ) is closed. The
structure and the waveforms of the converter in this phase are shown in Figure 2-3. Since
the middle point of the converter is connected to the output, the voltage of this point
(𝑉mid ) is approximately equal to the DC value of the output voltage (𝑉out_dc). Therefore,
Basic Working Principle of the DC-DC Converter
15
the current flowing through the inductor (𝑖L ) can be regarded as decreasing by a constant
ratio, which is
𝑑𝑖L
𝑑𝑡
=
𝑉out_dc −𝑉in
(2.5)
𝐿
In this phase, the load capacitor is not only discharged by the constant load current but
also charged by the inductor releasing current which is expressed by Equation 2.5. Hence,
in the off-time phase, the output voltage satisfies that:
𝑑𝑣out
𝑑𝑡
L
=
𝑖L −𝐼load
𝐶load
Vout
Vmid
Cload
ton
toff
0V
Vout_dc
iL
Iload
Vin
(2.6)
Vmid
Vout
(b)
(a)
Figure 2-2: Boost DC-DC converter in the on-time phase.
L
Vmid
Vout
Iload
Cload
Vin
ton
toff
0V
Vout_dc
iL
Vmid
Vout
(a)
(b)
Figure 2-3: Boost DC-DC converter in the off-time phase.
ton
toff
ton
toff
0V
Vout_dc
0V
Vout_dc
iL
Vmid
Vout
SwL
SwH
Figure 2-4: Timing diagram of main signals in a CCM boost converter.
16
Basic Principle Analyses and Preliminary Design
For the boost converter working in CCM, there are only two phases, one of which is
the on-time phase and the other is the off-time phase. The working principle of a CCM
boost DC-DC converter can be illustrated by the timing diagram of the main signals in
the converter, which is shown in Figure 2-4. However, for the boost converter working in
DCM, since there is a period of time when two power switches are both open, an
additional phase which is named the dead-time phase exists in the switching period of the
DC-DC converter. In the dead-time phase, the structure and the waveforms of the boost
converter are shown in Figure 2-5. Since both switches are open, the voltage of the
middle point (𝑉mid) is equal to the input voltage, which means the voltage across the
inductor and the current through the inductor are both zero. The output of the converter is
in the same condition as during in the on-time phase. Therefore, the output voltage
decreases by the ratio which has been expressed in Equation 2.4. The timing diagram of
the main signals in the DCM boost DC-DC converter is shown in Figure 2-6.
L
Vmid
ton
Vout
Iload
Cload
Vin
toff
tdead
iL
0A
Vmid
0V
Vout
Vin
Vout
(a)
(b)
Figure 2-5: Boost DC-DC converter in the dead-time phase.
ton
toff tdead
iL
Vmid
ton
toff tdead
0A
0V
Vout
Vin
0A
0V
Vout
Vin
Vout
SwL
SwH
Figure 2-6: Timing diagram of the main signals in a DCM boost converter.
From the discussion above, we can see that the working condition of a DC-DC
converter is determined by the power switches. Therefore, in the entire system of a
DC-DC converter, apart from the circuit shown in Figure 2-1 (normally named as the
Basic Working Principle of the DC-DC Converter
17
power plant of a DC-DC converter), there should be a control system that is used to
automatically control the opening and closing of the power switches alternatively. The
detailed discussion on the control system will be given in the next chapter.
The voltage conversion ratio (𝑘) which is the ratio of the output voltage over the
input voltage is an important parameter for a DC-DC converter. In a specific application,
this value is usually required to be fixed. Therefore, knowing its relationship with other
parameters will be very helpful for the design of a DC-DC converter. However, for the
converters working in different conduction modes (CCM or DCM), the expressions of
this value are quite different. For the converters working in CCM, this value is only
related to the duty cycle (𝐷). But for the converters working in DCM, this value depends
not only on the duty cycle (𝐷) but also on the inductor value (𝐿) and the load resistor (𝑅L ).
The derivation of the expressions is normally based on the volt-second balance of the
inductor. Since in steady state and regardless of the losses the net energy change in the
inductor over a switching period is zero, the volt-second balance of the inductor is also
zero [2], which can be expressed:
𝑇
∫0 𝑉L (𝑡)𝑑𝑡 = 𝑉in 𝑡on + (𝑉in − 𝑉out ) 𝑡on = 0
(2.7)
Therefore, for the converters working in CCM, it holds
𝑘=
𝑉out
𝑉in
=
𝑡on +𝑡off
𝑡off
=
𝑇
𝑡off
=
1
1−𝐷
,
(2.8)
for the converters working in DCM, it holds
𝑘=
𝑉out
𝑉in
=
2𝑅L
𝑡2
𝐿(𝑡on +𝑡off +𝑡dead ) on
1+√1+
2
=
2𝑅L 𝑇𝐷2
𝐿
1+√1+
2
,
(2.9)
in which 𝑡on , 𝑡off and 𝑡dead represent the durations of the on-time, the off-time and the
dead-time, respectively. 𝑇 is the total switching period. The detailed mathematic
derivation of these equations is introduced in [2]. In this thesis, no more discussions about
the mathematic derivation will be given. We just want to mention that, according to
Equations 2.8 and 2.9, how the parameter variations affect the DC-DC converter can be
clearly observed. Therefore, these two expressions are quite useful for the design of a
DC-DC converter.
The circuit shown in Figure 2-1 is normally named a synchronous boost DC-DC
converter, in which two power switches are applied to control the converter. In some
applications, since a diode can implement the same function as the power switch does, the
high-side power switch can be replaced by a diode, as shown in Figure 2-7. The DC- DC
converter in this structure is also named an asynchronous DC-DC converter. However,
due to the high forward voltage drop, it would be inefficient to use a diode for the
high-side switch [3], especially in low-voltage electronic circuit design such as this work
(the maximum voltage is about 1V). In a DC-DC converter, the voltage drop across the
power switch or the diode is expected to be as small as possible, since a high voltage drop
will cause a large power loss. For Schottky diodes, the typical forward drop voltage drop
18
Basic Principle Analyses and Preliminary Design
is about 200-300mV [4], which is too high to use in this work. Although there are some
techniques which can be used to implement a diode with a low forward voltage drop [4]
[5], the circuit implementations are all quite complex and will consumes much extra
power. In this work, the synchronous structure is finally used for the DC-DC converter
design, which can not only simplify the design work but also achieve a relatively low
voltage drop across the high-side switch. The final simulation results (in Chapter 6) show
that the maximum value of this voltage is less than 50mV.
L
Vin
Vmid
SwL
Vout
Cload
Iload
Figure 2-7: Asynchronous boost DC-DC converter.
In the previous discussion about the working principle of the boost DC-DC converter,
we have assumed that the boost converter works in the steady state. But before reaching
the steady state, the boost converter has to undergo a startup phase. During the startup
phase, the output voltage of the converter rises from zero to the steady value.
Since the circuit blocks of the control system require a sufficient supply voltage to
work, there should be a high enough voltage that can be used to power the control system.
In the buck DC-DC converter, the input voltage is usually high enough to provide the
supply voltage for the control system, so the supply voltage can be obtained directly from
the input voltage or through a voltage divider. But in the boost DC-DC converter, in some
cases, the input voltage is too low to provide the supply voltage for the control system, so
the output voltage is used to power the control system when the boost converter works in
the steady state. But during the startup phase, as the output voltage starts from zero, there
will is some time when the output voltage is not high enough. Therefore, an external
circuit is usually required to generate the supply voltage for a while until the output
voltage arises to a sufficient value. Then the output voltage is used for the supply voltage,
and the external circuit is switched off.
Many startup mechanisms have been proposed in previous studies. For instance, an
extra auxiliary voltage [2] or battery [6] is used to charge the output of the converter to
the minimum supply voltage during the startup phase; and in [7], a mechanical switch is
applied to transform vibration mechanical energy into electrical energy to provide the
startup voltage for the converter; in [8], an inductor-based transformer is used to form a
positive feedback loop which can amplify the thermal noise to generate the startup
voltage; in [9], an RF energy harvester is used with a multi-stage voltage doubler to
Basic Working Principle of the DC-DC Converter
19
generate the startup voltage. Among these methods, the last one which is reported in [9]
seems to be a suitable candidate for this work. As mentioned in Section 1.1, since the RF
energy harvester with a several-stage voltage doubler rectifier has been utilized to
generate the 0.4𝑉 input voltage for the boost DC-DC converter in this work, we can add
some additional stages to create a voltage doubler rectifier. These additional stages of the
voltage doubler rectifier are only used for the startup mechanism. After the startup phase,
these stages will be switched off.
The specific design of the startup mechanism is not included in this work. From the
simulation results shown in Chapter 6, it can be observed that the minimum supply
voltage for the control system of the boost DC-DC converter designed in this work is
about 0.7𝑉. Therefore, the whole design of this thesis project is based on the assumption
that the load capacitor has had an initial voltage of 0.7𝑉. The startup mechanism can be
studied in future work.
2.2 Power Loss Mechanism
The power conversion efficiency is normally the major consideration for DC-DC
converters, especially for those found in portable devices where prolonging the battery
life is a key goal [10]. In this design, since the target application of the boost DC-DC
converter is in an RF energy harvesting system, the power conversion efficiency is
definitely the principal specification. To achieve maximum power conversion efficiency
in a DC-DC converter, it is very helpful to understand the power loss mechanisms. If all
the main sources of power losses in a DC-DC converter are clearly known, the proper
efforts can be made on optimization of the power conversion efficiency.
The power losses of a DC-DC converter system can generally be divided into two
categories, which are the conduction losses and the switching losses. The conduction
losses are induced by the mean DC current flowing through the parasitic or equivalent
resistances. The switching losses are induced by the periodical variations of the current
through or the voltage across the components such as the inductor or the power switches
of the converter. As mentioned in [11], it is usually easy to calculate the conduction losses,
since only the average current and the resistances are required to know. But for the
switching losses, because they depend on many variables, any calculations are only a
rough approximation and can be far away from the real value found in the actual design,
particularly at high switching frequencies [11]. Therefore, only five fundamental power
losses are normally considered during the practical analysis of the power loss mechanism
of a DC-DC converter. The five power losses are: (1) the conduction loss of the power
switches; (2) the switching loss of the power switches; (3) the conduction loss of the
inductor DCR (DC resistance); (4) the loss of the load capacitor ESR (equivalent series
resistance); (5) the power consumption of the control circuit.
For a synchronous DC-DC converter in CMOS technology, the conduction losses of
20
Basic Principle Analyses and Preliminary Design
the power switches are caused by the turn-on resistances of the MOSFET transistors.
When there are currents flowing through the closed power switches, energy will be
consumed by the MOSFET turn-on resistances. The conduction losses of the low-side and
the high-side MOSFET power switches can be expressed as:
𝑃C_lsw =
𝑅on_lsw
𝑃C_hsw =
𝑅on_hsw
𝑇
𝑡lsw 2
𝑖L (𝑡) 𝑑𝑡
∫0
𝑇
(2.10)
𝑡hsw 2
𝑖L (𝑡) 𝑑𝑡
∫0
,
(2.11)
in which 𝑅on_lsw and 𝑅on_hsw are the MOSFET turn-on resistances; 𝑡lsw and 𝑡hsw
represent the durations of the time when the low-side switch and high-side switch are
closed, respectively; 𝑖L is the inductor current; 𝑇 is the switching period of the DC-DC
converter. According to Equation 2.10 and 2.11, it can be seen that the conduction losses
of the power switches are only determined by the inductor current and the MOSFET
turn-on resistance. Since the inductor current is related to many other variables such as
the switching frequency or input/output voltage, the available method to reduce this loss
is to reduce the turn-on resistance of the MOS power switch. The general equation of the
MOSFET turn-on resistance (𝑅on ) can be expressed as [12]:
𝑅on =
1
(2.12)
𝑊
𝐿
𝜇𝐶ox (𝑉gs −𝑉th )
Assuming the gate driving voltage (𝑉gs ) is limited by supply, which means no voltage
boosting technique is used, the only variation that can be used to adjust the turn-on
resistance is the aspect ratio (𝑊/𝐿). Therefore, using transistors with large aspect ratios is
the only way to reduce the turn-on resistances thus reducing the conduction losses of the
MOSFET power switches.
Compared to the conduction losses, the switching losses of the power switches are
less intuitive. Since the MOSFET power switches require some time to change their
on/off states, some energy will be consumed during the transition time. This loss
mechanism can be explained with the aid of Figure 2-8. As shown in Figure 2-8, due to
the overlap of the non-zero current and the non-zero voltage during the transition time,
energy will be lost on the transistor. Figure 2-8a shows the best-case scenario, in which,
the voltage across the transistor and the current through the transistor start changing
simultaneously and also reach their final values simultaneously. Figure 2-8b shows the
worst-case scenario (which is closer to reality) [11], in which, the voltage or the current
starts changing until the other one reaches its final value. The switching loss of the power
switch in the best case or the worst case can be expressed by Equations 2.13 and 2.14.
𝑡
1
𝑡
𝑃S_sw_b = 𝑇 (∫0 o 𝑉ds 𝐼ds 𝑑𝑡 + ∫0 c 𝑉ds 𝐼ds 𝑑𝑡)
1
𝑡 +𝑡vf
𝑃S_sw_w = 𝑇 (∫0 cr
𝑡 +𝑡cf
𝑉ds 𝐼ds 𝑑𝑡 + ∫0 vr
𝑉ds 𝐼ds 𝑑𝑡) ,
(2.13)
(2.14)
in which 𝑇 is the switching period of the DC-DC converter. In Equations 2.13 and 2.14,
since only the transition times (𝑡o , 𝑡c , 𝑡cr , 𝑡vf , 𝑡vr , 𝑡cf) can be independently adjusted, the
Power Loss Mechanism
21
available way to reduce the switching losses of the power switches is to reduce these
transition times. However, in order to further reduce the transition times, larger buffers
are required to drive the power switches. The larger buffer with stronger driving ability
will also consume more energy, which perhaps leads to a result opposite to what is
designed. Therefore, the trade-off between the transition time of the power switch and the
driving ability of the buffer should be considered when the switching losses of the power
switches are improved.
to
Transition
tc
Vds
V/I
Ids
0
t
(a)
tcr
tvf Transition tvr
V/I
tcf
Vds
Ids
t
0
(b)
Figure 2-8: Switching waveforms of the transistor
(a) in the best-case scenario; (b) in the worst-case scenario.
The conduction loss of the inductor is caused by the DC resistance (DCR) of the
inductor. The inductor DCR is actually the winding resistance which is determined by the
size and structure of the inductor. When there is current flowing through the inductor,
energy will be consumed on the inductor due to the DCR. This loss can be expressed as:
𝑃L_DRC =
𝑅dc_L
𝑇
𝑇
2
∫0 𝑖𝐿 (𝑡) 𝑑𝑡 ,
(2.15)
in which 𝑅dc_L is the inductor DCR; 𝑖L is the inductor current and 𝑇 is the switching
period of the DC-DC converter. It is obvious that the available way to reduce the
conduction loss of the inductor is using an inductor with a low DCR.
The loss mechanisms generated by the load capacitor are complex. As mentioned in
[10], for simplifying the loss model, the actual losses including the contact resistance,
leakage and dielectric losses are lumped together into an individual power-loss element
named “equivalent series resistance” (ESR). The loss of the ESR can represent the overall
power losses of the load capacitor, which can be expressed as:
𝑃C_ESR =
𝑅CESR
𝑇
𝑇
2
∫0 𝑖C (𝑡)𝑑𝑡
(2.16)
in which 𝑅C_ESR is the ESR of the load capacitor , 𝑇 is the switching period of the
22
Basic Principle Analyses and Preliminary Design
DC-DC converter and 𝑖C is the current flowing through the load capacitor ESR. 𝑖C can
be expressed as:
𝑖C (𝑡) = 𝑖load (𝑡) − 𝑖L (𝑡) ,
(2.17)
in which 𝑖load is the load current and 𝑖L is the inductor current. Since manufactures
usually offer data about ESR values of their capacitors, a capacitor with a low ESR can be
used in a DC-DC converter in order to reduce the loss of the load capacitor.
The loss mechanisms mentioned above are all caused by the components (inductor,
power switches and load capacitor) in the power plant of the DC-DC converter. Besides,
the circuit blocks in the control system such as the comparator, amplifier or digital circuit,
will also consume some power to maintain the operation of the DC-DC converter.
Normally, the DC-DC converter works in the high load current condition, which means
that the load current is much higher than the driving current of the control system. In this
case, the power consumption of the control system is generally neglected. But when the
load current of the DC-DC converter becomes very low, the power consumption of the
control system will take a great part of the total loss. In this case, ultra-low power
technology should be used for the circuit design of the control system.
After the analyses of the five fundamental loss mechanisms of the DC-DC converter,
the total power loss of the converter can be approximated by the sum of these losses:
𝑃loss = 𝑃C_hsw + 𝑃C_lsw + 𝑃S_hsw + 𝑃S_lsw + 𝑃DCR_L + 𝑃ESR_C + 𝑃control
(2.18)
Moreover, the output power (𝑃out ) is usually easy to obtain by the product of the output
voltage and the load current. Therefore, the power conversion efficiency (𝜂) of the
DC-DC converter can be expressed as:
𝜂=
𝑃out
𝑃in
=𝑃
𝑃out
out +𝑃loss
(2.19)
2.3 Preliminary Design of the Power Plant
For the design of a DC-DC converter, the first step is normally to determine the
parameters of the components in the power plant, which include the sizes of the power
switches, the inductance of the inductor and the capacitance of the load capacitor.
Compared to the design of the control system, the importance of this step seems to be
often neglected by designers, as few discussions about this step have been reported [13]
[14]. In fact, since the majority of the power loss of a DC-DC converter stems from the
components in the power plant rather than the circuit of the control system, an elaborate
design of the power plant will make much contribution to achieving a high efficient
DC-DC converter design. In this section, the preliminary design of the power plant of the
boost DC-DC converter for this project will be described.
The design specifications of this work have been listed in Table 1.1 in Section 1.3.
The design of the power plant should be based on these system parameters including the
Preliminary Design of the Power Plant
23
input voltage (𝑉in ), the output voltage (𝑉out ), the output voltage ripple (𝑉o_ripple ) and the
load current (𝐼load ). At first, let us analyze and roughly calculate the waveform of the
inductor current. Since the pulse frequency modulation (PFM) adaptive on-time/off-time
(AOOT) control technique is applied in this work, the boost converter will work in DCM
and the switching period of the boost converter will be changed with the variation of the
load current. If the input voltage and the output voltage are fixed, the on-time and the
off-time will be constant. When the boost converter works in the maximum load current,
the switching period will be shortest due to the minimum dead time. When the boost
converter works in the light load current, then the switching period will be increased by
increasing the dead time. The detailed working principle of the control technique will be
explained in Section 3.4.
For high power efficiency, the duration of the dead-time is expected to be as short as
possible when the boost converter works with the maximum load current. In this work,
the maximum load current is 10𝑚𝐴. Therefore, when the boost converter works with a
10𝑚𝐴 load current, in the ideal case, the dead-time should be zero. At this moment, the
boost converter works at the boundary of DCM and CCM. The waveform of the inductor
current is shown in Figure 2-9. Then the average value and the peak value of the inductor
current can be calculated as follows.
IL
ton
toff
ton
toff
IL_peak
t
0
Figure 2-9: Waveform of the inductor current for the boost converter working in the
boundary of CCM and DCM.
The output power of the boost converter can be derived from Equation 2.20.
𝑃out = 𝑉out ∙ 𝐼load = 1𝑉 ∙ 10𝑚𝐴 = 10𝑚𝑊
(2.20)
If we assume the power conversion efficiency (𝜂) is 95%, then the input power of the
boost converter is:
𝑃in =
𝑃out
𝜂
=
10𝑚𝑊
0.95
≈ 10.53𝑚𝑊
(2.21)
Meanwhile, the input power is also equal to the product of the input voltage and the
average input current. For a boost DC-DC converter, since the inductor is always
connected to the input terminal, the average inductor current is equal to the average input
current. Hence, the average value of the inductor current (𝑖L_ave) is:
24
Basic Principle Analyses and Preliminary Design
𝑃
𝑖L_ave = 𝑖in_ave = 𝑉in =
in
10.53𝑚𝑊
0.4𝑉
= 26.325𝑚𝐴
(2.22)
If the waveform of the inductor current is triangular, as shown in Figure 2-9, the
relationship between the average value of the inductor current (𝑖L_ave ) and the peak value
of the inductor current (𝐼L_peak) can be expressed by Equation 2.23.
𝑇
1
2
𝑖L_ave = ∫0 𝑖𝐿 (𝑡) ∙ 𝑑𝑡 = 𝐼L_peak
(2.23)
So, the peak value of the inductor current is:
𝐼L_peak = 2 ∙ 𝑖L_ave = 52.65𝑚𝐴
(2.24)
This result is obtained by the mathematical calculation based on many ideal assumptions.
In reality, due to the un-ideal factors such as the voltage drops over the inductor and the
power switches, the peak value of the inductor current should be a little higher than the
calculation result.
The sizes of the MOSFET power switches can be determined from the peak value of
the inductor current and the acceptable voltage drops across over the power switches.
Apart from Equation 2.12, the turn-on resistance of the MOSFET power switches can
also be expressed by:
𝑅on =
𝑉ds
𝐼ds
(2.25)
Therefore, if we know the maximum current flowing through the switch transistor and its
acceptable maximum crossover voltage drop, the aspect ratio (𝑊/𝐿) of the transistor can
be obtained. For the power switches of the DC-DC converter, the maximum current is
equal to the peak value of the inductor current. In this work, the calculation result of the
peak value of the inductor current is 52.65𝑚𝐴. But in consideration of the un-ideal
factors, this value can be roughly approximated as 60𝑚𝐴. The acceptable maximum
voltage drop across over the power switch (𝑉ds_max) is expected to be 20mV in this work.
Then, the aspect ratios of the NMOS and the PMOS power switch transistors can be
obtained by Equations 2.26 and 2.27.
𝑊
𝐿
( )𝑛 =
𝐼L_peak
(2.26)
𝜇𝑛 𝐶ox (𝑉gsn −𝑉thn )𝑉ds_max
𝐼L_peak
𝑊
( 𝐿 )𝑝 = 𝜇
𝑝 𝐶ox (𝑉gsp −𝑉thp )𝑉ds_max
,
(2.27)
in which 𝑉gsn and 𝑉gsp are the gate voltages of the power switches, which are both equal
to 1𝑉 in this design; 𝜇𝑛 , 𝜇𝑝 , 𝐶ox , 𝑉thn and 𝑉thp are the technological parameters,
which can be found in the technical files. After a rough calculation, the aspect ratios of
the power switches are:
𝑊
𝐿
60𝑚𝐴
200𝜇𝐴/𝑉 2 ∙(1𝑉−0.55𝑉)∙20𝑚𝑉
𝑊
60𝑚𝐴
( )𝑛 ≈
≈ 3.3 × 104
( 𝐿 )𝑝 ≈ 70𝜇𝐴/𝑉 2 ∙(1𝑉−0.55𝑉)∙20𝑚𝑉 ≈ 11 × 104
(2.28)
(2.29)
Preliminary Design of the Power Plant
25
The mathematic derivation only provides an elementary estimation in order to
simplify the design work. The final decision of the aspect ratios of the power switches
should be made on the base of the simulation results and some other considerations. In
this work, based on the simulation results of a parameter sweep and under the
consideration of layout simplification, the sizes of the low-side NMOS power switch and
the high-side PMOS power switch are determined. The parameters of the power switches
are listed in Table 2-1.
Table 2-1: Parameters of the MOSFET power switches
Width (W)
Length (L)
Aspect ratio (W/L)
Low-side NMOS power switch
3.584𝑚𝑚
100𝑛𝑚
3.584 × 104
High-side PMOS power switch
7.168𝑚𝑚
100𝑛𝑚
7.168 × 104
The inductance of the inductor in the power plant is generally related to the
switching frequency of the DC-DC converter. In general, increasing the inductance of the
inductor can reduce the switching frequency of the DC-DC converter. Therefore, during
the selection of an inductor for the DC-DC converter, the issue of the switching frequency
should be taken into consideration. The relationship between the inductance of the
inductor (𝐿) and the switching frequency (𝑓sw) of the boost DC-DC converter designed in
this work can be obtained from the following derivation.
According to Equation 2.1, we can get Equation 2.30 and 2.31 which express the
voltage and current conditions of the inductor during the on-time phase (2.30) and
off-time phase (2.31).
𝑉in = 𝐿 ∙
𝐼L_peak
(2.30)
𝑡on
𝑉out − 𝑉in = 𝐿 ∙
𝐼L_peak
(2.31)
𝑡off
Since the input and output voltage of the boost converter are known, the ratio of the
on-time (𝑡on ) and the off- time (𝑡off ) can be determined.
𝑡on
𝑡off
=
𝑉out −𝑉in
𝑉in
=
1𝑉−0.4𝑉
0.4𝑉
3
=2
(2.32)
When the boost converter works at the boundary of DCM and CCM, the switching period
(𝑇) of the boost converter is equal to the sum of the on-time and the off-time (𝑇 = 𝑡on +
𝑡off ). So we can get:
3
𝑡on = 5 𝑇
2
𝑡off = 5 𝑇
(2.33)
(2.34)
26
Basic Principle Analyses and Preliminary Design
According to Equations 2.30 and 2.33, we can obtain:
𝐿 ∙ 𝑓sw =
3∙0.4𝑉
5∙60𝑚𝐴
= 4 𝜇𝐻/𝑀𝐻𝑧 ,
(2.35)
in which 𝑓sw is the switching frequency, which is equal to the reciprocal of the switching
period (𝑓sw = 1/𝑇). Hence, Equation 2.35 shows the relationship between the inductor
inductance (𝐿) and the switching frequency (𝑓sw ) in this work. It means if a 1𝜇𝐻
inductor is used in the boost DC-DC converter, the maximum switching frequency of the
boost converter will be about 4𝑀𝐻𝑧; if a 10𝜇𝐻 inductor is used, the maximum
switching frequency will be about 400𝑘𝐻𝑧.
In this work, since there is not any specific requirement or limitation on the
switching frequency, the determination of the inductor inductance and the switching
frequency will be made in consideration of the power conversion efficiency. As discussed
in Section 2.2, the inductor inductance and the switching frequency will affect the power
conversion efficiency mainly through changing the conduction loss of the inductor DCR
and the switching losses of the power switches. Therefore, the inductor inductance will be
determined in order to achieve the minimum power losses mentioned above.
V/I
tvf
Transition
tvr tcf
Vds
Ids
0
t
(a)
V/I
tcr tvf
Transition
tvr
Vds
Ids
0
t
(b)
Figure 2-10: Switching waveforms of the transistor
(a) in the best-case scenario; (b) in the worst-case scenario.
The conduction loss of the inductor DCR and the switching loss of the power switch
are expressed by Equations 2.15 and 2.14 (assuming the worst-case scenario). But for the
boost DC-DC converter designed in this work, the voltage and current waveforms of the
two power switches are not similar to what was shown in Figure 2-8b. For the low-side
NMOS power switch, the initial current through the switch is close to zero at the moment
when it is turned on. At the moment when the switch is turned off, the initial current
Preliminary Design of the Power Plant
27
through the switch is equal to the peak current of the inductor which is about 60𝑚𝐴
given by a previous calculation. For the high-side PMOS power switch, the initial current
through the switch is equal to the peak current of the inductor (60mA) when it is turned
on. And the initial current through the switch is about zero when it is turned off.
Therefore, the waveforms of the two power switches are shown in Figure 2-10.
According to Equation 2.16, the switching losses of the low-side NMOS power switch
and the high-side PMOS power switch can be expressed as:
1
𝑡 +𝑡vf
𝑃S_nsw = 𝑇 (∫0 cr
𝑡 +𝑡cf
𝑉ds 𝐼ds 𝑑𝑡 + ∫0 vr
𝑉ds 𝐼ds 𝑑𝑡)
1
= 2 𝑉ds 𝐼ds (𝑡vr + 𝑡cf ) ∙ 𝑓sw
1
𝑡 +𝑡vf
𝑃S_psw = 𝑇 (∫0 cr
𝑡 +𝑡cf
𝑉ds 𝐼ds 𝑑𝑡 + ∫0 vr
(2.36)
𝑉ds 𝐼ds 𝑑𝑡)
1
2
= 𝑉ds 𝐼ds (𝑡cr + 𝑡vf ) ∙ 𝑓sw
(2.37)
Table 2-2: Candidates of the inductors for the comparison
Production No.
L
Rdc (Max.)
CLF6045T-100M
10𝜇𝐻
45.6𝑚𝛺
CLF7045T-1R0N
1𝜇𝐻
12.48𝑚𝛺
VLB7050HT-R11M
110𝑛𝐻
0.286𝑚𝛺
Table 2-3: Calculation results of the power losses with different inductors
Production No.
𝑃DCR_L
𝑃S_nsw
𝑃S_psw
𝑃sum
CLF6045T-100M
30.83𝜇𝑊
0.48𝑢𝑊
0.72𝑢𝑊
32.03𝑢𝑊
CLF7045T-1R0N
8.4𝜇𝑊
4.8𝑢𝑊
7.2𝑢𝑊
20.4𝑢𝑊
VLB7050HT-R11M
0.19𝜇𝑊
43.2𝑢𝑊
64.8𝑢𝑊
108.19𝑢𝑊
Based on Equation 2.15, 2.36 and 2.37, a comparison can be made to determine
which value is the best choice for the inductance of the inductor. The candidates of the
comparison are three inductors of TDK Company [15]. The production number and their
parameters are shown in Table 2-2. After substituting these parameters into Equations
2.15, 2.36 and 2.47, we can get the calculation results that are shown in Table 2-3. In this
design, 𝑉ds of the low-side NMOS transistor is about 0.4𝑉and 𝑉ds of the high-side
28
Basic Principle Analyses and Preliminary Design
PMOS transistor is about 0.6𝑉. 𝐼ds of these two transistors are both equal to 60𝑚𝐴.
The sum of 𝑡vr and 𝑡cf for the low-side NMOS transistor and the sum of 𝑡cr and
𝑡vf of the high-side NMOS transistor are both set to be about 100ps.
From the calculation results, it can be concluded that the inductor with a 1𝜇𝐻
inductance is relatively the best choice in this design. Although a larger inductor will
effectively reduce the switching losses of the power switches, the conduction loss of the
inductor will be seriously increased. A smaller inductor can dramatically decrease the
conduction loss of the inductor, but the switching losses of the power switches will badly
arise as well. Therefore, in this work, we finally choose “CLF7045T-1R0N” [16] as the
inductor in the boost DC-DC converter. According to the SPICE netlist provided from the
TDK website, the equivalent schematic model of the inductor is shown in Figure 2-11.
C=106.2fF
L=1u
R2 =9.6mΩ
R1 =33.5KΩ
Figure 2-11: Equivalent schematic model of the inductor “CLF7045T-1R0N”.
When the inductance of the inductor is decided to be 1𝜇𝐻, according to Equation
2.33, 2.34 and 2.35, we can obtain that the ideal values of the switching period, the
on-time and the off-time of the boost converter should be:
1
𝑇=𝑓
sw
𝐿
= 4 𝜇𝐻/𝑀𝐻𝑧 = 250𝑛𝑠
3
𝑡on = 5 𝑇 = 150𝑛𝑠
2
𝑡off = 5 𝑇 = 100𝑛𝑠
(2.38)
(2.39)
(2.40)
For the boost DC-DC converter designed in this work, the selection of the load
capacitor is only determined by the limitation on the output voltage ripple. When the
boost DC-DC converter works in DCM or at the boundary of DCM and CCM, the output
voltage ripple (𝑉o_ripple ) can be written as:
𝑉o_ripple =
𝑖load ∙(𝑡on +𝑡dead )
𝐶load
(2.41)
In this work, when the load current of the boost converter is 10𝑚𝐴, the maximum output
voltage ripple is expected to be lower than 10mV, (𝑉o_ripple < 10𝑚𝑉). Moreover, in the
Preliminary Design of the Power Plant
29
ideal case, the converter works at the boundary of DCM and CCM, which means the dead
time (𝑡dead ) is zero. Therefore, we can derive:
𝑡
𝐶load > 𝑉on
∙𝑖load
o_ripple
> 150𝑛𝐹
(2.42)
But in the real implementation of the control technique of the boost converter, the
dead-time is larger than zero when the load current is 10𝑚𝐴. (The detailed explanation of
the control technique applied in this design will be given in the next chapter.) As a result,
to guarantee the requested output voltage ripple, a little larger capacitor should be
selected for the load capacitor. Finally, the capacitance of the load capacitor is determined
to be 220𝑛𝐹. Since the equivalent schematic model of a capacitor is like what will be
shown in Figure 2-12, the parasitic inductance of the load capacitor will introduce some
spikes to the output of the DC-DC converter. Therefore, to reduce this effect, some small
capacitors in parallel can be used to implement the load capacitor. In this work, ten
22𝑛𝐹 capacitors are used to achieve the total capacitance of the load capacitor(s)
is 220𝑛𝐹. To reduce the power loss of the load capacitor ESR, a capacitor with a low
ESR should be chosen. Finally, the capacitor “C0603JB0J223K030BC” [17] with a
22𝑛𝐹 capacitance is applied in this work. Based on the SPICE netlist provided by TDK,
the equivalent schematic model of the capacitor is shown in Figure 2-12.
C=22nF
L=300p
R1 =53.3mΩ
R2 =110GΩ
Figure 2-12: Equivalent schematic model of the capacitor “C0603JB0J223K030BC”.
So far, the preliminary design of the power plant of the boost DC-DC converter has
been finished. Based on the conclusions made above, the control system of the boost
DC-DC converter can be designed in the next step. The discussion on the design of the
control system will be given in following chapters.
30
Basic Principle Analyses and Preliminary Design
Bibliography
[1] Erickson, Robert W., and Dragan Maksimovic. Fundamentals of power electronics,
Springer, 2001.
[2] Wens, Mike, and Michiel Steyaert. Design and implementation of fully-integrated
inductive DC-DC converters in standard CMOS, Springer, 2011.
[3] Carlson, E.J.; Strunz, K.; Otis, B.P., "A 20 mV Input Boost Converter With Efficient
Digital Control for Thermoelectric Energy Harvesting," Solid-State Circuits, IEEE
Journal of, vol.45, no.4, pp.741,750, April 2010.
[4] Kotani, K.; Sasaki, A.; Ito, Takashi, "High-Efficiency Differential-Drive CMOS Rectifier
for UHF RFIDs," Solid-State Circuits, IEEE Journal of, vol.44, no.11, pp.3011,3018,
Nov. 2009.
[5] Van Liempd, C.; Stanzione, S.; Allasasmeh, Y.; van Hoof, C., "A 1µW-to-1mW energyaware interface IC for piezoelectric harvesting with 40nA quiescent current and
zero-bias active rectifiers," Solid-State Circuits Conference Digest of Technical
Papers (ISSCC), 2013 IEEE International, vol., no., pp.76,77, 17-21 Feb. 2013.
[6] Doms, I.; Merken, P.; Mertens, R.; Van Hoof, C., "Integrated capacitive powermanagement circuit for thermal harvesters with output power 10 to 1000µW,"
Solid-State Circuits Conference-Digest of Technical Papers, 2009. ISSCC 2009.
IEEE International, vol., no., pp.300, 301,301a, 8-12 Feb. 2009.
[7] Ramadass, Y.K.; Chandrakasan, A.P., "A batteryless thermoelectric energyharvesting interface circuit with 35mV startup voltage," Solid-State Circuits
Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, vol., no.,
pp.486,487, 7-11 Feb. 2010.
[8] Jong-Pil Im; Se-Won Wang; Seung-Tak Ryu; Gyu-Hyeong Cho, "A 40 mV
Transformer-Reuse
Self-Startup
Boost
Converter
With
MPPT
Control
for
Thermoelectric Energy Harvesting," Solid-State Circuits, IEEE Journal of, vol.47,
no.12, pp.3055,3067, Dec. 2012.
[9] Yanqing Zhang; Fan Zhang; Shakhsheer, Y.; Silver, J.D.; Klinefelter, A.; Nagaraju, M.;
Boley, J.; Pandey, J.; Shrivastava, A.; Carlson, E.J.; Wood, A.; Calhoun, B.H.; Otis,
B.P., "A Batteryless 19
W MICS/ISM-Band Energy Harvesting Body Sensor Node
Bibliography
31
SoC for ExG Applications," Solid-State Circuits, IEEE Journal of, vol.48, no.1,
pp.199,213, Jan. 2013.
[10] "An Efficiency primer for Switch-Mode, DC-DC Converter Power Supplies,"
Application Note 4266, Maxim Integrated Products, Inc., 2008.
URL: http://www.maximintegrated.com/en/app-notes/index.mvp/id/4266
[11] Pressman, Abraham. Switching power supply design. McGraw-Hill, Inc., 1997.
[12] Razavi, Behzad. Design of analog CMOS integrated circuits. Tata McGraw-Hill
Education, 2002.
[13] Tzu-Chi Huang; Chun-Yu Hsieh; Yao-Yi Yang; Yu-Huei Lee; Yu-Chai Kang; Ke-Horng
Chen; Chen-Chih Huang; Ying-Hsi Lin; Ming-Wei Lee, "A Battery-Free 217 nW Static
Control Power Buck Converter for Wireless RF Energy Harvesting With
-Calibrated
Dynamic On/Off Time and Adaptive Phase Lead Control," Solid-State Circuits, IEEE
Journal of, vol.47, no.4, pp.852,862, April 2012.
[14] Xiaocheng Jing; Mok, P.K.T., "A Fast Fixed-Frequency Adaptive-On-Time Boost
Converter With Light Load Efficiency Enhancement and Predictable Noise
Spectrum," Solid-State Circuits, IEEE Journal of, vol.48, no.10, pp.2442,2456, Oct.
2013.
[15] URL: http://product.tdk.com/en/products/inductor/
[16] URL: http://product.tdk.com/inductor/ind/detailed_information.php?lang=en&ref=
jp&part_no=CLF7045T-1R0N
[17] URL: http://product.tdk.com/capacitor/mlcc/detailed_information.php?lang=en&ref=
jp&part_no=C0603JB0J223K030BC
32
Basic Principle Analyses and Preliminary Design
Chapter 3
Control System
3.1 Introduction to This Chapter
In a DC-DC converter system, the power switches in the power plant play very important
roles. Due to their dynamic switching (alternatively open and close), the topology of the
components (inductors or capacitors) in the power plant is periodically changed thus
making the DC-DC converter realize its functionality (step-up or step-down voltage
conversion). The working principle of an inductive DC-DC converter has been described
in Section 2.1. As mentioned before, an inductor is controlled by two power switches to
be connected to the input and output terminal. Hence the energy coming from the input
source is periodically stored in the inductor and then released to the load. In the ideal case
when all system parameters including the input voltage, the output voltage and the load
current are fixed, two pulse signals with a constant frequency and a fixed duty cycle can
be used to drive the power switches. But in reality, since the system parameters are
always be changed by some effects, a control system is required to automatically adjust
the duty cycles or the frequencies of the drive signals.
How to design a robust control system with lower power consumption has always
been the crucial issue for the research in this field. Until now, many kinds of control
methodologies have been proposed, each of which focus on solving different problems in
different applications and have corresponding advantages and disadvantages. If we make
a general classification of these methods, they can be sorted into two categories. One is
the conventional pulse width modulation (PWM) control which includes the voltagemode control (VMC) and the current-mode control (CMC). The other one is the pulse
frequency modulation (PFM) control in which the frequencies of the drive signals are
dependent on the system parameters and the propagation delays [1]. Since most PFM
control methods utilize the output ripple voltage of the converter for pulse modulation,
the PFM control is also named ripple-based control.
Later in Section 3.2, a short introduction to VMC and CMC as well as their
characteristics and limitations will be given. The PFM control technique and some
general implementation methods will be described in Section 3.3. The specific control
34
Control System
technique applied in this work will be presented in Section 3.4 along with the explanation
about some improvement techniques. The approaches which can be used to generate and
control the on-time and the off-time signals will be introduced in Section 3.5. Finally, an
advanced technique which is applied to achieve the zero-current switching (ZCS) for
improving the efficiency of the DC-DC converter will be discussed in Section 3.6. If
there is not any specific notification, all the control methods will be discussed for the
boost DC-DC converter.
3.2 PWM Control
Voltage-mode control (VMC) and current-mode control (CMC) are two kinds of
conventional PWM control methods which have been widely used for controlling DC-DC
converters. VMC was first proposed and was applied on the first IC switching controller
by Silicon General (later LinFinity, then Microsemi) in 1976 [2]. The basic operating
principle of the VMC is that the duty cycles of the drive signals to control the power
switches are proportional to the “control voltage” which is actually the difference
between the output voltage of the converter and the regulated (reference) voltage. Figure
3-1 shows a typical implementation of a VMC boost DC-DC converter. Therein, the error
amplifier (EA) is used to provide a control voltage 𝑉c to the PWM comparator (Comp).
The PWM comparator generates the drive signals to the power switches (𝑆𝑤𝐿 and 𝑆𝑤𝐻 )
via the gate drive logic circuit by comparing the control voltage (𝑉c ) with a fixed voltage
ramp (𝑉ramp) generated from an extra clock. The part in the dashed box is a Type 3 (PID)
compensation circuit for the frequency compensation. The resistor 𝑅f2 works together
with 𝑅f1 for biasing the input of the error amplifier.
L
SwH
Vout
Compensation
Cc2
Vin SwL
S1
S2
Cload
Rf1
Iload
Rc2
Gate Drive
Logic
Rf2
Vfb
Cc3
Rc1
D
Comp
Cc1
Vramp
Vc
EA
Vref
Figure 3-1: Boost DC-DC converter with a typical CCM VMC control.
The generation and control of the PWM signal can be illustrated by the waveforms
shown in Figure 3-2. If the output voltage (𝑉out) drops for some reason, the control
3.2 PWM Control
35
voltage (𝑉c ) generated by the error amplifier will be increased due to the larger difference
between the feedback voltage (𝑉fb ) and the reference voltage (𝑉ref ). The increment
of 𝑉c will lead to a larger duty cycle. Due to Equation 2.8, the ratio of the input voltage
over the output voltage is equal to (1 − 𝐷) for a boost converter working in the
continuous- conduction mode (CCM). Hence, when the input voltage is fixed, the output
voltage of the boost converter will be pulled up by the increment of the duty cycle. If the
output voltage rises, the opposite operation will occur. This mechanism ensures the output
voltage is always close to the reference voltage thus achieving a good output voltage
regulation for the boost DC-DC converter.
Vr
Vc
Vramp
S1
D3
D2
D1
Figure 3-2: PWM signal generation by the PWM comparator.
The small-signal transfer function, which is typically defined by the state-space
averaging method, is widely used to analyze the dynamic behavior, frequency response
and loop stability of a DC-DC converter [3]. A lot of studies have been done on the
mathematical analysis [4] [5] [6] [7]. In this work, the complex formula derivations and
mathematical analyses will not be studied. We just cite some conclusions from previous
studies and use them to discuss the characters of different control methods.
When doing small-signal analysis on a DC-DC converter, the entire converter
system is usually divided into some parts and the total transfer function of the entire
system is equal to the product of all the transfer functions of each part. For the CCM
VMC boost converter shown in Figure 3-1, the entire converter system can be divided
into three parts, which are consecutively the PWM signal generator, the power plant and
the compensation block. According to the waveforms shown in Figure 3-2, the transfer
function of the PWM signal generator becomes:
𝑑̂
𝑣̂𝑐
1
=𝑉
r
(3.1)
It means the small-signal transfer function of this part is independent of the frequency. So
it can be ignored during the dynamic analysis of the frequency response.
The transfer function of the power plant which is also named as duty-cycle-to-output
transfer function can be expressed as:
̂𝑜𝑢𝑡
𝑉
𝑑̂
=
2
𝑉out
𝑉in
𝑠
𝑠
)+(1−
)
𝜔z1
𝜔RHP_z
2
𝑠
𝑠
1+
+
𝜔0 ∙𝑄 𝜔2
0
(1+
(3.2)
36
Control System
in which,
𝜔z1 =
1
𝐶∙𝑅ESR_C
𝜔RHP_z =
𝜔0 =
𝑅𝑙𝑜𝑎𝑑
𝐿
(3.3)
𝑉
∙ (𝑉 in )2
out
1
𝑉
∙ in
√𝐿∙𝐶𝑙𝑜𝑎𝑑 𝑉out
𝑄 = 𝜔0 ∙ 𝐶𝑙𝑜𝑎𝑑 ∙ 𝑅ESR_C
(3.4)
(3.5)
(3.6)
The detailed mathematical derivation of these equations can be found in other
literatures such as [6] [7]. Here, we just choose the most classical expressions in which
some parasitic resistances and capacitances, such as the inductor parasitic resistance, the
inductor parasitic capacitance, power switch MOS transistor parasitic resistance, etc.,
have been ignored due to their relatively small value compared to the dominant
resistances (load resistor ) and capacitances (load capacitor) in the entire system. From
the small-signal transfer function of the power plant (Equation 3.2), we can see a
double-pole 𝜔0 (Equation 3.5), a zero 𝜔z1 caused by the ESR of the load capacitor
(Equation 3.3) and a Right-Half Plane (RHP) zero 𝜔RHP_z (Equation 3.4).
The RHP zero exists in any kinds of fixed frequency CCM boost DC-DC converter.
It is an unexpected zero, because in a mathematical explanation, the phase decreases with
increasing gain at this point, which makes it is very difficult to compensate the entire
control loop with adequate phase margin [8]. The effect of the RHP zero can also be
intuitively explained as below. If the output of the converter suddenly drops down which
means more energy is required to charge the load, the duty cycle will be increased thus
providing a longer on-time for the inductor to store more energy. But for a boost
converter, the energy is delivered to the load during the off-time. Although more energy
has been stored in the inductor during the on-time, there is now a smaller off-time
available for the inductor to deliver stored energy to the output. Therefore, the output of
the converter may even drop further. It is difficult to cancel the RHP zero in a boost
converter system. The only way to eliminate its effect is to move the RHP zero far away
from the switching frequency [2]. According to Equation 3.4, in a specific application, in
which 𝑉in , 𝑉out and 𝑅load are fixed, the only way to increase the value of the RHP zero
is to reduce the inductor. But in most cases, a smaller inductor means higher switching
frequency. So the effect of the RHP zero gives much trouble to a design of a fixed
frequency boost converter.
The last part of the entire converter system is the compensation block. This part is
used to compensate the entire control loop for loop stability. The general criterion for
stabilizing the loop of any DC-DC converter is to set the crossover frequency (Gain = 0)
at about 1/10 to 1/5 of the switching frequency and to ensure a straight line (on a “log
Gain” versus “log Frequency” plot) in “-20db” slope at the crossover frequency with
enough phase margin. For this purpose, a Type 3 (PID) compensation circuit is applied
3.2 PWM Control
37
and its Bode diagram (magnitude only) is shown in Figure 3-3. This compensation circuit
can provide a low frequency zero to compensate the double-pole existing in the power
plant. Figure 3-3 also exhibits the bode-diagram of the entire converter system. It can be
seen that, the loop stability of this kind of DC-DC converter can be guaranteed by a
correct setting of the parameters of the power plant and the compensation block.
Double-pole
vout/d
-40db
ESR pole
Power stage
RHP zero
-20db
0db
f
vc/vin
Type 3
Compensation
f
vout/vin
-20db
Entire
converter
-20db
f
-40db
-20db
Figure 3-3: Compensation for the loop stability of a VMC boost DC-DC converter.
In a VMC DC-DC converter system, the ramp signal used for the PWM comparator
is generated by an extra block which will consumes additional energy. Then, an idea came,
that is, whether an intrinsic signal in the DC-DC converter could be used to replace the
ramp signal. Accordingly, CMC technique was proposed around 1980 and subsequently
widely used [2]. A typical implementation of a CMC boost DC-DC converter is shown in
Figure 3-4. The basic working principle of CMC is quite similar to VMC except that the
ramp signal used for the PWM comparator is generated by a current sensor which senses
the current of the inductor or the power switches. It is just because of this inner current
loop that the transfer function of the PWM generation part is dependent on frequency and,
as a result, the transfer function of the power plant together with the PWM generation has
only a single-pole at the resonant frequency of the load resister and the load capacitor. A
detailed expression for the duty-cycle-to-output transfer function is:
̂𝑜𝑢𝑡
𝑉
̂𝑐
𝑉
=
𝑅load (1−𝐷)
2×𝑅 ramp
𝑠
𝑠
)+(1−
)
𝜔z1
𝜔RHP_z
𝑠
1+
𝜔0
(1+
,
(3.7)
in which,
𝜔z1 =
1
𝐶∙𝑅ESR_C
(3.8)
38
Control System
𝜔RHP_z =
𝑅𝑙𝑜𝑎𝑑
𝐿
𝜔0 = 𝑅
2
𝑉
∙ (𝑉 in )2
(3.9)
out
(3.10)
𝑙𝑜𝑎𝑑 ∙𝐶𝑙𝑜𝑎𝑑
From the equations, we can see the RHP zero also exits in this kind of boost
converter. So CMC technique does not give any contribution to eliminate the effect of the
RHP zero. But because the double-pole in VMC has been replaced by a single-pole in
CMC, the compensation block will become simpler. The Type 2 compensation is enough
for a CMC DC-DC converter. The Bode diagram (magnitude only) of the entire converter
system is shown in Figure 3-5.
IL
SwH
Vout
L
Rf1
Vin
H
SwL
Vsen
Vslope
Cload
Iload
Gate Drive
Logic
Rf2
Cc2
Vramp
D
Comp
Rc
Cc1
Vc
EA
Vref
Figure 3-4: Boost DC-DC converter with a typical CCM CMC control.
Single-pole
vout/vc
ESR zero RHP zero
-20db
Power stage &
PWM generation
20db
f
vc/vin
Type 2
Compensation
vout/vin
Entire
converter
f
-20db
-20db
f
Figure 3-5: Compensation for the loop stability of a CMC boost DC-DC converter.
3.2 PWM Control
39
Besides the RHP zero effect, the CCM CMC DC-DC converter also suffers from
Subharmonic Oscillation when the duty cycle exceeds 50%. As shown in Figure 3-6,
when the duty cycle is greater than 50% (𝐷 > 50%), if the inductor current is suddenly
increased by ∆𝑖L0 due to an unexpected disturbance, this current increment will be
magnified after a cycle (grows to ∆𝑖L1 and ∆𝑖L2 ) thus causing large variation of the duty
cycle. In Figure 3-6, 𝐷0 is the duty cycle of a stable DC-DC converter and 𝐷1 is the
duty cycle of a DC-DC converter in Subharmonic Oscillation. A traditional method to
solve this problem is named “slope compensation”, that is adding a fixed slope current
onto the sensed ramp current. The circuit implementation of this method has been shown
in Figure 3-4 and its theory can be illustrated by Figure 3-7. It should be noted that, the
theory illustrated in Figure 3-7 is in current domain but in the implementation circuit
shown in Figure 3-4, all current signals are transformed to voltage signals by resistors and
then used for the comparison. As shown in Figure 3-7, it can be seen that, any disturbance
of the inductor current (∆𝑖L0 ) will be damped (drops to ∆𝑖L1 and ∆𝑖L2 ) and the inductor
current will finally return to the steady-state condition after several cycles.
Ic = Vc/Rramp
IL
∆iL0
∆iL1
∆iL2
T
D>50%
D0
T
D1
T
Figure 3-6: Subharmonic oscillation when duty cycle exceeds 50%.
Ic
Islp
IL
∆iL0
D0
∆iL1
∆iL2
T
D>50%
T
D1
T
Figure 3-7: Slope compensation to eliminate the subharmonic oscillation.
40
Control System
Although the current-mode control technique can simplify the compensation and
make it easier to stabilize the DC-DC converter, there are still some drawbacks of this
method. For example, the power consumption cannot be effectively reduced due to the
slope compensation current generation block. Moreover, the RHP zero problem also exits
in this control technique the same as in the VMC control technique. An effective method
to eliminate the RHP zero effect is making the fixed frequency PWM DC-DC converter
work in the discontinuous-conduction mode (DCM) (for both VMC and CMC). This
conclusion has been demonstrated by many other studies such as [5] [8]. As mentioned in
[8], when a DC-DC converter works in DCM, due to a relatively smaller inductor, the
RHP zero will be extended to a high frequency which is beyond the switching frequency.
Therefore, the RHP zero effect can be neglected in a DCM boost DC-DC converter.
In a DCM DC-DC converter system, the main difference from a CCM DC-DC
converter is that one more signal is required to terminate the off-time and start the
dead-time. In a CCM converter, the external clock signal is used to synchronously
terminate the off-time in the last cycle and start the on-time in the next cycle. The
termination of the on-time will be determined by the PWM comparator and meanwhile
the off-time will be started. Hence, a CCM converter only needs two signals (the clock
signal and the output signal of the PWM comparator) to control the two power switches.
But in a DCM converter, the termination of the off-time is no longer determined by the
external clock signal. The high-side power switch should be turned off when the inductor
current falls down to zero. Therefore, the DCM DC-DC converter needs three signals, in
addition to the clock signal and the output signal of the PWM comparator, an extra block
is required to sense the inductor current and generate a control signal to terminate the
off-time when the sensed inductor current reaches zero. An implementation of the DCM
VMC boost DC-DC converter with zero inductor current sensing is proposed in [9]. The
schematic of the circuit system is exhibited in Figure 3-8. We can see that except an
additional current sensor for the off-time control, all the other blocks are the same as the
CCM VMC boost converter system.
Vp
Psw
L
Vout
Nsw
Vsen1
Vn
Cload
Vsen2
Iload
Comp
Vin
Rf1
Rf2
Current Sensor
Vp
Buf
Cc
Vn
D
Buf
Off-time Control
Vramp
Comp
Vc
EA
Vref
Figure 3-8: DCM VMC boost DC-DC converter system [9].
3.2 PWM Control
41
Comparing Figure 3-8 with Figure 3-1, we can find another difference between a
DCM VCM boost converter and a CCM VCM boost converter that is the compensation
circuit. Since the transfer function of a boost converter working in DCM (no matter in
VMC or CMC) has only a single-pole [10], Type 1 or Type 2 compensation is enough for
the loop stability. As shown in Figure 3-8, Type 1 compensation is applied in the control
loop.
Making the fixed frequency PWM boost DC-DC converter working in DCM can
effectively cancel the effects of the RHP zero and the double-pole thus enhancing the
loop stability. But this method also has its weakness. If the load current varies over a
large range, the power conversion efficiency of the DC-DC converter will change a lot.
The efficiency of the converter working in a light load condition can be much worse than
that in a high load condition. This can be qualitatively explained as follows. Since the
working frequency of the DC-DC converter is always the same, the switching losses are
almost in the same value for both high and light load conditions. But in the light load
condition, because the power delivered to the load in each cycle is smaller, the switching
losses will take a larger proportion of the total power thus reducing the total power
conversion efficiency. In order to optimize the power conversion efficiency of the DC-DC
converter in both high and light load condition, another kind of control method has been
widely used for the low-power and high-efficiency applications. Because the working
frequency is changed according to different load currents, this method is named pulse
frequency modulation (PFM) control. Detailed discussion on this control method will be
given in the next Section.
3.3 PFM Control
As mentioned in the last Section, for the PWM control method, the regulation of the
output voltage of the converter under different load current conditions is achieved by
adjusting the duty cycle or the on-time of the drive signal with a fixed frequency.
However, in terms of the PFM control method, the regulation of the output under
different load current conditions is achieved by changing the frequency. In the light load
condition, since the frequency of the PFM control is much lower than that in the high
load condition, the switching losses will be reduced thus significantly improving the
power conversion efficiency. Because the output ripple voltage of a DC-DC converter is
dependent on the load current, the PFM control generally utilizes this voltage for pulse
modulation. As a result, the PFM control method is also named the ripple-based control
[1]. There are two basic PFM ripple-based control techniques which have widely been
used in recent years. One of them is the hysteretic control and the other is the constant
on-time/off-time (COOT) control. Although [1] mentioned these methods are more
suitable for the buck converter, after some modification, they can actually be used for the
boost converter as well.
42
Control System
Sw
L
Vout
Rf1
Vin
Cload
Iload
Rf2
Hysteretic
Comparator
S1
Vfb
Vref
Figure 3-9: Buck DC-DC converter with hysteretic control [1].
Figure 3-9 shows a buck converter with hysteretic control [1]. In here, the hysteretic
comparator is the core of the entire control system. This comparator is used to not only
regulate the output voltage but also generate the pulse signal. The asynchronous structure
is used for design simplification which means only one drive signal is required for the
main power switch. The basic operation of the buck converter is illustrated in Figure 3-10.
When the switch 𝑆𝑤 is on, the buck converter works in the on-time phase. The energy
coming from the input terminal is being stored in the inductor and used to charge the load.
Both the inductor current and the output voltage increase. When the output voltage rises
up to the upper boundary of the hysteretic band (𝑉ref + 0.5𝑉H ), the hysteretic comparator
will send a signal to open Switch 𝑆𝑤. Then, the buck converter works in the off-time
phase and the dead time phase. The inductor current will fall down to zero (in the off-time)
and stay zero (in the dead-time). The output voltage will continuously fall down to the
lower boundary of the hysteretic band (𝑉ref − 0.5𝑉H ), at this moment, the switch 𝑆𝑤 will
be turned on and a new cycle will start again.
ton
toff
tdead
ton
Vref + 0.5VH
Vfb
Vref
Vref - 0.5VH
S1
IL
Figure 3-10: Timing diagram of the buck converter with hysteretic control.
Figure 3-11 exhibits a buck converter with constant-on-time/off-time control [1]. In
here, the general comparator is used to monitor the output voltage and send the timer an
3.3 PFM Control
43
active signal to start the on-time (constant on-time) or the off-time (constant off-time).
The duration of the on-time (constant on-time) or the off-time (constant off-time) is set as
a constant value by the timer. The detailed operation can be understood by the aid of the
timing diagram which is shown in Figure 3-12. In terms of the constant on-time control,
the comparator sends an active signal to start the on-time when the output voltage falls
down to the reference voltage (Figure 3-12 (a)). In terms of the constant off-time control,
the comparator sends an active signal to start the off-time when the output voltage rises
up to the reference voltage (Figure 3-12 (b)).
L
Sw
Vout
Vin
Rf1
Iload
Cload
Rf2
S1
Vfb
Q
Q
On-timer
Comp
Constant
On-time
Vref
Vfb
Q
Q
Off-timer
Comp
Vref
Constant
Off-time
Figure 3-11: Buck DC-DC converter with COOT control [1].
ton
toff
tdead
ton
ton
toff
tdead
ton
Vref
Vfb
Vfb
Vref
S1
S1
Constant
Constant
Constant
IL
IL
(a)
(b)
Figure 3-12: Timing diagram of the buck converter with
(a) constant on-time (b) constant off-time control.
For the buck converter, the output voltage rises up during the on-time and falls down
during the off-time and the dead-time. But for the boost converter, the output voltage rises
44
Control System
up during the off-time and falls down during the on-time and the dead-time. Because of a
similar behavior of the output voltage during the on-time and the dead-time, the general
PFM control methods such as those mentioned before cannot be applied for the boost
converter. That is the reason why [1] mentioned ripple-based control is more suitable for
buck converters. However, after making some improvement, the hysteretic control and
the COOT control can also be used for the design of a boost DC-DC converter. For
example, [11] provided an implementation method of the boost DC-DC converter with
hysteretic control, and [12] designed a boost DC-DC converter with constant on-time
control. In this thesis, the detailed explanation of these methods will not be given. The
control method finally applied in this work belongs to an enhanced method of the COOT
control. Its operating principle will be discussed in detail in the next section.
Because the PFM control system does neither require an error amplifier nor a clock
signal generation, it can further improve the power conversion efficiency of the DC-DC
converter, besides reducing the switching losses in the light load current condition. Due to
its good performance in terms of power conversion efficiency and loop stability, the PFM
(ripple-based) control technique is extremely attractive for low-power high-efficiency
required applications such as portable or energy harvesting electronic devices. However,
this method also suffers from some practical limitations or problems. Detailed discussions
about these issues have been given in [1]. In summary, there are three dominant
drawbacks of the ripple-based PFM technique, which are respectively (1) poorly defined
switching frequency, (2) sensitivity to external noises, (3) inadequate DC regulation. The
poorly defined switching frequency means the working frequency has a strong
dependency on the system parameters (input and output voltage, load current) and some
other non-ideal effects (parasitic effects and propagation delays). The sensitivity to
external disturbances means that if there is some noise at the feedback node (𝑉fb), the
noise may be sensed by the comparator and injected into the control loop thus interfering
with the functionality. The inadequate DC regulation means the output voltage cannot be
too close to the reference voltage due to some propagation delays or parasitic effects.
Relevant improvement methods which can be used to eliminate the problem have also
been proposed in [1]. In this thesis, we will not describe all of them in detail. We will just
introduce the methods which have been applied in this work in the next section.
3.4 Control Technique Applied in This Work
Almost all kinds of general methods which can be used to control the DC-DC converter
have been discussed in the previous sections. As mentioned before, each method has its
own merits and limitations. Consequently, it has widely been acknowledged that no one
method is optimal for all applications. It should be determined by the design requirements
or specifications which control method is the best choice for controlling the DC-DC
converter. In this design, because the boost DC-DC converter is used to transfer the
3.4 Control Technique Applied in This Work
45
energy coming from the energy harvesting front-end to charge the load battery, the power
conversion efficiency is the most important specification. Besides, since the input DC
voltage of the boost DC-DC converter comes from a rectifier which rectifies an AC signal
into a DC signal, the value of the rectified DC voltage is not stable. Hence, the loop
stability is also a very important specification for this design. As for the frequency
variation and the inadequate output DC regulation, there are not any specific requirements
on them in this work.
Based on the analysis of the design specifications and the characteristics of different
control techniques, the COOT control is finally applied in this work. As a kind of PFM
ripple-based control technique, COOT control can provide not only perfect power
conversion efficiency but also sufficient loop stability, which is undoubtedly the most
suitable choice for this design. But as mentioned before, the basic COOT control circuit
shown in Figure 3-12 cannot be directly used for a boost converter. Some improvements
and adjustments should be made in order to achieve a boost DC-DC converter with
COOT control. Figure 3-13 shows a simplified circuit model of the boost DC-DC
converter with an enhanced COOT control technique which is used in this design. Its
operation will be explained later by the aim of the timing diagram shown in Figure 3-14.
L
Vin
Vmid
Vout
Psw
Cload Iload
Vp
Nsw
Vn
Rf1
Comp
Vfb
ton
Ton
Generator
toff
Toff
Generator
Von
Voff
Rf2
Vcomp
Digital
Logic
Vref
Figure 3-13: Boost DC-DC converter with an enhanced COOT control.
From Figure 3-14, we can see that the rising edge of the comparator output signal
(𝑉comp ) is used to activate a new cycle. During the dead-time in last cycle, since both the
NMOS power switch (𝑁sw ) and the PMOS power switch (𝑃sw) are open, the output
voltage of the boost converter (𝑉out) falls down due to the load current. When the
feedback voltage 𝑉fb drops down to the reference voltage (𝑉ref ), the rising of 𝑉comp will
start a new cycle. In a cycle, the on-time and the off-time is set to be constant values by
two time generators. These two time generators utilize a specific mechanism to generate
the proper on-time and off-time. (The proper on-time and off-time means the energy
charged in the inductor during the on-time is equal to the energy discharged from the
inductor to the load capacitor during the off-time.) After the on-time and off-time, the
46
Control System
boost converter works in the dead-time. The duration of the dead-time will be determined
by when the feedback voltage falls down to the reference voltage.
Vref
Vfb
Vcomp
Vn
ton
ton
toff
Vp
toff
tdead
tdead
IL
Figure 3-14: Timing diagram of the boost converter with an enhanced COOT control.
By using this enhanced method, COOT control has been achieved on a boost
DC-DC converter design. But the general limitations of the PFM ripple-based control
techniques which have been mentioned in previous section ((1) poorly defined switching
frequency, (2) sensitivity to external noise, (3) inadequate DC regulation) also occur in
this control system. Some improvements should be made to eliminate their effects. At
first, since it is exactly our target to change the switching frequency under different load
current conditions for high power conversion efficiency, there is no specific requirement
on a fixed switching frequency. Hence, the first limitation will not be considered in this
design. Moreover, as it is not necessary to charge the load battery with an accurate
1𝑉 voltage in this work, a little deviation (tens 𝑚𝑉) between the output voltage and the
reference voltage will not affect the charging action. Therefore, the third problem will
also be ignored in this design. The only problem required to be considered in this work is
the second one which is that the control system is sensitive to external noise.
Vref
Noise
Vfb
Vcomp
Vn
ton
IL
Figure 3-15: Control system is sensitivity to the noise at the node Vfb .
3.4 Control Technique Applied in This Work
47
This problem is illustrated in Figure 3-15. We can see, if there is a spike (red curve)
occurring at the feedback node 𝑉fb, this spike will be sensed by the comparator and
imported into the control system thus breaking the right functionality. Some effective
solutions to eliminate this problem have been discussed in [1]. In this work, we choose a
simple method proposed in [1] which is to add a small capacitor (𝐶f ) across the upper
resistor (𝑅f1 ) of the feedback divider. The small parallel capacitor works as a high-pass to
improve noise immunity by increasing the PWM ramp. If the capacitor is chosen to
satisfy the inequality
𝑅 ∙𝑅
𝐶f 𝑅 f1+𝑅f2 ≫ 𝑇 ,
f1
(3.11)
f2
in which 𝑇 is the switching period, then the ripple of the output voltage will reach the
input of the comparator without further attenuation. But we should also pay attention to
another issue which is the value of this high-pass filter capacitor should not be too much,
because the step response of the boost converter with a large 𝐶f will be very slow. Based
on the simulation results, the value of this filter capacitor is finally set to be 200𝑓𝐶.
Figure 3-16 shows the boost DC-DC converter system with this improvement. However,
during the research, we found that the performance of this improvement method is not
very good. In future works, more effective methods should be studied and proposed.
L
Vin
Vmid
Vout
Psw
Cload Iload
Vp
Nsw
Cf
Vn
Rf1
Comp
Vfb
ton
Ton
Generator
toff
Toff
Generator
Von
Voff
Rf2
Vcomp
Digital
Logic
Vref
Figure 3-16: Boost DC-DC converter system with the filter cap
Until now, COOT control with relevant improvement techniques to eliminate its
limitations has been described. But in order to achieve the proper setting of the on-time
and off-time as mentioned before, an adaptive on-time/off-time (AOOT) control is
applied to replace the general COOT control in this work. AOOT control is almost the
same as the COOT except that the on-time and off-time are no more a constant value. In
AOOT control, the values of the on-time and the off-time will be dependent on one or
more system parameters (input voltage, output voltage, load current, etc.). In this work,
we set the on-time and the off-time related to the input voltage and the output voltage. Let
us review the equations in Section 2.1. Equations 2.3 and 2.5 express the charging and
48
Control System
discharging of the inductor current. According to these two equations, we can obtain that:
𝑉in ∙𝑡on
𝐿
(3.12)
(𝑉out −𝑉in )∙𝑡off
𝐿
(3.13)
𝑖rise =
𝑖fall =
For high efficiency, we expect that 𝑖rise is equal to 𝑖fall , which means the current charged
in the inductor is fully delivered to the load battery without any waste. But in COOT
control, if there is a variation on the input voltage, because the output voltage is always
fixed close to the reference voltage, the current balance will be broken. In AOOT control,
if we set the on-time proportional to (𝑉out − 𝑉in) and the off-time proportional to 𝑉in , no
matter what value the input voltage or output voltage is, the current balance will always
be satisfied. The conclusion can be demonstrated by following equations. If we set:
𝑡on = 𝑘1 ∙ (𝑉out − 𝑉in )
(3.14)
𝑡off = 𝑘2 ∙ 𝑉in
(3.15)
And we make 𝑘1 = 𝑘2, there will always be:
𝑖rise =
𝑉in ∙𝑡on
𝐿
= 𝑖fall =
(𝑉out −𝑉in )∙𝑡off
𝐿
(3.16)
Hence, by using AOOT control, the on-time and the off-time can be automatically
adjusted according to different values of the input voltage and the output voltage thus
always guaranteeing that the charging current of the inductor during the on-time is equal
to the discharging current of the inductor during the off-time. Now the only problem is
how to generate the on-time and the off-time which satisfy Equations 3.14 and 3.15. The
mechanism of the time signal generation will be introduced in the next section.
3.5 Time Signal Generation
In a boost DC-DC converter with AOOT control, the generation and control of the
on-time and the off-time is a crucial task. Actually, the on-time is the high-level pulse
width of the drive signal 𝑉n to the NMOS power switch, and the off-time is the low- level
pulse width of the drive signal 𝑉p to the PMOS power switch. Usually, these two time
signals are generated and controlled by time generators.
There have been many implementation methods for time generators which have been
proposed in previous works. Recently, two kinds of approaches have been widely applied
in other studies. The first one is using an oscillator to generate a square-wave pulse signal
for one power switch, and using a controlled delay line with a simple digital circuit to
generate the signal for the other power switch [13], [14], [15], [16], [17]. One instance of
the first approach is shown in Figure 3-17 [14]. A tunable ring oscillator with some
frequency dividers can generate a pulse signal 𝑉1 with 50% duty cycle for the on-time, of
3.5 Time Signal Generation
49
which the pulse width (𝑡on ) can be controlled by the bias current. A digital controlled
delay line and an AND gate are used for the off-time generation. According to the timing
diagram of the main signals shown in Figure 3-18, the off-time (𝑡off ) is equal to the delay
time (𝑡delay) which can be tuned by a digital control code.
Tunable Ring Oscillator
D
●●●●●●
D
Q
CLK
Q
Q
Enalbe
V1
●●●●●●
CLK
Q
Bias
Frequency Divider
V1
V1
V0000
V1111
●●●●●●
V2
V1d
Controlled Delay Line
4-bit MUX
Digital Control
Figure 3-17: One approach to implement the time generators. [14]
V1
ton
V1
V1d
tdelay
toff
V2
Figure 3-18: Timing diagram of main signals in the time generator. [14]
The other approach which has been widely employed to generate pulse signals in a
DC-DC converter is charging a capacitor by a current source and comparing the voltage
with a reference [18], [19], [20], [21], [22], [23]. Based on the charging and discharging
equation of a capacitor (Equations 3.17 and 3.18) any desired time can be obtained by a
proper setting of the values of C, V and I.
𝑑𝑉
𝐼 = 𝐶 ∙ 𝑑𝑡
𝑉
𝑡=𝐶∙𝑡
(3.17)
(3.18)
The working principle can be viewed clearly through an example [21], in which, a
50
Control System
pulse generator with a DAC pulse width modulator and a sleep mode control was
proposed. Its schematic is shown in Figure 3-19. The MOSFET 𝑃s works as a current
mirror to generate a reference current for charging the capacitor array. The capacitance of
the capacitor array in shunt structure is digitally controlled by the switch D4-D0 and their
compliments. An analog comparator compares the voltage of the node 𝑉charge with the
reference voltage 𝑉ref , and then outputs a pulse signal with the desired pulse width. The
timing diagram of the main signals is shown in Figure 3-20.
VDD
Ppull-up
Ps
Bias
VRef
IRef
Vcomp+
Vcharge
VcompD4
D3
D2
D1
D0
Sleep
reset
D4
D3
16C
D2
8C
D0
D1
4C
2C
C
VSS
Figure 3-19: I-C time generator with DAC and sleep mode control [21].
reset
Vcharge
VRef
Sleep
VcompFigure 3-20: Timing diagram of main signals in the time generator [21].
Comparing these two methods, the second one is less power-efficient due to the
constant DC current in the comparator, but it is more area-efficient and easy implemented
as the circuits only include a ramp generator and an analog comparator [21]. In addition,
in order to achieve AOOT control, the time signals should satisfy Equation 3.14 and 3.15.
The second method can easily achieve this function by setting the charging current or the
comparison voltage related to the input voltage and output voltage. Based on these
benefits, the second method is used for the design of the time generators in this work.
Figure 3-21 shows the on-time generator and its working principle. A constant
current 𝐼on is used to discharge the capacitor 𝐶on from the initial voltage 𝑉out to the
reference voltage 𝑉in , the generation time 𝑡on satisfies the equation:
3.5 Time Signal Generation
51
𝑡on =
𝐶on
𝐼on
∙ (𝑉out − 𝑉in )
(3.19)
Figure 3-22 shows the off-time generator and its working principle. A constant
current 𝐼off is used to charge the capacitor 𝐶off from the initial zero to the reference
voltage 𝑉in , the generation time 𝑡off satisfies the equation:
𝑡off =
𝐶off
𝐼off
∙ 𝑉in
(3.20)
If we make 𝑘1 in Equation 3.14 is equal to (𝐶on /𝐼on), and 𝑘2 in Equation 3.15 equal to
(𝐶off / 𝐼off ), Equations 3.19 and 3.20 are exactly the same as Equation 3.14 and 3.15. Then,
the timing balance of the on-time and the off-time mentioned in Section 3.4 can be
achieved by just making 𝐶on /𝐼on= 𝐶off / 𝐼off .
Vout
Comparator
Vcon
Ion
Vin
Vcon
Von
Vin
Con
Vout
Von
(a)
ton
(b)
Figure 3-21: On-time generator and its working principle.
Vout
Ioff
Vin
Vcoff
Comparator
Vcoff
Coff
Vin
Voff
(a)
Voff
toff
(b)
Figure 3-22: Off-time generator and its working principle.
3.6 Zero Current Switching Adjustment
According to the analysis in Section 3.4, the adaptive on-time control can theoretically
ensure the current stored in the inductor during the on-time equals the current released
from the inductor during the off-time. However, many non-ideal effects are not taken into
account during the formula derivation. For example, the voltage across the inductor
during the on-time should actually be (𝑉in − 𝑉ds_nsw ) rather than 𝑉𝑖𝑛 (𝑉ds_nsw is the
52
Control System
drain-source voltage of the NMOS power switch transistor), hence a precise expression of
the inductor charging equation should be:
𝑖rise = (𝑉in − 𝑉ds_nsw ) ∙
𝑡on
𝐿
(3.15)
The same non-ideal effect also occurs during the off-time, a more precise expression
of the inductor discharging equation would be:
𝑖fall = (𝑉in − 𝑉out − 𝑉ds_psw ) ∙
𝑡off
𝐿
(3.16)
The non-ideal effects in the time generator will also break the timing balance
between the on-time and the off-time. In terms of the time generators applied in this work,
non-ideal effects include capacitor mismatch (∆𝐶mis ), current mismatch (∆𝑖mis) and the
inaccuracy of the comparator (𝑉err). A more precise expression of the time generating
equation would be:
𝑡 = (𝐶 ± ∆𝐶mis ) ∙
(𝑉ref ±𝑉err )
(𝑖c ±∆𝑖mis )
(3.17)
Due to these non-ideal effects, an extra block is required to slightly adjust the
off-time thus guaranteeing the timing balance. As mentioned in Section 2.1, the boost
converter operates in DCM, which means the DC current flowing through the inductor is
zero. Hence, the inductor current should rise from zero at the beginning of the on-time
and fall down to zero at the end of the off-time. This mechanism is named zero current
switching (ZCS).
To achieve ZCS adjustment, an energy efficient method which is nearly free of static
current dissipation has been proposed and widely used in recent studies [13] [16] [20]
[24]. According to the condition of the drain voltage (𝑉mid) of the high-side power switch
(PMOS) at the end of the off-time phase, whether the off-time is overly short or overly
long can be judged.
ton
toff
ton
tdead
iL
iL
0A
0A
S1
S1
S2
S2
Vmid
Vmid
0V
0V
toff
tdead
(a)
(b)
Figure 3-23: Boost converter with overly short off-time (a) and overly long off-time (b)
3.6 Zero Current Switching Adjustment
53
The operating principle can be explained by means of Figure 3-23. In the off-time
period, because the high-side power switch is closed, its drain voltage (𝑉mid) is nearly
equal to its source voltage which is exactly the output voltage (𝑉out ) of the boost
converter. At the end of the off-time period, if the off-time is overly short which means
the inductor current has not fallen down to zero (Figure 3-23 (a)), 𝑉mid will have a
positive voltage jump. The reason for the positive jump is the remaining positive inductor
current will continue flowing through the high-side PMOS power switch which has a
large crossover resistance when it is switched off. The positive direction of the current is
defined as flowing from the input to the output of the boost converter. On the other hand,
at the end of the off-time period, if the off-time is overly long which means the inductor
current has fallen to a negative value (Figure 3-23 (b)), 𝑉mid will have a negative voltage
jump. The reason for the negative jump is that, at this moment, there is a negative current
flowing through the high-side PMOS power switch which has a large crossover resistance.
Therefore, by detecting the high or low state of 𝑉mid at the end of the off-time, we can
obtain whether the off-time should be increased or decreased for ZCS.
Clock
Vmid
1-bit
ADC
Up/Down
Up/Down
Counter
Digital Code
tad
DTC
Figure 3-24: Mechanism of the ZCS adjustment.
The ZCS adjustment can be achieved by the control system shown in Figure 3-24. A
1-bit analog-to-digital converter (ADC) is used to detect the high/low state of the node
𝑉mid and provide the information to the control system about whether the off-time
should be increased or decreased in next cycle. According to the ADC’s information, an
up/down counter adjusts the digital code which carries the information about how much
the off-time should be corrected for ZCS. A digital-to-time converter (DTC) is applied to
receive the digital code, and based on the digital code, to generate an additional time to
correct the off-time for ZCS. This ZCS adjustment system detects the off-time condition
(overly short or long) in a period, and makes correction on the off-time in the next period.
In steady state, the digital code should be 1-bit up and down around a definite value.
In this work, regardless of the effects of the non-ideal factors, the off-time should be
100ns if the on-time is 150ns. Since the non-ideal effects do not change the timing
balance drastically, a ±15% adjustment of the off-time is sufficient to overcome these
non-ideal effects, which means the off-time is tuned in a range of 85ns~115ns. Under the
consideration of the design simplification and allowable tuning accuracy, the resolution of
the ZCS adjustment in time is determined as 1ns per bit. According to the inductor
54
Control System
discharging equation, we can obtain that 1ns off-time variation can cause the inductor
current to change a value of:
𝑖L_v = 0.6𝑉 ∙
1𝑛𝑠
1𝑢𝐻
= 600𝜇𝐴
(3.18)
It means the resolution of the ZCS adjustment in current is about 600μA, which is
accurate enough for this work. Therefore, a 5-bit binary code is applied in the ZCS
adjustment system.
Finally, Figure 3-25 shows the model of the entire boost DC-DC converter system
with AOOT control and ZCS adjustment that has been designed in this work.
L
Vmid
Vout
Psw
Cload Iload
ZCS Adjustment
Vp
Vin
Cf
Nsw
Vn
Rf1
Comp
Vfb
ton
Ton
Generator
tad
toff
Toff
Generator
Von
Voff
Rf2
Vcomp
Digital
Logic
Vref
Figure 3-25: Entire boost DC-DC converter with AOOT control and ZCS adjustment.
Bibliography
55
Bibliography
[1] Redl, R.; Jian Sun, "Ripple-Based Control of Switching Regulators ̶ An
Overview," Power Electronics, IEEE Transactions on, vol.24, no.12, pp.2669,2680,
Dec. 2009.
[2] Sanjaya Maniktala, "Voltage-Mode, Current-Mode (and Hysteretic Control),"
Technical Note TN-203, Microsemi, Inc., 2012.
[3] Wens, Mike, and Michiel Steyaert. Design and implementation of fully-integrated
inductive DC-DC converters in standard CMOS, Springer, 2011.
[4] Demetriades, Georgios D, "On small-signal analysis and control of the single-and the
dual-active bridge topologies," Doctoral Dissertation, Royal Institute of Technology,
Swede, 2005.
[5] Fronczak, Kevin, "Stability Analysis of Switched DC-DC Boost Converters for
Integrated Circuits," MSc. Thesis, Rochester Institute of Technology, U.S.A, 2013.
[6] KEONG, NG POH, "Small Signal Modeling of DC-DC Power Converters Based on
Separation of Variables," MSc. Thesis, University of Kentucky, U.S.A, 2004.
[7] Zaitsu, Rick. "Voltage Mode Boost Converter Small Signal Control Loop Analysis
Using the TPS61030," Application Report SLVA274A, Texas Instruments, 2009.
[8] Lynch, Brian T., "Under the Hood of a DC/DC Boost Converter," TI Power Supply
Design Seminar, Dallas, TX. Vol. 2009. 2008.
[9] Wens, M.; Cornelissens, K.; Steyaert, M., "A fully-integrated 0.18µm CMOS DC-DC
step-up converter, using a bondwire spiral inductor," Solid State Circuits Conference,
2007. ESSCIRC 2007. 33rd European, vol., no., pp.268,271, 11-13 Sept. 2007.
[10] Rogers, Everett. "Understanding Boost Power Stages in Switchmode Power
Supplies." Application Report SLVA061, Texas Instruments Incorporated, 1999.
[11] Thekkevalappil, Soniya Noormuhamed. "Hysteretic Pulse Width Modulation with
Internally Generated Carrier for a Boost Dc-dc Converter," MSc. Thesis, University of
Florida, U.S.A, 2005.
56
Control System
[12] Xiaoru Xu; Xiaobo Wu; Xiaolang Yan, "A quasi fixed frequency constant on time
controlled boost converter," Circuits and Systems, 2008. ISCAS 2008. IEEE
International Symposium on, vol., no., pp.2206,2209, 18-21 May 2008.
[13] Weng, P.-S.; Tang, H.-Y.; Ku, P.-C.; Lu, L.-H., "50 mV-Input Batteryless Boost
Converter for Thermal Energy Harvesting," Solid-State Circuits, IEEE Journal of ,
vol.48, no.4, pp.1031,1041, April 2013.
[14] Po-Hsiang Lan; Po-Chiun Huang, "A High Efficiency FLL-Assisted Current-Controlled
DC-DC Converter Over Light-Loaded Range," Circuits and Systems I: Regular
Papers, IEEE Transactions on , vol.59, no.10, pp.2468,2476, Oct. 2012.
[15] Pengfei Li; Bhatia, D.; Lin Xue; Bashirullah, R., "A 90-240 MHz Hysteretic Controlled
DC-DC Buck Converter With Digital Phase Locked Loop Synchronization,
" Solid-State Circuits, IEEE Journal of, vol.46, no.9, pp.2108,2119, Sept. 2011.
[16] Carlson, E.J.; Strunz, K.; Otis, B.P., "A 20 mV Input Boost Converter With Efficient
Digital Control for Thermoelectric Energy Harvesting," Solid-State Circuits, IEEE
Journal of, vol.45, no.4, pp.741,750, April 2010.
[17] Ramadass, Y.K.; Chandrakasan, A.P., "An Efficient Piezoelectric Energy Harvesting
Interface Circuit Using a Bias-Flip Rectifier and Shared Inductor," Solid-State Circuits,
IEEE Journal of, vol.45, no.1, pp.189,204, Jan. 2010.
[18] Xiaocheng Jing; Mok, P.K.T., "A Fast Fixed-Frequency Adaptive-On-Time Boost
Converter With Light Load Efficiency Enhancement and Predictable Noise
Spectrum," Solid-State Circuits, IEEE Journal of , vol.48, no.10, pp.2442,2456, Oct.
2013.
[19] Bhatia, D.; Lin Xue; Pengfei Li; Qiuzhong Wu; Bashirullah, R., "High-Voltage Tolerant
Digitally Aided DCM/PWM Multiphase DC-DC Boost Converter With Integrated
Schottky Diodes in 0.13 µm 1.2 V Digital CMOS Process," Solid-State Circuits, IEEE
Journal of, vol.48, no.3, pp.774,789, March 2013.
[20] Tzu-Chi Huang; Chun-Yu Hsieh; Yao-Yi Yang; Yu-Huei Lee; Yu-Chai Kang; Ke-Horng
Chen; Chen-Chih Huang; Ying-Hsi Lin; Ming-Wei Lee, "A Battery-Free 217 nW Static
Control Power Buck Converter for Wireless RF Energy Harvesting With
-Calibrated
Dynamic On/Off Time and Adaptive Phase Lead Control," Solid-State Circuits, IEEE
Journal of, vol.47, no.4, pp.852,862, April 2012.
Bibliography
[21] Bandyopadhyay, S.; Ramadass, Y.K.; Chandrakasan, A.P., "20
57
A to 100 mA DC–
DC Converter With 2.8-4.2 V Battery Supply for Portable Applications in 45 nm
CMOS," Solid-State Circuits, IEEE Journal of, vol.46, no.12, pp.2807,2820, Dec.
2011.
[22] Yi-Ting Lee; Chia-Ling Wei; Chin-Hong Chen, "An integrated step-down DC-DC
converter with low output voltage ripple," Industrial Electronics and Applications
(ICIEA), 2010 the 5th IEEE Conference on, vol., no., pp.1373,1378, 15-17 June 2010.
[23] Emira, A.; Elwan, H.; Abdelaziz, S., "DC-DC converter with ON-time control in
pulse-skipping modulation," Circuits and Systems (ISCAS), Proceedings of 2010
IEEE International Symposium on, vol., no., pp.2746,2749, May 30 2010-June 2
2010.
[24] Cliquennois, S.; Donida, A.; Malcovati, P.; Baschirotto, A.; Nagari, A., "A 65-nm, 1-A
Buck Converter With Multi-Function SAR-ADC-Based CCM/PSK Digital Control
Loop," Solid-State Circuits, IEEE Journal of, vol.47, no.7, pp.1546,1556, July 2012.
58
Control System
Chapter 4
Circuit Implementation
4.1 Overview of This Chapter
The basic functionality of the boost DC-DC converter system designed in this work has
been introduced in previous chapters. In Chapter 2, the power plant of the boost converter
has been designed based on the target specifications. In Chapter 3, the most suitable
control technique has been selected after detailed analyses of all candidates. Figure 4-1
shows the system-level schematic of the entire boost DC-DC converter system designed
in this research. In this chapter, the circuit implementation of each block in transistor
level will be introduced. The Digital Logic block used to control the sequence of all
signals in the control loop is introduced in Section 4.2. The time generators applied to
control the durations of the on-time and off-time are described in Section 4.3. The circuit
implementation of the ZCS adjustment is presented in Section 4.4. In Sections 4.5 and 4.6,
the circuit design of the comparator and the reference current generator are discussed.
L=1μH
Vin=0.4V
Iload
Vp
Cf
Digital
Up/Down Code
Counter
ZCS Adjustment
Up/Down
toff=100ns
ton=150ns
Ton
Generator
tad=
±15ns
Toff
Generator
S1
Von
Voff
Digital
Logitc
Rf1
Cload=
220nF
Gate
Buffer
Comp
1-bit
ADC
ZCS Adjustment
Vmid
Vn
Nsw
Vout=1V
Psw
Vmid
S2
Rf2
Vcomp
Vref
Toff Generator
Ton Generator
DAC
IDAC
Ioff
Von
Vcon
tad
Voff
Vcon
Ion
Con
Coff
Figure 4-1: Entire boost DC-DC converter system designed in this work.
60
Circuit Implementation
4.2 Digital Logic Block
The Digital Logic block is the only digital circuit in the entire system of the boost DC-DC
converter. It plays a crucial role, namely to control the sequence of all signals in the
control system thus making the converter operate in the right functionality. Its specific
working principle in steady state will be explained by means of Figure 4-1 and the
following flow chart (Figure 4-2).
Figure 4-2: Operation flow chart of the boost DC-DC converter.
̅̅̅̅ = 0) comes and resets the Digital Logic block to the
At first, a “Reset” signal (𝑅𝑒
initial phase. In this phase, there are 𝑆1 = 0, 𝑆2 = 0 and 𝑆3 = 1. S1 is the signal that
carries the on-time information. As shown in Figure 4-1, after a gate buffer, 𝑆1 is turned
to 𝑉𝑛 . S2 is the signal that carries the off-time information. As shown in Figure 4-1, after
an inverter and a gate buffer, 𝑆2 is turned to 𝑉𝑝 . S3 is the signal that carries the dead-time
information. The reset signal also resets the Ton Generator and Toff Generator to the initial
phase where there are 𝑉con = 1 and 𝑉coff = 0. Then the “Reset” signal is turned off
(̅̅̅̅
𝑅𝑒 = 1) and the boost converter starts working in the dead-time phase. The dead-time
phase will be maintained until the output voltage of the boost converter drops below the
reference voltage (𝑉out < 𝑉ref ). When 𝑉out < 𝑉ref, S1 is activated to 1 and the boost
converter steps into the on-time phase. The duration of the on-time phase is controlled by
the Ton Generator. After a specific time, the Ton Generator will send a signal to switch S1
4.2 Digital Logic Block
61
from 1 to 0 and S2 from 0 to 1 which means to terminate the on-time phase and start the
off-time phase. The duration of the off-time phase is determined by the Toff Generator
which will send a signal to shift the boost converter from the off-time phase into the
dead-time phase. When the boost converter enters the dead-time phase, it will face an
operating model selection which will be further explained later in this section. If the
output voltage is still lower than the reference voltage (𝑉out < 𝑉ref ) after a cycle, 𝑆1 will
be immediately turned to 1, which means a new on-time phase starts. In this case, the
boost converter works in quasi-CCM. If the output voltage is higher than the reference
voltage after a cycle, the dead-time will be maintained until the voltage output drops
below the reference voltage. In this case, the boost converter works in DCM. The timing
̅̅̅ = −𝑅𝑒.
diagram of main signals in the control system is shown in Figure 4-3 where ̅𝑅𝑒
Vref
Vout
ton
toff tdead
ton
toff
tdead
ton
Reset
S3
S1
S2
Vcon
Vin
Vcoff
Vin
Von
Voff
Vra
Vcomp
Q-CCM
DCM
Figure 4-3: Timing diagram of all signals.
In order to achieve the logic function mentioned above, the Digital Logic block is
built by some digital cells such as D flip-flops and logic gates. Its detailed schematic is
shown in Figure 4-4. During the design of this block, some issues should be considered,
otherwise the performance or even the functionality of the converter will be destroyed.
62
Circuit Implementation
S2
VDD
S1
D
S2
Vra
S1
Voff
Q
CLK
S2
Q
Re
Vcomp
Reset
Reset
Voff
S1
VDD
D
Q
S3
VDD
S3
S3
D
Q
Vra
CLK
S1
Q
Re
CLK
Q
Re
Reset
Reset
VDD
D
Q
VDD
D
Voff
CLK
Q
Q
Von
Re
CLK
Q
Re
Figure 4-4: Schematic of the Digital Logic block.
The first issue also the most important one is which signal should be used to trigger
S3. S3 is the control signal for the dead-time. According to the working principle of the
control method discussed in Section 3.4, the dead-time will be maintained until the output
voltage of the boost converter drops below the reference voltage (𝑉out < 𝑉ref ). But if S3 is
directly triggered by the output signal of the comparator (𝑉comp), there will be a mistake
if the output voltage of the boost converter is still lower than the reference voltage
(𝑉out < 𝑉ref ) after the off-time. The failure mechanism is shown in Figure 4-5.
Vref
Vout
Vcomp
tdead
tdead
S3
S1
S2
ton
toff
Figure 4-5: First failure mechanism of the control system.
4.2 Digital Logic Block
63
S1
S2
Vra
Voff
Vcomp
Re
Figure 4-6: Operating model selection circuit.
To avoid this failure, an operating model selection circuit shown in Figure 4-6 can be
used to solve this problem. The signal 𝑉ra is used to control the dead-time instead of the
̅̅̅2 and ̅𝑅𝑒
̅̅̅. When the boost converter
signal 𝑉comp . 𝑉ra is controlled by 𝑉comp , 𝑉off , 𝑆̅1 , 𝑆
steps from the off-time phase into the dead-time phase, two models will be selected:
(1) 𝑉comp = 1 which means 𝑉out is still lower than 𝑉ref (𝑉out < 𝑉ref ) after an
̅̅̅2 and 𝑅𝑒
̅̅̅̅ are all equal to 1 and 𝑉ra will be
off-time. At this moment, 𝑉comp , 𝑉off , ̅̅̅
𝑆1̅, 𝑆
only controlled by 𝑉off. In Figure 4-7, we can see 𝑉coff will quickly fall below 𝑉in in the
dead-time phase thus causing 𝑉off rising to 1. Accordingly, 𝑉ra will be turned to 0 and
then S3 will be turned to 0 by the falling edge of 𝑉ra . S1 will be turned to 1 by the falling
edge of S3 which means a new cycle starts. In this case, because the dead-time is very
short, the boost converter works in the quasi-CCM mode.
(2) 𝑉comp = 0 which means 𝑉out is higher than 𝑉ref (𝑉out > 𝑉ref ) after an off-time.
At this moment, 𝑉ra is controlled by 𝑉comp . From Figure 4-7, we can see that, after some
time, 𝑉comp will rise to 1 because the output voltage falls below the reference voltage.
Then 𝑉ra will become 0 due to the falling edge of 𝑉comp and a new cycle begins. In this
case, due to a relatively long dead-time, the boost converter works in the DCM mode.
DCM
Q-CCM
Vref
Vout
（1）
（2）
S3
S1
S2
Vcoff
Vin
Voff
Vra
Vcomp
Figure 4-7: Timing diagram of quasi-CCM and DCM.
64
Circuit Implementation
From the above analyses, it becomes clear that, by using the operation model
selection circuit, automatic model selection can be really achieved thus ensuring the
converter to work properly. Moreover, the model selection circuit can also ensure a new
cycle starting after the previous cycle ending. The reason is that 𝑉ra can only be turned to
̅̅̅2 are 1, which means the boost converter is not working in the
0 when both 𝑆̅1 and 𝑆
on-time or the off-time phase.
The second issue which should be considered occurs in the S1 and S3 generation. The
signal S3 should be reset to 1 by the falling edge of 𝑉off rather than the low level of 𝑉off.
According to the working principle, Signal S3 is switched from 1 to 0 to terminate the
dead-time and start the on-time by the falling edge of Signal Vra. But at the falling edge of
𝑉ra , 𝑉off may be low due to system delay. If S3 is reset by the low level of 𝑉off, it may
miss the activated signal (the falling edge of 𝑉ra). If this happens, the boost converter will
not work correctly. The timing diagram of this problem is shown in Figure 4-8.
S3
Voff
Vra
Figure 4-8: Timing diagram of S3 triggering and resetting.
An extra D flip-flop can be used to reset S3 on the falling edge of 𝑉off. The detailed
circuit implementation is shown in Figure 4-9. The same problem also occurs in the
generation of S1. So the same circuit is applied for S1 generation as well.
S1
VDD
D
Q
S3
VDD
S3
S3
D
Q
Vra
CLK
Q
Re
CLK
Q
Re
Reset
Reset
VDD
D
Q
VDD
D
Voff
CLK
Q
Q
Re
Von
CLK
Q
Re
Figure 4-9: S1 and S3 generating circuits.
S1
4.2 Digital Logic Block
65
The third issue which should be paid attention to is the overlap of Signals S1 and S2.
From Figure 4-10, we can see that if the two power switches are closed simultaneously,
the output of the DC-DC convertor will be shorted to ground. Not only the energy stored
in the load capacitor will be lost, but also the output voltage ripple will be affected by the
short. Therefore, the overlap of S1 and S2 should be avoided at all times. As shown in
Figure 4-4, the S2 is triggered by the falling edge of S1 in this design. Hence, this problem
does not occur any more.
L
Vin
Vmid
Psw
Nsw
Vout
C
Iload
VSS
Figure 4-10: Output of the boost converter short to the ground.
4.3 On-Time and Off-Time Generators
In Section 3.5, we have discussed the selection of the implementation method for the time
generators in this work, and their basic schematics have been shown in Figure 3-21 and
Figure 3-22. In this section, the transistor-level circuit implementation will be described.
Figure 4-11 shows the transistor-level circuit of the on-time and off-time generators. The
parameters of all transistors are shown in Table 4-1. Figure 4-11 (a) is the circuitry of the
on-time generator, and Figure 4-11 (b) is the circuitry of the off-time generator. In the
circuits, the transistors M1, M2, M5, M6, M8 and M9 work as current mirrors which
provide charging and discharging currents, Transistors M3, M4, M7, M10 and M11 are
applied as switches which are controlled by S1, S2 and S3.
VDD
VDD
M4
S3
M9
M8
Ioff
IRon
Ib
Ib
S2
Itune
M10
Comp1
S1
M3
Ion
VCon
Von
Vin
Ioff0
S2
M7
VCoff
Comp2
Vin
M1
M2
S11
Con
VSS
M5
VSS
(a)
Coff
M6
M11
IRoff
(b)
Figure 4-11: Circuit implementation of the on-time and off-time generators.
Voff
66
Circuit Implementation
Table 4-1: Parameters of the transistors in the on-time and off-time generators
M1
2
0.2
1
10
L (μm)
W (μm)
F (μm)
M (μm)
M2
2
0.8
1
100
M3
0.1
0.6
2
1
M4
0.04
2.4
7
2
M5
2
0.2
1
10
VDD
M6
2
0.2
1
80
M7
0.1
0.6
2
1
M8
2
5
2
2
M9
2
5
2
2
M10 M11
0.1 0.04
0.9
1.2
2
7
1
1
VDD
M4
VDD
M4
M4
S3
S3
IRon
S3
Ion
VCon
M3
VCon
M3
Von
S1
Comp1
Con
Comp1
Vin
Ion
Con
VSS
On-time Phase
Ton
VSS
Off-time Phase
Toff
S1
Comp1
Vin
Ion
Con
VSS
S1
Von
S1
S1
Vin
Ion
VCon
M3
Von
Dead-time Phase
Tdead
S1
S3
S3
S3
Vcon
Vin
Vcon
Vin
Vcon
Vin
Von
Von
Von
Figure 4-12: Different working phases of the on-time generator.
Figure 4-12 shows the working conditions of the on-time generator in different
phases. In the on-time phase, switch M3 is close and switch M4 is open. The capacitor
𝐶on with an initial voltage 𝑉DD is discharged by a constant current 𝐼on. The voltage of
node 𝑉con drops down on a rate of,
𝑑𝑉𝑐𝑜𝑛
𝑑𝑡
=
𝐼𝑜𝑛
𝐶𝑜𝑛
(4.3)
When 𝑉con drops to the value 𝑉in , i.e., the same voltage as appeared at the other input of
the comparator, the comparator will output an active signal (falling edge) to the Digital
Logic block. This signal will shift the boost converter from the on-time phase to the
off-time phase. In the off-time phase, switch M3 and M4 are both open. The voltage of
node 𝑉con will remain at a value which is slightly lower than 𝑉in and the output of the
comparator will stay low. In the dead-time phase, the switch M3 is open and the switch
M4 is closed. The capacitor is quickly charged to 𝑉dd. In this phase, the output of the
comparator will return to the high level.
4.3 On-Time and Off-Time Generators
67
From the analysis in Chapter 2, we know 𝑉in , 𝑉dd and 𝑡on is 0.4𝑉, 1𝑉 and 150𝑛𝑠,
respectively. According to Equation 4.3, we can get:
𝐶𝑜𝑛
𝐼𝑜𝑛
=𝑉
𝑡𝑜𝑛
150𝑛𝑠
𝑜𝑢𝑡 −𝑉𝑖𝑛
= 1𝑉−0.4𝑉 = 250𝑛𝐹/𝐴
(4.4)
Under the consideration of acceptable power consumption, the discharging current (Ion) is
set to be 10μA in this work. Hence the capacitor Con becomes
𝐶on = 250𝑛𝐹/𝐴 × 𝐼on = 2.5𝑝𝐹
(4.5)
For lower power consumption, the discharging current can be further reduced. As a result,
capacitor 𝐶on should be decreased as well. Table 4-2 shows the simulation results of the
power consumption of the on-time generator with different discharging currents.
In Table 4-2, we can see that the decrement of the discharging current makes little
contribution to reducing the power consumption. This demonstrates that it is a reasonable
decision to set the discharging current and the capacitor as 10𝜇𝐴 and 2.5𝑝𝐹 in this work.
Table 4-2: Power consumption of the on-time generator for different discharging currents
Discharging current 𝐼on
Pton_generator at high load condition (10mA)
Pton_generator / Pin at high load condition (10mA)
Pton_generator at low load condition (0.1mA)
Pton_generator / Pin at low load condition (0.1mA)
VDD
M8
10μA
9.6μW
0.093%
3μW
2.471%
VDD
M9
VDD
M8
M9
M10
S2
M7
Vin
Vin
M7
M9
Ioff0
Coff
M10
S2
Voff
M7
VCoff
Comp2
Ioff0
S2
M11
S3
S2
Voff
Comp2
Ioff0
M8
Ioff
M10
Itune
VCoff
S2
1μA
4.3μW
0.091%
2.9μW
2.45%
Comp2
Ioff0
Coff
VSS
M11
Coff
S3
IRoff
VSS
On-time Phase
Off-time Phase
VSS
Dead-time Phase
Tdead
Toff
Ton
Voff
VCoff
S2
M11
S3
Vin
S2
S2
S2
S3
S3
S3
Vin
Vcoff
Vin
Vcoff
Vin
Vcoff
Voff
Voff
Voff
Figure 4-13: Different working phases of the off-time generator.
68
Circuit Implementation
Figure 4-13 exhibits the working conditions of the off-time generator working in
different phases. In the on-time phase, switches M7, M10 and M11 are all open. The
voltage of node 𝑉off will remain the same value as it is in the dead-time phase, and the
output of the comparator will stay high. In the off-time phase, switch M11 is open and
switches M7 and M10 are closed. The capacitor is charged by a constant current 𝐼off . The
voltage of node 𝑉coff rises at a rate of,
𝑑𝑉coff
𝑑𝑡
I
= 𝐶off
off
(4.6)
When 𝑉coff rises to the same value (𝑉in) as present at the other input of the comparator,
the comparator will output an active signal (falling edge) to the Digital Logic blocks
which will terminate the off-time phase and turn the boost convertor to the dead-time
phase. In the dead-time phase, switches M7 and M10 are both open and the switch M11 is
closed. The capacitor is fast discharged to 0𝑉. The output of the comparator will return to
the high level during this phase.
According to Equation 2.32, if the on-time is 150𝑛𝑠, the off-time is required to be
100𝑛𝑠 for the timing balance. In order to generate a 100𝑛𝑠 off-time, based on Equation
4.3, it follows:
𝐶off
𝐼off
𝑡
= 𝐶 off =
coff
100𝑛𝑠
0.4𝑉
= 250𝑛𝐹/𝐴
(4.7)
Since the charging current 𝐼off in the off-time generator should be tuned in a range so as
to adjust the off-time for achieving the ZCS adjustment (the detailed operating principle
will be presented in the next section). Under the consideration of the ZCS adjustment
resolution, this current cannot be too small. Therefore, the value of the charging current
𝐼off is finally set to be 10𝜇𝐴, and 𝐶off becomes
𝐶off = 250𝑛𝐹/𝐴 × 𝐼off = 2.5𝑝𝐹
(4.8)
As mentioned above, transistors M1, M2, M5, M6, M8 and M9 work as current
mirrors in the time generators. In general, it is better to use a transistor with larger size for
the current mirror application due to the better performance on mismatch and noise. But
since the charging and the discharging currents in the time generators are relatively small
(in microampere level), the transistors with too large size will lead to a longer setting time
which will reduce the accuracy of the time generators or even break down the
functionality of the boost converter. From the simulation results shown in Figure 4-14,
this issue can be seen clearly.
Figure 4-14 (a) is the simulation results of the time generators in which the channel
lengths (L) of the transistor M1, M2, M5, M6, M8 and M9 are 2𝜇𝑚. Figure 4-14 (b) is the
simulation results of the time generators in which the channel lengths (L) of the transistor
M1, M2, M5, M6, M8 and M9 are 3𝜇𝑚. The W/L ratios of the transistors are the same on
these two conditions. But in Figure 4-14 (b), the larger L leads to a bigger parasitic
capacitor, thus causing a longer settling time. If in this case, the average currents during
the on-time and the off-time will be far away from the desired value. As a result, the
4.3 On-Time and Off-Time Generators
69
generated time based on Equations 4.2 and 4.3 will not be accurate. In this work, the
channel lengths of the transistors M1, M2, M5, M6, M8 and M9 are determined as 2𝜇𝑚.
Figure 4-14: Simulation results of the time generators with different channel length.
In the circuitry of the time generators (Figure 4-11), transistors M3, M4, M7, M10
and M11 are applied as switches. Among these transistor-based switches, M4 and M11
should have a very large W/L, because the voltage of node 𝑉con need be immediately
charged to 𝑉dd and the voltage of node 𝑉coff need to be immediately discharged
to 𝑉ss in the dead-time phase, especially when the boost converter works in the
quasi-CCM mode (the dead-time is very short). In this work, the W/L of M4 is chosen to
be 840 and the W/L of M11 is chosen to be 200. The simulation results are shown in
Figure 4-15. The reset time of nodes 𝑉con and 𝑉coff are approximately 600𝑝𝑠. The
maximum current passing through the transistors during the reset process is about 5𝑚𝐴.
Figure 4-15: Reset of nodes Vcon and Vcoff in the dead-time phase.
70
Circuit Implementation
4.4 Zero Current Switching Adjustment Blocks
The operating principle of the zero current switching (ZCS) adjustment has been
described in Section 3.6. The transistor-level circuit implementation will be introduced in
this section. Figure 3-24 showed the system-level diagram of the ZCS adjustment block.
In this block, a 1-bit ADC is applied to detect the high/low state of node 𝑉mid at the end
of the off-time phase. A simple digital block (up/down counter) receives the ADC’s
information and adjusts the digital code which carries the information about how much
the off-time should be corrected. A DTC is controlled by the digital code and generates
additional time to correct the off-time. The tuning range of this block is −15𝑛𝑠~ + 15𝑛𝑠.
The minimum tuning step is 1𝑛𝑠.
Since only the high/low state of 𝑉mid need to be detected, the 1-bit ADC can be
implemented by a CMOS D flip-flop. Compared with an analog ADC, this method is
more power efficient. The circuit of the 1-bit ADC is illustrated in Figure 4-16. 𝑉p is the
drive signal of the PMOS power switch transistor. When 𝑉p turns from low to high, the
high-side power switch is turned open which means the off-time ends and the dead-time
starts. At this moment, the drain voltage of the PMOS power switch transistor 𝑉mid will
have a positive voltage jump or a negative voltage jump according to the state
(positive/negative) of the inductor current. The working principle has been explained in
Section 3.6 by Figure 3-23. Hence, 𝑉mid is connected to the D terminal and 𝑉p is used as
the clocking signal for the D flip-flop. In addition, the D flip-flop will be reset by 𝑉n in the
on-time phase. 𝑉n is the drive signal of the low-side NMOS power switch transistor.
Vmid
Up/down
D
Vp
Delay
Vdet
Q
CLK
Re
Vn
Figure 4-16: A D flip-flop 1-bit ADC.
However from the simulation result, an unexpected ringing is seen at node
𝑉mid when the boost converter is switched from the off-time phase to the dead-time phase
(as shown in Figure 4-17). Because node 𝑉mid is also connected to the large inductor, the
ringing is perhaps caused by the effect of the inductor and some other parasitic capacitors.
The specific reason of this ringing will be studied further in future works. The ringing
will perhaps cause a false reading of the inductor current at the end of the off-time and
result in an opposite ZCS adjustment. Comparing Figures 4-17 and 3-23, we can find the
reason of the false reading. For instance, to compare Figure 4-17a with 3-23a, if the
voltage detection happens on the top half-wave position, the off-time will be further
increased thus making an opposite adjustment.
In this work, the problem is solved by adding a short delay between the clocking
4.4 Zero Current Switching Adjustment Blocks
71
terminal of the D flip-flop and the signal 𝑉p . Figure 4-17 shows this solution. The state
(positive/negative) of the inductor current at the beginning of the dead-time can be
illustrated by the original direction of the ringing waveform. If the inductor current has
dropped below zero at the end of the off-time, the starting direction of the ringing
waveform will be negative (Figure 4-17a). On the contrary, if the inductor current is still
higher than zero when the off-time ends, the starting direction of the ringing will be
positive (Figure 4-17b). Therefore a careful setting of the delay time can guarantee the
correct reading of the inductor current state (positive/negative) at the end of the off-time
thus guaranteeing the function of the ZCS adjustment block.
ton
toff
ton
tdead
iL
iL
0A
0A
VN
VN
Delay
VP
DC
Vdet
tdead
Delay
VP
Vdet
Vmid
Vmid
0V
toff
DC
0V
（a）
（b）
Figure 4-17: Voltage detection for an overlong or insufficient off-time.
The output signal of the 1-bit ADC presents the state of the inductor current at the
end of the off-time. If the output is high, it means the inductor current at the end of the
off-time is positive, thus the duration of the off-time should be increased in the next cycle.
If the output is low, it means the inductor current at the end of the off-time is negative and
the off-time should be decreased in the next cycle. An up/down counter can be applied to
read the output signal of the 1-bit ADC and to adjust the off-time. According to the
analysis in Section 3.6, the up/down counter will output a 5-bit binary code to control the
DTC. A general up/down counter is applied in this work. When it is reset, the initial state
of the output signal is 10000. If the output signal of the counter exceeds the range (11111),
the counter will be automatically reset to the initial state.
The digital code output from the up/down counter is applied to control a DTC to
calibrate the off-time for ZCS adjustment. From the discussion in last section, we know
the off-time is generated by applying a current (𝑖off ) to charge a capacitor (𝐶off ) (Figure
3-a1). Hence, the ZCS adjustment block can adjust either the charging current 𝑖off
(current mode) or the charged capacitor 𝐶off (capacitor mode) to achieve the off-time
calibration. Then the off-time generating equation will be changed to:
Current mode:
𝑡off ± 𝑡ad = 𝑖
𝐶off
off ±𝑖ad
× 𝑉in
(4.9)
72
Circuit Implementation
𝑡off ± 𝑡ad =
Capacitor mode:
𝐶off ±𝐶ad
𝑖off
× 𝑉in
(4.10)
To achieve 1ns minimum tuning step for the ZCS adjustment (𝑡𝑎𝑑_𝑙𝑠𝑏 = 1𝑛𝑠), 1 LSB
of the DTC should be 100𝑛𝐴 (𝑖𝑎𝑑_𝑙𝑠𝑏 = 100𝑛𝐴) in current-mode or 25𝑓𝐹 (𝐶𝑎𝑑_𝑙𝑠𝑏 =
25𝑓𝐹) in capacitor mode. A comparison of these two methods on accuracy can be made
dependent on the matching formulas in TSMC-40nm technology files. By hand
calculation, the accuracies of 1 LSB adjustment for the current mode (𝜕(∆𝐼off_lsb )/
𝜕(𝐼off_lsb )) and for the capacitor mode (𝜕(∆𝐶off_lsb )/𝜕(𝐶off_lsb )) are both about 1%.
Although the results show the capacitor mode is a little better (about 0.2%) than the
current mode, the difference is rather small. In terms of area, a 1 LSB tuning capacitor
(25fF) occupies about 20𝜇𝑚2 area, but a 1 LSB tuning current source (100nA) just needs
less than 0.5𝜇𝑚2 area. So the current-mode DTC is much better than the capacitor-mode
DTC with respect to area. The power consumption of the capacitor-mode DTC should be
undoubtedly less than the current-mode DTC because it is theoretically free of static
current. But the power consumption of the current-mode DTC is also relatively small
compared with the total power loss of the whole converter system (its maximum static
current is just 1.5μA). A comparison chart of these two methods is listed in Table 4.3.
Under the consideration of accuracy, area and power consumption, the current-mode DTC
is finally employed in this work. Figure 4-18 illustrates the schematic of a current-mode
DTC which is implemented by adding a current-steering DAC in the off-time generator.
The current-steering DAC is applied to generate the additional time for the off-time
calibration. The current-steering DAC is based on an array of matched current sources
which are unity code or binary weighted.
Table 4.3: Comparison between the current-mode DTC and the capacitor-mode DTC
Accuracy
Area
Power consumption
Current mode
A little worse
Much smaller
Larger but acceptable
Capacitor mode
A little better
Much larger
Smaller
Off-time Generator
Current-steering DAC
vdd
vdd
i4
i3
i2
iad
i1
i0
ioff
Comparator
Vcoff
B4
B3
B2
B1
B0
iad
Vin
Coff
Digital Code
Vcoff
Figure 4-18: Current-mode DTC for the off-time calibration.
Vo
4.4 Zero Current Switching Adjustment Blocks
73
As discussed before, the up/down counter outputs a 5-bit binary code to control the
DAC. However, there will be some problems existing in a fully binary-controlled DAC.
As mentioned in [1], the monotonicity cannot be guaranteed, the DNL errors and the
glitch energy are both large. By contract, a thermometer-controlled DAC with only unit
elements can have better performance at a time. Since the thermometer-controlled DAC
only changes one bit in each reaction, the monotonicity can be guaranteed. Moreover, for
a binary-controlled DAC, the current branch controlled by high-order digital codes
requires to generate large current which will cause large glitch energy and DNL error. But
for a thermometer-controlled DAC, because each current branch produces an equal
amount of current, which is not large, the glitch energy and DNL error will be smaller
than for a binary-controlled DAC. However, this implementation also has its drawbacks
such as the requirements on more control signals and more area. Hence, in order to take
the advantages of two structures, a segmented structure is applied to implement the
current-steering DAC.
The n-bit input digital code is segmented into m less significant bits (LSBs) and (n-m)
most significant bits (MSBs). The m-bit LSBs are used to control the binary weighted
current branches and the (n-m)-bit MSBs are decoded from binary to thermometer to
control the unary current branches. By applying this structure, not only the problem of
non-monotonicity, large glitch energy and large DNL error can be solved by the
high-order code thermometer control, but also the number of control signals and area can
be effectively reduced by low-order code binary control. The ratio of the number of
MSBs (n-m) over the number of LSBs (m) is named segmentation. For conventional
designs, optimum segmentation is 75% [2]. In [1], a segmentation of 90% is used for
good performance in high-speed design. In this work, the 5-bit binary output of the
up/down counter can be segmented to 3/2 (60%) or 4/1 (80%) to control the DAC. Under
consideration of simple implementation and acceptable performance, the segmentation is
finally determined as 60%, which means the high-order 3 bits is decoded to thermometer
and the low-order 2 bits are remained in binary. Figure 4-19 illustrates the final
implementation of the ZCS adjustment block in system level.
Clock
Vmid
1-bit
ADC
Up/Down
Low-order 2-bit binary
Delay
Up/Down
Counter
Toff_ad
5-bit binary
DTC
High-order
3-bit binary
B-T
Decoder
7-bit
Thermometer
Figure 4-19: System-level diagram of the ZCS adjustment block
Due to the segmentation mechanism, the input signal of the DAC is 2-bit binary
74
Circuit Implementation
weighed and 7-bit unary weighed. The schematic of the two current branches controlled
by the 2-bit binary is shown in Figure 4-20. In here, two NMOS transistors Mb1 and Mb2
are used as current mirrors to generate 100𝑛𝐴 (1 LSB) and 200𝑛𝐴 (2 LSBs) current in
each branch. Since these two branches generate the two minimum current signals in the
DAC, the accuracy of these two current mirrors is the most important specification. The
accuracy of a MOS transistor-based current mirror is mainly determined by three
parameters of the copying transistor: generated current, overdrive voltage and area. There
have been a lot of studies on their relationship. The detailed equations are not described
here. In general, the larger these three parameters are, the better the current mirror’s
accuracy is. In this work, since the target currents have been determined, the controllable
parameters are only the overdrive voltage and the area. But due to the quite small
generated currents (hundreds of 𝑛𝐴𝑠), a large overdrive voltage means a small width to
length ratio (W/L), and the parasitic capacitors caused by large area will affect the
performance of the current mirror in high-speed operating condition (several MHz).
Therefore, in the trade-off, the overdrive voltage is set to about 80𝑚𝑉 and transistors with
relatively small size are used for Mb1 and Mb2 in the end. The detailed parameters are
listed in Table 4.3.
As shown in Figure 4-20, differential pairs of NMOS transistors are used as the
switches to control each current branch connected to the output of the DAC (𝑉coff) or not.
By applying this method, a constant current occurs in every current branch, but the
current flows to different places under the control of two complementary switches. The
drain voltage of each current mirror transistor (𝑉x , 𝑉y ) is fixed, thus cancelling the effect of
𝑉ds variation on the generated current. Because these two current branches generate the
minimum current signals, the additional power consumption due to the constant current
can be ignored. The accuracy is more important than the power consumption for these
two current branches. The size of these switch transistors should be small so as to reduce
the parasitic capacitors for high-speed application. The detailed parameters of these
transistors are listed in Table 4-5.
Vcoff
vdd
10μA
Ib
B2
B2n
Vy
Ms2
M0
Vload
200nA
Mb2
Ms2n
100nA
B1n
B1
Vx
Ms1n
Ms1
Mb1
vss
Figure 4-20: Two current branches controlled by 2-bit binary digital code in the DAC.
4.4 Zero Current Switching Adjustment Blocks
75
The schematic of the other seven unary current branches is shown in Figure 4-21.
Each branch generates the same current (400𝑛𝐴) which represents 1 MSB in the DAC.
All branches use the same structure and transistors. Because the currents in these
branches are relatively large, for a high efficient, a single transistor is used as the switch
in each branch rather than the complementary structure applied in the binary-controlled
branches. The detailed parameters of the transistors are listed in Table 4-4.
vdd
Vcoff
10μA
400nA
Ib U7
U6
Ms9
400nA
Mu6
400nA
U4
U5
Ms8
Mu7
M0
400nA
400nA
400nA
U2
U3
Ms7
Ms6
Ms5
Mu5
Mu4
Mu3
400nA
U1
Ms4
Mu2
Ms3
Mu1
vss
Figure 4-21: Seven current branches controlled by 7-bit unary digital code in the DAC.
Table 4-4: Parameters of the transistors in the DAC
L
W
M
M0
Mb1
Ms1
Ms1n
Mb2
Ms2
Ms2n
Mu1~ Mu7
Ms3~ Ms10
2μ
0.2μ
100
2μ
0.2μ
1
0.1μ
0.6μ
1
0.1μ
0.6μ
1
2μ
0.2μ
2
0.1μ
0.6μ
1
0.1μ
0.6μ
1
2μ
0.2μ
4
0.1μ
0.6μ
1
4.5 Comparator
No matter which kind of control technique, there will necessarily be a comparator in the
control system of a DC-DC converter. For instance, as mentioned in Section 3.2, in the
voltage-mode control or the current-mode control system, a comparator is used to
compare the output of the error amplifier with a ramp signal, and then outputs a signal to
adjust the duty cycle of the PWM signals which control the power switches. In a PFM
ripple-based control system, the comparator plays a more important role since it replaces
the function of the error amplifier to regulate the output voltage of the DC-DC converter.
A comparator continuously monitors the output of the DC-DC converter. If the output
voltage of the converter drops or rises across the reference voltage, the comparator will
send an active signal to the Digital Logic blocks and then shift the operating phase
(on-time, off-time or dead-time) of the DC-DC converter. The specific working principle
76
Circuit Implementation
has been described in Section 3.4 and Section 4.1.
In this work, since the PFM ripple-based control technique is applied, no error
amplifier exits in the control system. The output voltage of the boost converter is
regulated by a comparator. For the comparator in this application, some characteristics
should be considered during the design. The most important one is the propagation delay.
Figure 4-22 illustrates the effect of the comparator delay on the performance of the boost
converter. A large comparator delay will make the triggering point far away from the
comparison point thus increasing the dead-time. When the boost converter works at a
light load condition, a large comparator delay will not give much trouble to the boost
converter, since the additional dead-time caused by comparator delay is a small portion of
the whole dead-time. In this case, only the DC (average) value of the output voltage of
the boost converter will be slightly decreased as shown in Figure 4-22 (a). So it means
that just the output regulating accuracy of the boost converter is impaired by the large
comparator delay at light load condition. However, when the boost converter works with
a high load, if the comparator delay is too large, besides the regulating accuracy, even the
functionality of the boost converter will be destroyed. As shown in Figure 4-22 (b), if the
dead-time is too long such that the energy discharging in the dead-time and the on-time
has been larger than the energy charging in the off-time, the output of the boost converter
cannot stay in a steady state, which means the stability of the converter has been
interfered by the large comparator delay. Therefore, the propagation delay of the
comparator should be designed to be a small value.
tdead
ton
toff
toff
tdead
S1
tdead
ton
toff tdead ton
S1
S2
S2
triggering
point
Vout_avg
triggering
point
with small delay
Vout
Vout
Vref
Comparison
point
td
Vout_avg
with large delay
(a)
triggering
point
Vref
Comparison
point
td
Comparison
point
td
(b)
Figure 4-22: Comparator delay effect under (a) low load and (b) low load.
Apart from the propagation delay, the uncertain transition region of the comparator
which is determined by the noise level should be controlled in a safe range. In this design,
the comparator is applied to compare the small output ripple of the boost converter with a
reference DC voltage, and the minimum output ripple is only about 10mV. Therefore, the
detection range of the comparator should be much smaller than 10mV. In addition, since
in this design, the comparator is the only block which needs to constantly operate in the
whole control system besides the biasing block, its power consumption takes up a large
portion of the total power consumption. In order to design a boost converter with very
high power conversion efficiency, after ensuring the functionality of the comparator, its
4.5 Comparator
77
power consumption should be optimized as much as possible.
In this work, besides the comparator used for the output regulation, there are still
two comparators existing in the time generators to control the duration of the on-time and
the off-time. Their working principle has been described in Section 4.3. For these two
comparators, due to their different application, the functionality and the performance are
less sensitive to the propagation delay and the noise compared to the other comparator.
Hence, the static current in these two comparators could be set at a smaller value to
reduce the power consumption. As a consequence, the propagation delays will be larger.
In this work, a two-stage, open loop comparator is applied in the control system of
the boost converter. The schematic of the comparator is shown in Figure 4-23. For the
comparators applied in the time generators, since the comparison point is about 0.4𝑉, a
differential pair of PMOS transistors can be used as the input stage. For the comparator
applied for the output voltage regulating, as the output voltage of the boost converter can
be dropped down by a voltage divider, the comparison point can also be set at about 0.4𝑉.
For simplification, the comparator in the two applications can use the same structure
(shown in Figure 4-23) but with different bias currents for different propagation delays.
vdd
Mbp0
Mbp1
Mbp2
Ibc1
Ibc2
Ib
M1
Vout
M2
Vn
Vp
M5
M3
Mbn1
M4
Mbn2
vss
Figure 4-23: Schematic of the comparator.
In the schematic of the comparator, transistors M1 and M2 are the differential input
pairs of the first stage. Due to a low bias current, these two transistors work in the
subthreshold region. Transistor M5 is the input of the second stage. It works in the
saturation region. The poles of the comparator caused by two stages can be expressed as:
𝑝1 =
𝑝2 =
𝑔𝑑𝑠_𝑀2 +𝑔𝑑𝑠_𝑀4
𝐶1
𝑔𝑑𝑠_𝑀5 +𝑔𝑑𝑠_𝑀𝑏𝑝2
𝐶2
(4.11)
(4.12)
In which 𝐶1 is the sum of the capacitors connected to the output of the first stage and
𝐶2 is the sum of the capacitors connected to the output of the second stage. As a general
knowledge, the open loop amplifier which works as a comparator should have a large
78
Circuit Implementation
bandwidth. Hence, poles 𝑝1 and 𝑝2 should be at high frequency.
As mentioned above, for different applications, due to the different limitation for the
propagation delay, the bias currents are set at a different value. For a short propagation
delay, the bias currents (𝐼𝑏𝑐1 , 𝐼𝑏𝑐2 ) of the comparator which is used for the output
regulation are set at 2𝜇𝐴. As a result, the effect of the comparator delay to the accuracy of
the output voltage regulation is very weak. After a trade-off between the acceptable
propagation delay and power consumption, the bias current (𝐼𝑏𝑐1 , 𝐼𝑏𝑐2) of the comparators
which are used in the time generators are set at 0.2𝜇𝐴.
4.6 Reference Current Generator
In the control system of the boost DC-DC converter designed in this work, a precise and
stable current reference is indispensable, not only for the time generators to generate
pulse signals with desired duty cycles to drive the power switches (Section 4.2), but also
for the current-mode DAC in the ZCS adjustment block to slightly calibrate the off-time
(Section 4.4). As we know, many external factors can affect the accuracy of the
generating current, of which temperature and the supply voltage (𝑉𝑑𝑑 ) variation are two
dominant ones. Hence, to design a low power reference current generator which is in
sensitive to temperature and supply voltage (𝑉𝑑𝑑 ) variations becomes a crucial task.
In order to suppress the temperature effect on the generating current, the general idea
which has been widely applied is adding a positively scaled (PTAT) current to a
negatively scaled (CTAT) current [3]. By setting these two temperature compensating
currents in a proper ratio, the temperature effect can be canceled and the total current will
be, to a first order, independent of temperature.
Vdd
M3
M4
M1
M2
Ipt0
R1
vss
Figure 4-24: PTAT current source.
The PTAT current can be generated by the circuit shown in Figure 4-24. The
transistors M1 and M2 work in the subthreshold saturation region, and the transistors M3
4.6 Reference Current Generator
79
and M4 work in strong inversion saturation region as current mirrors. For a subthreshold
MOS transistor, there is:
𝑉
𝐼𝐷 = 𝐼0 𝑒𝑥𝑝 𝜁𝑉𝐺𝑆
(4.13)
𝑇
Accordingly, for M1 and M2, there are:
𝐼𝐷1
)
𝐼0_𝑀1
(4.14a)
𝐼𝐷2
)
𝐼0_𝑀2
(4.14b)
𝑉𝐺𝑆1 = 𝜁𝑉𝑇 ln(
𝑉𝐺𝑆2 = 𝜁𝑉𝑇 ln(
Since M1 and M2 compose a current mirror, their source currents are in a ratio of:
𝐼𝐷2
𝐼𝐷1
𝐼
𝑆4
= 𝐼𝑆4 = 𝑆3
(4.15)
𝑆3
in which, S3 and S4 are the aspect ratios of the transistor M3 and M4. Then, the current
flowing through the resistor R1 can be expressed as:
𝐼𝑝𝑡0 =
𝑉𝐺𝑆2 −𝑉𝐺𝑆1
𝑅1
=
𝐾𝑇
𝑆1 𝑆4
ln(𝑆2 ∙ 𝑆3)
𝑞
(4.16)
Therefore, the current 𝐼𝑝𝑡0 generated in this part is a PTAT current.
The CTAT current can be generated based on the conclusion proposed in [3]. It says
that, after biasing a constant drain current, the gate-source voltage of a MOSFET which
works in subthreshold region, decreases linearly with temperature. An approximation
equation between the gate-source voltage (𝑉𝐺𝑆 ) and temperature (𝑇) is obtained in [3]:
𝑇
𝑉𝐺𝑆 (𝑇) ≈ 𝑉𝐺𝑆 (𝑇0 ) + 𝐾𝐺 (𝑇 − 1) ,
0
(4.17)
where
𝐾𝐺 ≅ 𝐾𝑇 + 𝑉𝐺𝑆 (𝑇0 ) − 𝑉𝑇𝐻 (𝑇0 ) − 𝑉𝑂𝐹𝐹
(4.18)
For typical values of 𝐾𝑇 and 𝑉𝑂𝐹𝐹 which are BSIM3v3 model parameters, 𝐾𝐺 is a
negative quantity [3] thus causing the voltage 𝑉𝐺𝑆 to decrease with temperature.
Therefore, a CTAT current 𝐼𝑛𝑡0 can be obtained by applying the CTAT voltage 𝑉𝐺𝑆 on a
resistor, which can be expressed as:
𝐼𝑛𝑡0 =
𝑉𝐺𝑆 (𝑇)
𝑅
=
𝑉𝐺𝑆 (𝑇0 )
𝐾
𝑇
+ 𝑅𝐺 (𝑇
𝑅
0
− 1)
(4.19)
A simple circuit to combine the PTAT current and the CTAT current for getting a
temperature independent current is shown in Figure 4-25, which was proposed in [4].
This implementation method is much simpler than the circuit proposed in [3]. In this
circuitry, M1, M2, M3 and M4 compose the PTAT current generator, and the generating
PTAT current 𝐼𝑝𝑡0 is copied to the output by the current mirror composed of M3 and M9.
In addition, M5, M6, M7 and M8 compose the CTAT current generator and the generating
CTAT current 𝐼𝑛𝑡0 is copied to the output by the current mirror composed of M8 and M9.
Then, the output current 𝐼𝑏 can be expressed as:
𝑆9
𝐼𝑏 = 𝑆3 𝐼𝑝𝑡0 +
𝑆10
𝐼
𝑆8 𝑛𝑡0
= 𝐾1 (𝑇) + 𝐾2 (𝑇)
(4.20)
80
Circuit Implementation
If the derivative of the output current 𝐼𝑏 with respect to temperature T is zero (𝜕𝐼𝑏 /𝜕𝑇 =
0), the output current 𝐼𝑏 is independent of temperature. This can be done by a proper
setting of the ratio of the PTAT current 𝐼𝑝𝑡0 and the CTAT current 𝐼𝑛𝑡0 .
vdd
M3
M4
M5
M9
M10
M8
Ipt0
PTAT
M7
M1
Ipt
Int
M2
M6
CTAT
Ib
R1
R2
Int0
Vo
vss
Figure 4-25: Combination of a PTAT current source and a CTAT current source [4].
Another factor that can affect the accuracy of the generating current is the supply
voltage (𝑉𝑑𝑑 ) variation. Due to the channel-length modulation effect, if the source-drain
voltage on a transistor is changed, the drain current of this transistor will also be different.
The supply voltage (𝑉𝑑𝑑 ) variation can lead the PTAT current generator and CTAT current
generator to make a positive response, which means, if there is an increment on the
supply voltage (𝑉𝑑𝑑 ), both the PTAT and CTAT currents will be increased, and vice versa.
The supply voltage (𝑉𝑑𝑑 ) variation effect can be suppressed by just adding an N-time
of the PTAT current to the CTAT current generator [4]. The detailed implementation is
shown in Figure 4-26. The transistor M11 composes a current mirror with the transistor
M3, which adds an N-time of the PTAT current 𝐼𝑝𝑡1 (𝐼𝑝𝑡1 = 𝑁 ∙ 𝐼𝑝𝑡0 ) to the CTAT
current generator. After adding this block, the current flowing through the transistor M8 is
the sum of the CTAT current 𝐼𝑛𝑡0 and the N-time of the PTAT current 𝐼𝑝𝑡1 . The
expression of the final output current 𝐼𝑏 (equation 4.20) will be modified to:
𝑆9
𝐼𝑏 = 𝑆3 𝐼𝑝𝑡0 +
𝑆10 𝑉𝐺𝑆6
( 𝑅2
𝑆8
− 𝑁𝐼𝑝𝑡0 )
(4.21)
By taking the derivative of equation (4.21) with respect to 𝑉𝑑𝑑 , there is:
𝜕𝐼𝑏
𝜕𝑉𝑑𝑑
𝑆9
= (𝑆3 −
𝑆10
𝑁
𝑆8
+
𝜕𝐼𝑝𝑡0
𝜕(𝑉𝐺𝑆6 /𝑅2)
) × 𝜕𝑉𝑑𝑑
𝜕𝑉𝑑𝑑
(4.22)
Due to equation 4.14, the derivation of (𝑉𝐺𝑆6 /𝑅2) with respect to 𝑉𝑑𝑑 is:
𝜕(𝑉𝐺𝑆6 /𝑅2)
𝜕𝑉𝑑𝑑
𝜁𝑉𝑇 𝜕𝐼𝐷6
𝐷6 𝑅2 𝜕𝑉𝑑𝑑
=𝐼
𝜁𝑉𝑇 𝑆5 𝜕𝐼𝑝𝑡0
𝐷6 𝑅2 𝑆3 𝜕𝑉𝑑𝑑
=𝐼
(4.23)
4.6 Reference Current Generator
81
Finally, we can obtain that:
𝜕𝐼𝑏
𝜕𝑉𝑑𝑑
𝑆9
= (𝑆3 −
𝑆10
𝑁
𝑆8
+
𝜕𝐼𝑝𝑡0
𝑆10 𝑆5 𝜁𝑉𝑇
) × 𝜕𝑉𝑑𝑑
𝑆8 𝑆3 𝐼𝐷6 𝑅2
(4.24)
The negative item in Equation 4.24 can make that the expression in the bracket becomes
equal to zero, thus causing the derivative of the output current with respect to the supply
voltage variation to zero (𝜕𝐼𝑏 /𝜕𝑉𝑑𝑑 = 0). Therefore, the supply voltage variation effect
on the output current 𝐼𝑏 can be suppressed by this method.
vdd
M3
M4
M5
M11
M9
M10
M8
Ipt0
M7
M1
Int
Ipt
M2
M6
Ipt1=N·Ipt0
Ib
R1
R2
Int0
Vo
vss
Figure 4-26: Final schematic of the reference current generator.
Based on Equations 4.20 and 4.21, the output current 𝐼𝑏 can theoretically be
independent of temperature and supply voltage variation. But in real work, since many
parameters in the circuit are correlative to each other, it is different to find out the balance.
For example, a larger N for the additional current 𝐼𝑝𝑡1 is good to suppress the supply
voltage variation effect, but as a result, it will lead to a bad temperature compensation
behavior.
According to the result given in [4], if the target reference current is 1𝜇A, the effect
of the supply voltage variation on the reference current should be about 0.009μA/V and
the temperature effect on the reference current should be 0.027μA peak-to-peak for
temperature variation from -20°to 120°. But in this research, due to time limitation, the
circuit was not set in an optimal condition. The simulation results show that the supply
voltage variation on the reference current is about 0.07μA/V, and the temperature effect
on the reference current is about 0.29μA peak-to-peak for temperature variation from -20°
to 120°. An easy method to properly set the parameters in the circuit should be studied in
future work. The parameters of the transistors used in the work are shown in Table 4.5.
82
Circuit Implementation
Table 4-5: Parameters of the transistors in this block.
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
L (μm)
4
4
4
4
4
4
4
4
4
4
2
W (μm)
160
4
4
4
3
125
125
2
3.2
2.3
1
R1 = 160kΩ
R2 = 300kΩ
Bibliography
83
Bibliography
[1] Aliparast, Peiman, and Nasser Nasirzadeh. "Very high-speed and high-accuracy
current-steering CMOS D/A converter using a novel 3-D decoder."Analog Integrated
Circuits and Signal Processing 60, no. 3: 195-204, 2009.
[2] Chi-Hung Lin; Bult, K., "A 10-b, 500-MSample/s CMOS DAC in 0.6 mm 2," Solid-State
Circuits, IEEE Journal of, vol.33, no.12, pp.1948,1958, Dec 1998.
[3] Banba, H.; Shiga, H.; Umezawa, A.; Miyaba, T.; Tanzawa, T.; Atsumi, S.; Sakui, K., "A
CMOS bandgap reference circuit with sub-1-V operation," Solid-State Circuits, IEEE
Journal of, vol.34, no.5, pp.670,674, May 1999.
[4] Po-Hsuan Huang; Hongchin Lin; Yen-Tai Lin, "A Simple Subthreshold CMOS Voltage
Reference Circuit With Channel-Length Modulation Compensation," Circuits and
Systems II: Express Briefs, IEEE Transactions on, vol.53, no.9, pp.882,885, Sept.
2006.
84
Circuit Implementation
Chapter 5
Layout Design
5.1 Overview of the Layout Design
Due to the technology limitation and design consideration, not all components of the
boost DC-DC converter are integrated on-chip in this work. At first, the 1𝜇𝐻 inductor and
the 220𝑛𝐹 load capacitor are applied off-chip. The reason is that on-chip inductors or
capacitors with such a large inductances or capacitances have large area and poor series
resistance which will seriously reduce the efficiency of the boost converter. Secondly, for
easy output voltage control, the voltage reference and the output voltage divider of the
boost converter are implemented outside the chip as well, which means any required
output voltage can be obtained by just changing the off-chip parameters. Moreover, the
capacitor 𝐶f applied to improve the noise immunity of the boost converter (discussed in
Section 3.4) is also placed outside of the chip. As shown in Figure 5-1, the layout design
just involves the circuits in the red square.
On-chip
L
Vmid
Vout
Psw
Vmid
ZCS
Adjustment
Vin
Cf
Nsw
Vn
Vp
Rf1
±15ns
Comp
GND
ton=150ns
Ton
Generator
Von
Digital
Logitc
toff=100ns
Re
Toff
Generator
Vcomp
Vfb
Vref
Rf2
Voff
Figure 5-1: On-chip and off-chip parts of the boost DC-DC converter.
Cload Iload
86
Layout Design
The final layout of the entire on-chip system of the boost DC-DC converter is shown
in Figure 5-2. It includes two large power switch MOS transistors with buffers, three
comparators, two time generators, a current mirror array, a reference and bias current
generator, a ZCS adjustment block, a digital logic control block and some decoupling
capacitors. During the whole layout work, only two parts of the boost converter require
elaborate design because the functionality and the performance of the converter are very
sensitive to their effects. One of them are the MOS transistors used as the power switches,
and the other one is the current mirror array which includes the current-steering DAC
applied in the current-mode DTC for the ZCS adjustment. Later in this chapter, detailed
discussions will be given on the layout design of these two parts. As for the layout design
of the other blocks, because no special skills are applied, no detailed description will be
mentioned in the thesis.
Figure 5-2: Layout of the entire on-chip part of the boost DC-DC converter.
5.2 Layout Design of the Power Switches
87
5.2 Layout Design of the Power Switches
In Chapter 2, we have discussed the size of the MOS transistors used for the power
switches in the boost converter. To achieve a very low turn-on resistance, the aspect ratios
(W/L) of these MOS transistors should be very large. In this work, the final aspect ratios
of the two MOS transistors used as power switches in the boost DC-DC converter have
been shown in Table 2-1. So there are:
𝑊
𝐿
( )𝑛 = 35840
(5.1)
𝑊
( 𝐿 )𝑝 = 71680
(5.2)
From the equations, we can find that the aspect ratios of the power switch transistors
are extremely large. A problem consequently appears, that is, how to reasonably design
the layout of the transistors with such high aspect ratios. Obviously, it is impossible to
make it in the simplest structure as shown in Figure 5.3. Then, the finger structure can be
applied to reduce the aspect ratio of each transistor unit. In the finger structure, a single
transistor with an extremely high aspect ratio can be divided into many unit cells which
connect with each other. But as shown in Figure 5.4, we can find that, if the aspect ratio
of each unit cell is in a reasonable value, the number of the fingers will be very large. It
means this structure is still unreasonable in terms of the space. Therefore, more advanced
methods should be used to design the layout of the power switch transistors.
L=0.1μm
D
S
W=~3mm
Figure 5-3: Transistor with a large W/L in the simplest structure.
W=~3μm
L=0.1μm
S
D
S
D
S
D
F=~1000
Figure 5-4: Transistor with a smaller W/L in the finger structure.
88
Layout Design
In this work, we segment the large power switch transistors into several independent
small cells and place them in parallel (as shown in Figure 5.5). By using this approach,
the layout design for the power switch transistors will be easily implemented. The reason
is the transistor with a high aspect ratio has been segmented to 𝑁 independent cells and
the aspect ratio of each unit cell will be 1/𝑁 smaller. For example, 𝑁 is set to be 32 in
this work. For a unit cell of the NMOS power switch transistor, we only need to draw the
layout of a transistor with an aspect ratio of 112𝜇𝑚/0.1𝜇𝑚. By applying the finger
structure, it is easy to design the layout of such a unit cell. The layout implementation of a
unit cell is exhibited in Figure 5.6. In addition, an extra benefit can be obtained by using
this structure, that is, the turn-on resistance of the power switch transistor will be reduced
by the parallel structure. As mentioned in Section 2.2, since the static loss caused by the
power switch transistor’s turn-on resistance is a dominant factor in the loss mechanism,
this approach can effectively improve the efficiency of the boost converter.
A
Vin
A
A
A
A
Vin
SW_1
SW
B
SW_2
B
SW_3
B
SW_n
B
B
Figure 5-5: Segmentation of the large power switch transistor.
Figure 5-6: Unit cell of the power switch transistor.
After determining the size of each unit cell, the next step is to join the 32 unit cells
together and connect them to the two terminals of the power switch. Since, in this design,
the current flowing through the power switches is relatively large (about 60𝑚𝐴), the
relationship between the maximum tolerable current and the width of the Copper metal
5.2 Layout Design of the Power Switches
89
wire is required to be considered in order to prevent the failure in terms of reliability. The
equations of this relationship can be derived from the technical documents of TSMC
40nm technology [1]. For metal x (𝑥 = 1~6), there is:
𝐼max _𝑀𝑥 = 1.329 × (𝑊 × 0.9 − 0.008)
(5.3)
For metal y (𝑦 = 7~8), there is:
𝐼max _𝑀𝑦 = 3.04 × (𝑊 × 0.9 − 0.2)
(5.4)
The maximum current (𝐼max) is defined as the maximum DC current allowed for metal
lines, vias, or contacts. It is based on 0.1% point of measurement data at a 10% resistance
increase after 100𝐾 hours of continuous operation at 110℃ [1]. As the currents flowing
through the power switch transistors are in pulse wave, the effective DC current is equal
to the average current which can be calculated as:
1
𝜏
𝐼𝑎𝑣𝑔 = 𝜏 × ∫0 𝐼(𝑡)𝑑𝑡
(5.5)
For a current in a pulsed wave, the rules of the effective DC current (𝐼𝑎𝑣𝑔 ) are identical
to the rules of the maximum current (𝐼max) [1], which means the item 𝐼max in Equations
5.3 and 5.4 can be replaced by 𝐼𝑎𝑣𝑔 .
According to the rules mentioned above, the widths of the wires used to connect the
power switch transistor can be determined. In this work, for simplification, apply the
same structure to implement the layout of the PMOS and NMOS power switch transistors.
Since its size of the PMOS power switch transistor is two times of the NMOS power
switch transistor, two identical cells in parallel are applied to implement its layout design.
Therefore, we will just discuss the layout design for the NMOS power switch transistor.
150ns
100ns
ton
toff
~60mA
IL
Insw
Ipsw
ton
toff
Figure 5-7: Currents flowing through the inductor and power switch transistors.
As we know, the current flowing through the NMOS power switch transistor is equal
to the current flowing through the inductor during the on-time and the maximum duty
cycle of the current pulse exits when the boost converter works in the boundary of CCM
and DCM. As shown in Figure 5.7, the effective DC current flowing through the NMOS
90
Layout Design
power switch can be roughly calculated as:
1
𝜏
𝜏
𝐼𝑎𝑣𝑔_𝑛𝑠𝑤 = × ∫0 𝐼𝑛𝑠𝑤 (𝑡)𝑑𝑡 ≈ 40𝑚𝐴
(5.6)
As discussion before, the NMOS power switch transistor with a high aspect ratio has
been segmented into 32 unit cells. For each cell shown in Figure 5-6, the effective DC
current should be:
𝐼𝑎𝑣𝑔_𝑢𝑛𝑠𝑤 =
𝐼𝑎𝑣𝑔_𝑛𝑠𝑤
32
≈ 1.25𝑚𝐴
(5.7)
According to Equation 5.3, to tolerate a 1.25𝑚𝐴 current, the width of the wire (metal x)
should be more than 1.1𝑢𝑚. In this work, two metal wires with a width of 1.4𝑢𝑚 are
used to connect the source and drain area of the transistor to the two terminals (A and B
in Figure 5-5) of the power switch. In order to save area and increase the contact area,
these two metal wires can be placed above the transistor as shown in Figure 5-8. By using
this method, not only the area but also the resistance caused by the metal contacts can be
effectively reduced.
D
1.4μm
M3
D
S
D
S
D
S
M3
1.4μm
S
Figure 5-8: Source and drain connection of a unit transistor.
Two main power lines are required to connect the 32 unit cells together, one of
which is used to connect all the drain terminals of the unit transistors with the inductor,
and the other one is used to connect all the source terminals of the unit transistors to
ground. The current tolerance of these two power lines have been calculated by using
Equation 5.6, which should be more than 40𝑚𝐴. But as the maximum width of the metal
x wire is 4.95𝜇𝑚 and the maximum width of the metal y wire is 13.2𝜇𝑚 in this
technology, according to Equations 5.3 and 5.4, we can obtain that the maximum
tolerable current though a single-layer metal wire is:
𝐼max _𝑀𝑥 = 1.329 × (4.95 × 0.9 − 0.008) ≈ 5.9𝑚𝐴
(5.8)
𝐼max _𝑀𝑦 = 3.04 × (13.2 × 0.9 − 0.2) ≈ 35𝑚𝐴
(5.9)
It is obvious that only a single-layer metal wire cannot tolerate the current flowing
through the power switches. Therefore, multiple-layer metal wires in parallel can be used
to solve the problem. In this work, not only to increase the maximum tolerable current,
5.2 Layout Design of the Power Switches
91
but also to reduce the resistance caused by the wide metal wires, five-layer metal wires
are used for the power switch transistor. The structure of the five-layer metal wires is
shown in Figure 5-9. Since the metal contact areas are very large, the resistances of the
vias can be ignored. As shown in Figure 5-9 (a), a Metal 7 wire and a Metal 8 wire both
having a width of 13𝜇𝑚 are placed on two vertically parallel layers. Below these two
metal wires, metal 4, 5 and 6 wires are separately placed on three vertically parallel layers.
On each layer, three wires in the same metal and in the same width of 4𝜇𝑚 are placed in
horizontally parallel as shown in Figure 5-9 (b) (the area with dashed line). In this
structure, the maximum tolerable current of the total wires is:
𝐼max _𝑡𝑜𝑡𝑎𝑙 = 3 × (𝐼max _𝑀4 (4𝜇𝑚) + 𝐼max _𝑀5 (4𝜇𝑚) + 𝐼max _𝑀6 (4𝜇𝑚))
+𝐼max _𝑀8 (13𝜇𝑚) + 𝐼max _𝑀7 (13𝜇𝑚) ≈ 110𝑚𝐴
(5.10)
It is much larger than the maximum effective current flowing through the power switch
transistor. Hence, the reliability of the metal wires can be guaranteed even the flowing
current becomes larger.
(a)
(b)
Figure 5-9: 5-layer metal wire, (a) cross-section view, (a) top view.
Figure 5-10 shows two topologies of the final layout implementation of the NMOS
power switch transistor composed by 32 unit cells. Figure 5-10 (a) shows a general
structure, in which, two power lines 𝑉𝑚𝑖𝑑 and 𝑉𝑠𝑠 are placed on two sides of the unit
transistors. Figure 5-10 (b) shows an advanced structure which is similar with the finger
structure. In the second structure, the two power lines 𝑉𝑚𝑖𝑑 and 𝑉𝑠𝑠 are closer to each
other compared with the first one, which means the parasitic resistance will be lower and
the area will be smaller. A comparison experiment between these two structures has been
done. The simulation results show that the parasitic resistance caused by the metal
connection wires for the first structure is about 70𝑚𝛺; and the parasitic resistance
caused by the metal connection wires for the second structure is about 60𝑚𝛺. Since the
92
Layout Design
lower parasitic resistance can reduce the static power consumption thus improving the
power efficiency for the boost converter, the final layout implementation of the power
switch transistor in this work uses the structure shown in Figure 5-10 (b).
(a)
(b)
Figure 5-10: Two topologies of the NMOS power switch transistor’s layout.
For the transistor with a very high aspect ratio, the parasitic capacitance on the gate
is also very large. From the simulation results, we can obtain that, in this design, the gate
parasitic capacitance of the NMOS power switch transistor (3584𝜇𝑚/0.1𝜇𝑚) is about
1𝑝𝐹, and the parasitic capacitance induced by the metal wires (shown in Figure 5-10 (b))
is about 1.5𝑝𝐹. Thus, it means the signal used to turn the power switch on and off need to
drive a 2.5𝑝𝐹 load capacitor. In addition, the transition time of the power switch should
be short, as much energy will be lost on the switch during the transition time. Therefore, a
large buffer is required to drive the power switch. In this work, the transition time of the
NMOS power switch (shown in Figure 2-10) is controlled within 100𝑝𝑠, so according to
the charging/dis-charging equation of a capacitor, the average driving current of the
buffer should be about 25𝑚𝐴. Although the driving current is quite large, since the buffer
works in the high current condition only for a short while, the effective DC current of the
buffer calculated by Equation 5.6 is quite small. Based on Equations 5.1 and 5.2, in which
the item 𝐼max is replaced by 𝐼𝑎𝑣𝑔 , the width (𝑊) of the metal wire connecting the buffer
and the gate of the power switch need not to be very large.
In this work, for design simplification, the size of the PMOS power switch transistor
is determined as two times of the size of the NMOS power switch transistor. The layout
implementation of the PMOS power switch transistor is to connect two identical unit cells
in parallel, each of which is in the same structure as the NMOS power switch transistor.
The final layouts of the NMOS and PMOS power switch transistors with buffers are
5.2 Layout Design of the Power Switches
93
exhibited in Figure 5-11.
(a)
(b)
Figure 5-11: Final layout of the NMOS (a) and PMOS (b) power switches with buffers.
5.3 Layout Design of the Current Mirror Array
As discussed in Section 4.2, a 1𝜇𝐴 current is required for the on-time generator to
discharge the capacitor at a specific rate, and for the same purpose, a 10𝜇𝐴 current is
required for the off-time generator. As discussed in Section 4.3, since a current-mode
DAC is used to calibrate the off-time, an accurate 0.1𝜇𝐴 current is required for 1 LSB
adjustment and an accurate 0.4𝜇𝐴 current is required for 1 MSB adjustment. All these
accurate currents required in the boost converter are generated by the current mirrors
which scale up/down the 1𝜇𝐴 reference current generated by the reference current
generator. Therefore, to design current mirrors with high accuracy is a crucial mission for
this work.
The accuracy of a transistor-based current mirror can be improved by using large
transistors or increasing the overdrive voltage (𝑉𝐺𝑆 − 𝑉𝑇𝐻 ). Besides, a good layout can
guarantee the matching characteristic of a current mirror thus improving the accuracy as
well. A general layout technique for current mirrors is shown in Figure 5-12. Based on
this technique, the layout topology for the current mirrors in this work is shown in Figure
5-13. The reference branch of the current mirror which has 1𝜇𝐴 current is segmented to
ten unit cells. These unit cells are placed in the middle of the structure. The minimum
mirroring currents which are 0.1𝜇𝐴 for 1 LSB of the DAC and 0.2𝜇𝐴 for 2 LSB of the
DAC (shown in Figure 4-20) are placed close to the center at the yellow squares in Figure
94
Layout Design
5-13. The mirroring currents which are 0.4𝜇𝐴 for 1 MSB of the DAC (shown in Figure
4-21) are placed at the red squares in Figure 5-13. Because the accuracy level of the
currents used for the DAC is superior, the current mirrors to generate these currents are
placed in the center. For the currents used for the on-time generator (at the blue squares in
Figure 5-13) and the off-time generator (at the purple squares in Figure 5-13), the
accuracy is less important. The current mirrors to generate these currents can be placed
farther away from the center.
(a)
(b)
Figure 5-12: General layout techniques for current mirrors.
Figure 5-13: Layout topology for the current mirrors in this work.
The final layout of the current mirror array is shown in Figure 5-14. Besides the
current mirrors mentioned before, there are still some other additional current mirrors to
generate the bias current for the comparators in the boost converter circuit system.
Because the accuracy of the bias current is not important, these current mirrors can be
5.3 Layout Design of the Current Mirror Array
95
placed at anywhere.
Figure 5-14: General layout techniques for current mirrors.
5.4 Conclusions of the Layout Design
Since the power switch transistors play a very crucial role in a DC-DC converter circuit
system, usually transistors with very large aspect ratios and extremely wide connection
metal wires are employed in the circuit in order to not only reduce the parasitic resistance
for high efficiency but also increase the maximum current tolerance. As a consequence,
much area is consumed by these parts (power switch, connection wires and driving
buffers). The highlight of this layout design compared to other studies is that by using the
method mentioned in Section 5.2, less area is used to implement power switches but also
making the DC-DC converter with good performance.
A comparison of this design with some other outstanding low-power DC-DC
converters published during recent years is shown in Table 5-1. For the boost DC-DC
converter designed in this work, although the required maximum load current is 10𝑚𝐴
(to charge the load battery), the simulation results demonstrate that this boost converter
can also achieve an approximate 95% power conversion efficiency when it is loaded
with a 12𝑚𝐴 current. In order to evaluate these designs, we can use a figure of merit
(FOM) which is expressed by Equation 5.11.
𝐹𝑂𝑀 =
𝜂max ×𝐼load_max
𝐴
(5.11)
Although the FOM of “Saurav [3]” is close to this design, its power conversion efficiency
which is generally the most importance consideration for a DC-DC converter is relatively
96
Layout Design
low. Therefore, it can be concluded that this design is the best one.
Table 5-1: Comparison table of several low-power boost DC-DC converters
Technology
Consuming area
(𝑨)
(Power switches, metal
This work
Tzu-Chi [2]
Saurav [3]
Po-Hsiang [4]
40nm
0.25μm
45nm
0.35μm
~100 × 150
𝜇𝑚2
~450 × 550
𝜇𝑚2
~200 × 600
𝜇𝑚2
~800 × 1000
𝜇𝑚2
12mA
50mA
100mA
450mA
95%
(Post-layout)
95%
87%
95%
0.76
0.2
0.73
0.53
wires and buffers)
Max. load current
(𝑰𝐥𝐨𝐚𝐝_𝐦𝐚𝐱 )
Max. power
conversion efficiency
(𝜼𝐦𝐚𝐱 )
Figure of merit
(FOM)
Bibliography
97
Bibliography
[1] TSMC 45/40 NM CMOS LOGIC AND MS_RF DESIGN RULE (Confidential).
[2] Tzu-Chi Huang; Chun-Yu Hsieh; Yao-Yi Yang; Yu-Huei Lee; Yu-Chai Kang; Ke-Horng
Chen; Chen-Chih Huang; Ying-Hsi Lin; Ming-Wei Lee, "A Battery-Free 217 nW Static
Control Power Buck Converter for Wireless RF Energy Harvesting With 𝛼 -Calibrated
Dynamic On/Off Time and Adaptive Phase Lead Control," Solid-State Circuits, IEEE
Journal of, vol.47, no.4, pp.852,862, April 2012.
[3] Bandyopadhyay, S.; Ramadass, Y.K.; Chandrakasan, A.P., "20
A to 100 mA DC–
DC Converter With 2.8-4.2 V Battery Supply for Portable Applications in 45 nm
CMOS," Solid-State Circuits, IEEE Journal of, vol.46, no.12, pp.2807,2820, Dec.
2011.
[4] Po-Hsiang Lan; Po-Chiun Huang, "A High Efficiency FLL-Assisted Current-Controlled
DC-DC Converter Over Light-Loaded Range," Circuits and Systems I: Regular
Papers, IEEE Transactions on, vol.59, no.10, pp.2468,2476, Oct. 2012.
98
Layout Design
Chapter 6
Simulation Results
6.1 Simulation Environment
The post-layout simulation results of the boost DC-DC converter designed in this project
are presented in this chapter. Because this project missed the tape-out of our company, the
designed boost DC-DC converter was not turned into a real production although the
layout of the circuit had been implemented in TSMC 40nm CMOS process as shown in
Figure 5.2. The functionalities and performances of this boost DC-DC converter are
verified through the post-layout simulations which are made in Cadence Virtuoso.
The schematic of the test bench is shown in Figure 6-1. In here, an ideal voltage
source is used to provide the input voltage for the boost DC-DC converter. Besides, as
discussed in Section 3.5, the input voltage source is also connected to the time generators
to determine the on-time and off-time for achieving the AOOT control. The load battery
which is charged by the boost converter is modeled as a constant current source. When
the battery is charged in the fast charging mode, the current of the equivalent constant
current source is 10𝑚𝐴. When the battery is charged in the slow charging mode, the
current of the constant current source is 1𝑚𝐴. The boost DC-DC converter is composed
of an on-chip part and some off-chip parts. The on-chip part uses the extraction of the
circuit layout shown in Figure 5.2. The off-chip parts include the voltage divider, the
inductor and the load capacitor. According to the discussion in Section 3.4, the voltage
divider consists of a 200𝑓𝐹 capacitor (𝐶f ), a 600𝑘𝛺 resistor (𝑅f1 ) and a 400𝑘𝛺
resistor (𝑅f2 ). Based on the selections of the inductor and the load capacitor explained in
Section 2.3, the Spice models of the inductor “CLF7045T-1R0N” and the capacitor
“C0603JB0J223K030BC” provided by TDK Company are used in the test bench. The
values of the parameters of the inductor are shown in Figure 2-11. The values of the
parameters of the capacitor are shown in Figure 2-12. Hereby, it should be emphasized
that, as mentioned in Section 2.3, the load capacitor consists of ten separate capacitors
connected in parallel. Finally, except for the input voltage source, another two voltage
sources are used for the test. One of them is used to provide the reference voltage (𝑉ref )
for the output voltage regulation and the other one is used for the initial reset of the
100
Simulation Results
digital circuit. In order to make the simulation results closer to the real measurement
results, the connection such as bond wires or bond pads can be added to the test bench. In
this work, these parts are not taken into account. In future work, an improvement of the
test bench can be made in this respect.
Inductor
CL
Boost DC-DC Converter
L
RL1
Vin
Vmid
Vmid
Vout
Vout
RL2
On-Chip Part
LC
Cf Rf1
Vin
Vref
Vfb
Vref
Re
GND
Re
GND
Iload
RC1
Vfb
Rf2
Cload
Voltage
Divider
RC2
Load
Capacitor
Load
Battery
Figure 6-1: The schematic of the test bench.
The post-layout simulations of the boost DC-DC converter are carried out using the
test bench introduced above. The functionalities and performances of the boost DC- DC
converter will be presented in the following sections. The minimum supply voltage for
the control system and the operation of the boost converter in the startup phase will be
shown in Section 6.2. Section 6.3 will discuss the waveforms and the performance of the
boost converter which is operating in the steady state under two different load current
conditions (𝐼load = 10𝑚𝐴 or 1𝑚𝐴). The responses of the boost converter to the input
voltage or load current variations will be presented in Section 6.4.
6.2 Operation of the Converter in the Startup Phase
The startup phase mentioned here is different from what has been introduced in Section
2.1. The startup phase discussed in Section 2.1 means the phase during which the output
voltage of the boost DC-DC converter rises from zero to the steady state value. In fact,
the startup phase can be divided into two sub-phases for the boost DC-DC converter
designed in this project. In the first sub-phase, since the output voltage of the boost
converter is not high enough to provide the supply voltage for the control system, an
external mechanism is required to generate a supply voltage to power the control system
or pre-charge the load capacitor at the output of the boost converter. After the voltage of
6.2 Operation of the Converter in the Startup Phase
101
the load capacitor (the output voltage of the boost converter) reaches a sufficient value,
the boost converter enters the second startup sub-phase. In this phase, the output voltage
is used to provide the supply voltage for the control system and the output voltage will
finally rise to the steady state value. The study of the first startup sub-phase is not
included in this research. The startup phase discussed in this section just refers to the
second startup sub-phase. Therefore, in the test bench shown in Figure 6-1, the load
capacitor (𝐶load ) is given an initial voltage which is equal to the minimum voltage that
can ensure the control system operating correctly.
In most cases, the boost DC-DC converter is only applied in the steady state. Hence,
in the startup phase, the boost converter can be without any load, which means the load
current is equal to zero. In addition, the power conversion efficiency is no longer an
important consideration for the boost converter working in the startup phase. In contrast,
the minimum supply voltage for the control system is the most significant, because the
lower this value is, the easier it will be for the external startup voltage generation
mechanism such as the thermoelectric or RF energy harvesting.
In this design, the minimum voltage for the control system is about 0.7𝑉. If the load
capacitor has an initial voltage of 0.7𝑉, the boost DC-DC converter can automatically
raise its output voltage to the steady state value (1𝑉). The startup behavior of the boost
DC-DC converter designed in this research is shown in Figure 6-2. It can be seen that,
before the boost converter reaches the steady state, it operates in CCM (to be more
precise, quasi-CCM as mentioned in Section 4.2). When the boost converter reaches the
steady state, it starts to operate in DCM. The lowest value of the initial voltage is mainly
determined by the analog circuits in the control system. For example, in this design, if the
initial voltage is lower than 0.7𝑉, the overly long propagation delays of the comparators
(Section 4.5) and the unsufficient biasing current generated by the reference current
generator (Section 4.6) will cause the boost DC-DC converter to break down.
Figure 6-2: Startup phase of the boost DC-DC converter.
102
Simulation Results
6.3 Operation of the Converter in the Steady State
When the boost DC-DC converter is used to charge the load battery, it should operate in
the steady state. For the boost DC-DC converter designed in this work, it should achieve
the specifications listed in Table 1-1 (Section 1.3) when it operates in the steady state.
The post-layout simulations are carried out to verify its functionality and performance
under two load conditions (𝐼load = 10𝑚𝐴 or 1𝑚𝐴). Firstly, the post-layout simulation
results of the boost converter loaded with a 10𝑚𝐴 constant current source (𝐼load =
10𝑚𝐴) are shown.
Figure 6-3 shows the waveforms of the boost converter working in the steady state.
In here, UD is the “up/ down” signal in the Zero Current Switching (ZCS) adjustment
blocks (Figure 4-19). UD is a binary signal. When UD is low, the off-time will be
decreased in the next cycle. When UD is high, the off-time will be increased in the next
cycle. The detailed control principle has been introduced in Sections 3.6 and 4.4.
Moreover, 𝑉n and 𝑉p are the signals used to control the MOSFET power switches
(Figure 4-1). Furthermore, 𝐼L represents the inductor current and 𝑉out is the output
voltage of the boost converter. From Figure 6-3, it can be seen that, the boost converter
works without any load (𝐼load = 0) at the beginning time (< 50𝜇𝑠). When the load
current is changed to 10𝑚𝐴, the boost converter starts working in the high load condition.
After a short response time, its output voltage will be stable close to 1𝑉(988~996𝑚𝑉).
The peak value of the inductor current (𝐼L ) is about 57𝑚𝐴.
Figure 6-3: Waveforms of the boost DC-DC converter (𝐼load = 10𝑚𝐴).
Zooming in on Figure 6-3, Figure 6-4 is obtained. In here, we can see that, the
on-time is a constant value of 151.1𝑛𝑠 in each cycle and the off-time is alternatively
changed from 92.7𝑛𝑠 to 93.9𝑛𝑠 and vice versa because of the ZCS adjustment. The
ripple of the output voltage is 8𝑚𝑉 (996𝑚𝑉 − 988𝑚𝑉 = 8𝑚𝑉).
6.3 Operation of the Converter in the Steady State
103
Figure 6-4: Zoom-in waveforms of the boost DC-DC converter (𝐼load = 10𝑚𝐴).
The ZCS adjustment technique is applied in this boost converter system in order to
achieve the accurate time balance between the on-time and the off-time (see Section 3.6).
Its functionality and performance are verified by the simulation results shown in Figure
6-5. Figure 6-5 displays the waveforms of the boost converter in two adjacent cycles.
From Figure 6-5a, we can see that, by detecting the voltage 𝑉mid at the end of the
off-time, whether the off-time is overly long or overly short can be determined by the
ZCS adjustment blocks. The residual current (519𝜇𝐴) in the inductor at the end of the
off-time leads the “up/down” signal UD to the high level, which will increase the off-time
by one LSB in the next cycle. In Figure 6-5b, the off-time in the next cycle is increased
from 92.7𝑛𝑠 to 93.9𝑛𝑠 (one LSB is about 1.2𝑛𝑠) and as a result the residual current in
the inductor at the end of the next off-time is changed to -180𝜇𝐴. This leads the signal
UD staying in the low level, which will accordingly decrease the off-time by one LSB in
the following cycle. Therefore, the off-time will be toggled between these two values and
the residual current in the inductor at the end of each off-time will be controlled in the
range of -180𝜇𝐴~ 519𝜇𝐴. The ringing problem mentioned in Section 4.4 can be clearly
seen in the post-layout simulation results. This issue will reduce the accuracy of the ZCS
adjustment by one LSB. An improvement will be made in future work.
(a)
104
Simulation Results
(b)
Figure 6-5: Verification of the ZCS adjustment technique (𝐼load = 10𝑚𝐴).
Finally, the power conversion efficiency of the boost converter can be obtained from
the post-layout simulation results by using Calculator in Cadence Virtuoso. Because the
power consumptions of the reference voltage source (𝑉ref ) and the reset voltage source
(𝑅𝑒) is extremely small compared with that of the input voltage source (𝑉in ), the
calculation formula can be approximately written as:
𝜂=
∫(𝑉out ∙𝐼load )𝑑𝑡
∫(𝑉in ∙𝐼(𝑉in ))𝑑𝑡
(6.1)
in which 𝐼(𝑉in ) is the current flowing through the input voltage source (𝑉in ). The
calculation result shows that the power conversion efficiency can achieve 94.8% for the
boost DC-DC converter working with a 10𝑚𝐴 load current.
The same post-layout simulations are made for the boost DC-DC converter loaded
with a 1𝑚𝐴 constant current source (𝐼load = 1𝑚𝐴) as well. The simulation results are
displayed in the following:
Figure 6-6: Waveforms of the boost DC-DC converter (𝐼load = 1𝑚𝐴).
6.3 Operation of the Converter in the Steady State
105
Figure 6-7: Zoom-in waveforms of the boost DC-DC converter (𝐼load = 1𝑚𝐴).
(a)
(b)
Figure 6-8: Verification of the ZCS adjustment technique (𝐼load = 1𝑚𝐴).
By using Calculator in Cadence Virtuoso, we obtain that the power conversion efficiency
of the boost DC-DC working with a 1𝑚𝐴 load current can achieve 93.3%.
106
Simulation Results
6.4 Responses of the Converter to Input Voltage and Load Current Variations
For the boost DC-DC converter applied in an energy harvesting system, the input voltage
will be affected by the front-end circuit. For instance, in an RF energy harvesting system,
the variation of the input power received by the RF energy harvester (antenna and
rectifier) will change the input voltage of the boot converter. Besides, the load current of
the boost converter will often be changed according to different load conditions. As a
consequence, a well-designed boost DC-DC converter should always generate a stable
output voltage no matter what variations are encountered. In this design, the AOOT
control technique is applied to control the boost converter in order to achieve the target.
According to the explanation about AOOT control given in Section 3.4, we know that: (1)
the boost converter will adjust the on-time and the off-time based on Equation 3.13 and
3.14 in response to the input voltage variation; (2) the boost converter will change the
switching frequency by increasing or decreasing the dead-time in response to the load
current variation.
The post-layout simulation results of the responses of the boost DC-DC converter to
an input voltage variation is shown in Figure 6-9. We can see that, in this extreme
condition, when the input voltage rises from 350𝑚𝑉 to 650𝑚𝑉, the on-time is adjusted
from 163.5𝑛𝑠 to 90.1𝑛𝑠. Accordingly, the off-time is also changed. As shown in the
black ellipses in Figure 6-9, in order to achieve Zero Current Switching, the ZCS
adjustment block is fine tuning the off-time after a changing of the on-time and the
off-time. Based on the simulation results, it can be concluded that the boost DC-DC
converter designed in this research can quickly respond to an input voltage variation and
generate a very stable output voltage despite any variation of the input voltage.
Figure 6-9: Responses of the boost converter to an input voltage variation.
6.4 Responses of the Converter to Input Voltage and Load Current Variations
107
The responses of the boost DC-DC converter to a load current variation can be seen
in Figures 6-3 and 6-6. For instance, Figure 6-6 shows the responses of the boost
converter on a load current variation from 0 to 1𝑚𝐴. The on-time and the off-time are
almost maintained at the same values. Only the dead-time is decreased as the load current
is increaed. Figure 6-10 presents the responses of the boost converter when the load
current is changed from 10𝑚𝐴 to 1𝑚𝐴. According to the simulation results, a similar
conclusion can be made, that is, the boost DC-DC converter designed in this work can
quickly respond to a load current variation and generate a very stable output voltage.
Figure 6-10: Responses of the boost converter to a load current variation.
108
Simulation Results
Chapter 7
Conclusions
7.1 Summary
This thesis presents the design of a switch-mode inductor-based boost DC-DC converter
which can be applied for power management in energy harvesting systems. By using the
adaptive on-time/off-time (AOOT) control and zero current switching (ZCS) adjustment,
the proposed boost converter can generate a stable 1𝑉 output voltage and achieve very
high power conversion efficiency over wide input voltage and load current ranges. The
circuit implementation and the layout design of the on-chip part have been done in TSMC
40nm CMOS technology. With the post-layout simulation results, the functionality and
performance of the circuit system have been demonstrated to achieve the design targets.
7.2 Contributions
The main contributions of this work include:

A systematic design flow of a boost DC-DC converter has been proposed from the
initial system-level design to the final layout implementation.
Since this is the first time to design a boost DC-DC converter for energy harvesting
applications in our team at Holst Centre/imec, this work is not only to design a
circuit that can meet the specifications but also to provide a guideline for further
design of any other types of DC-DC converters in other applications. In this thesis, a
detailed design flow has been presented from (1) the design of the power plant, to (2)
the selection of the most suitable control technique, then to (3) the transistor-level
implementation and finally to (4) the layout design. Based on this flow, if the
application or requirement is changed, it will be easy to make a modification of this
boost DC-DC converter or to design a new DC-DC converter.
110

Conclusions
An advanced control method with the combination of AOOT control and ZCS
adjustment has been applied in the boost DC-DC converter to achieve high power
conversion efficiency and a stable output voltage over wide input voltage and load
current ranges.
Due to large variations of the input voltage and load current, the general PWM
control techniques are usually not suitable for the boost DC-DC converter used for
energy harvesting. A boost DC-DC converter in AOOT control can quickly respond
to an input voltage variation and achieve high power conversion efficiency over a
wide load current range. Moreover, by using the ZCS adjustment technique, the
performance of the boost DC- DC converter will be improved because of the fine
tuning of the off-time. Therefore, AOOT control with ZCS adjustment has been
demonstrated to be very appropriate for a boost DC-DC converter in energy
harvesting applications.

A novel method to implement the layout of the MOSFET power switches has been
presented which can not only save area but also reduce the parasitic resistance thus
improving the performance of the boost DC-DC converter.
In general, the power switches are the most area-consuming components in a DCDC converter except the inductor and the capacitor. As a result, the large parasitic
resistances caused by the big transistors will reduce the power conversion efficiency.
By using the structure proposed in this thesis to implement the layout of the
MOSFET power switches, much area can be saved and the power conversion
efficiency can be improved due to the reduction of the parasitic resistance.

A boost DC-DC converter with very high power conversion efficiency targeted for
energy harvesting has been designed.
The simulation results have demonstrated that the proposed boost DC-DC converter
can achieve more than 90% (maximum about 95%) power conversion efficiency
over a wide input voltage range (0.35𝑉~0.65𝑉) and a wide load current range
(1𝑚𝐴~10𝑚𝐴). In fact, according to the application requirements, after a little
modification of the circuit, this boost DC-DC converter can also fulfil the same
performance under other working conditions such as loaded with a much higher or
lower current.
Future Works
111
7.3 Future Works
Due to the time constraint, this project missed the tape-out of our company. As a result,
the designed boost DC-DC converter cannot be tested by real measurements. As a next
step, this circuit should be manufactured and assembled in a printed circuit board (PCB).
The effects of the pond wires, pond pads and some other practical factors on the
functionality and performance of the boost DC-DC converter will be tested and analyzed.
Moreover, some improvements should be made for solving the problems mentioned
in this thesis. For example, as mentioned in Section 4.4, because of the ringing occurring
on the drain of the PMOS power switch at the end of each off-time, the accuracy of the
ZCS adjustment may be degraded by one-LSB. In future, a good solution should be
worked out after doing a further analysis on the causes of this ringing. In addition, the
temperature behavior of the reference current generator should be improved in order to
generate a more stable reference current over a wider temperature range.
112
Conclusions