First Thermal Estimates for Serial Powering at
Chip/Module Level
Yadira Padilla
Joe Conway, Charlie Strohman, Jim Alexander, Anders Ryd, Julia Thom
Cornell University
Jorgen Christiansen
CERN
July 21, 2016
Outline
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Shunt and LDO power dissipation thermal issues
Chip and Dee Geometry
Assumptions and Thermal properties
Nominal Case: Operation
Max case (1.5X): Operation
Worst case (1.5X): Shut down
Summary and comments
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Shunt and LDO power dissipation thermal issues
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Shunt-LDO power dissipation
•
Nominal operation average IC current:
2 x 0.8A (analog and digital) @ 1.2v
– What if this can become 2x
• Start-up
• Mis-configuration
• SEU
Needs to inject enough current to get
system started
– What if this can become 0.
• Powering down analog FEs
• No clock to digital
All power will have to be “burned” by SLDO
•
Nominal shunt current: ~25%
– Total current ~2 x 1A
– Note: This is what allows serial power to run
with constant currents despite load variations
•
LDO minimum voltage: 0.3volt @ 1A (lower would be nice)
– Depends on current
•
Optimizing injected current (controller by external PS)
– Must assure correct function in all cases and no “melt-down”
– Can be adjusted on-line
•
Optimizing Shunt-LDO (SLDO):
– Resistance (defined by on-module resistor and possibly on-line)
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Shunt-LDO regulator
Classical shunt regulator: Inject current into
voltage “clamps”/shunts + LDO
• Problematic current sharing: Variations in
clamp voltages and parasitic resistance
• Coupling between analog and digital
supply voltage via common shunt
ATLAS outer tracker developed different
schemes to cope with this but this work is now
abandoned (decided for DC/DC power)
Resistive SLDO: Make it look like well controlled resistors
• Well defined current sharing between resistors
• Multiple “independent” shunt-LDOs per chip with
different output voltages
• Multiple chips in parallel
• Improved decoupling between analog and digital
• (Increased power losses)
How to make shunt-LDO appear resistive ?
~4 chips
per module
Optimal: Compromise between the two ?
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Thermal issues
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Pixel array: 1.7cm x 1.7cm, ~uniform analog and digital power
– Nominal operation power: 1.445W (0.7225 W digital + 0.7225 W Analog)
– Maximum: 2.023W
– Minimum power: 0W
•
0.5A shunt-LDO building block
– Shunt (NMOS): 5 transistors of 130µm x 30µm = 650um x 30um (yellow)
– LDO (PMOS): 5 transistors of 85µmx30µm = 425um x 30um (red)
– Power dissipated in thin top layer of Si (few um).
•
Shunt-LDO’s at bottom of chip
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Analog: 4 blocks of 0.5A = Max 2A
Digital: 4 blocks of 0.5A = Max 2A
Interleaved to have better heat distribution
(we may even be forced to distribute this within the pixel array in case of serious thermal
problems)
Heat removal from back side of pixel chip (initially forget about bump bonded
sensor on top)
– Initial trial with uniform heat removal across whole chip
– Cooling tube below shunt-LDOs + cooling tube middle pixel array with some kind of heat
distribution layer in-between
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Chip and Dee Geometry
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Odd Dee
Even Dee
Chip and dee geometry
Small Disc
• Each Z-layer consists of 2 Dees, one with the 1st and 3rd rings of
modules (Odd Dee) and the other with the 2nd and 4th rings
(Even Dee)
• The Dees are carbon fiber(CF) sandwich structures with CO2
cooling tubes embedded in thermally conductive foam with CF
face sheets on either side
• Pixel modules are populated on both sides of the Dee to create
a hermetic layer
• The Dees will also host the LpGBTs and other electrical
accessories in high-radius locations
Pixel
chip
HDI
Si Sensor
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Thermophysical properties
Thermal
Conductivity
[W/m-K]
Characteristic
Length [mm]
148.0
0.100
3.8
0.080
Carbon Fiber
Tencate K13C2V
620.0
0.250
Permanent Glue
3M2216
0.2
0.020
2803.0
3.500
Thermal Grease
TC5022
4.0
0.050
Tube
Stainless steel
13.8
1.025
Conductive
Thermal Pathways
ROC, Shunt, LDO
Silicon
Phase Change Glue
Laird Film
Carbon Foam
Allcomp K9
CO2 Refrigerant
Temperature = -30oC
Heat transfer coefficient = 5000 W/m2-K
Power “distribution” on chip
(Max power: 2.023W)
Nominal power: 1.445W
Min power: 0W
Pixel array
17 mm X 17mm
~19mm
Shunt-LDOs:
Worst case Max power: 6.6W
Model assumptions
• Convert conductivity for thermal grease and glues into a thermal
conductance value between contact regions so that glues and films are not
modeled as solid objects
– hLaird film = 0.0475 W/mm2-K
– h3M2216 = 0.0100 W/mm2-K
– hTC5022 = 0.0800 W/mm2-K
• Use constant heat transfer coefficient and constant temperature for CO2
• Thermophysical properties are homogenous throughout each body and not
temperature dependent
• All heat is transferred to CO2 refrigerant
• One half of a Dee ring will be analyzed
• Uniform analog and digital power
• LDO, Shunt dissipation does not change with pixel array size (same for
20mm2 and 17mm2
Nominal case: Operation
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Nominal case: operation
• Pixel array: 2 W*(172/202)=1.445 W
– Uniformly distributed over pixel array of 17x17 mm
• Analog shunt-LDO: 0.5 W
– 4 shunts each burning 0.2 W/4 = 0.05 W
– 4 LDOs each burning: 0.3 W/4 = 0.075 W
• Digital shunt-LDO: 0.5 W
– 4 shunts each burning 0.2 W/4 = 0.05 W
– 4 LDOs each burning: 0.3 W/4 = 0.075 W
• Total power per chip 2.445 W
• Thermal issues (Total power 117.36W):
1.
Temperature gradient over array less than ~5oC
• Analog front-ends quite temperature sensitive. Acceptable gradient to be
verified with circuit simulations)
2.
Hottest spot on chip (shunt-LDO) temperature
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Nominal case: results
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Location
ΔT [oC]
Quarter D
10.5
ROC Pixel area
2.5
LDO, Shunt, Periphery
3.7
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Max Temperature
-18.78oC
Min Temperature
-29.32oC
Resistance due to glues keeps heat on chip
increasing temps on chip
Temp distribution on pixel array dependent on
cooling line position
Conclusion: Hottest spot on LDO (Below 1,414oC
melting point of silicon), ΔT of pixel array about
2.5oC
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Max case (1.5x): Operation
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Max case (1.5xnominal power):
operation
• Pixel array: 2.023 W (When power-up or if mis-configured)
– Uniformly distributed over pixel array of 17x17 mm
• Analog shunt-LDO: 1.9 W
– 4 shunts each burning 0.4 W/4 = 0.1 W
– 4 LDOs each burning: 1.5 W/4 = 0.375 W
• Digital shunt-LDO: 1.9 W
– 4 shunts each burning 0.4 W/4 = 0.05 W
– 4 LDOs each burning: 1.5 W/4 = 0.375 W
• Total power 5.823 W.
• Thermal issues (Power 269.9 W):
– Pixel chip does not need to be operational but it must be guaranteed
that the chip does not “melt”
– Hottest spot on chip (shunt-LDO) temperature
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Max case (1.5xnominal power): results
2
1
Location
ΔT [oC]
Quarter D
31.0
ROC Pixel area
6.9
LDO, Shunt, Periphery
17.0
Max Temperature
2.57oC
Min Temperature
-28.43oC
• Temperatures much higher in chip due to
higher loads by the shunts and LDOs
• Resistance of glues is still an issue
• Conclusion: Hottest spot on LDO 2.6oC (Below
1,414oC melting point of silicon), ΔT of pixel
array about 2.5oC
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Worst case (1.5x): shut-down
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Worst case (1.5x): shut-down
• Pixel array: 0 W (Pixel array shut-down. Power dissipated by on-chip shunt)
– Uniformly distributed over pixel array of 17x17mm
• Analog shunt-LDO: 3.3 W
– 4 shunts each burning 1.8 W/4 = 0.45 W
– 4 LDOs each burning: 1.5 W/4 = 0.375 W
• Digital shunt-LDO: 3.3 W
– 4 shunts each burning 1.8 W/4 = 0.45 W
– 4 LDOs each burning: 1.5 W/4 = 0.375 W
• Total power 6.6 W
• Thermal issues (413.9 W):
– Hottest spots on chip (shunt or LDO) temperature
• Chip should not “melt”
• Thermal induced bending of module
• Other ?
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Worst case: results
2
1
Location
ΔT [oC]
Quarter D
44.4
ROC Pixel area
5.1
LDO, Shunt, Periphery
26.0
Max Temperature
16.77oC
Min Temperature
-27.58oC
• Temperatures much higher in chip due to
higher loads by the shunts and LDOsTemp
distribution on pixel array dependent on
cooling line position
• Conclusion: Hottest spot on LDO 16.77oC
(Below 1,414oC melting point of silicon), ΔT of
pixel array about 5.1oC
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Scenario: normal > normal X1.5 > shutdown
16.77oC
-18.78oC
Worst case
Nominal case X1.5
Failure would not cause chips to melt
Nominal case
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Glue and thermal grease effect
• Assuming worst case scenario
with heat loads
• Assuming a perfect world, no glue
or thermal resistance from
thermal grease
• Highest temperature achievable
would be 2.74oC (16.77oC if
thermal resistance due to glue
and grease) due to better
temperature distribution
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Comments and Conclusions
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Comments and pending questions
• Chips will not melt even at worst case
• Material selection key to thermal dissipation
• Resistances due to proper contact (glue and thermal
grease) key in removing heat from LDO and shunts;
still limited by properties of remaining materials
• More detailed analysis needed as chip design and
Dee materials are finalized
• Thermal analysis on chip will move to Andy Jung
([email protected]) from Purdue University, with
Cornell as secondary check
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Thank you!
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Additional slide: Thermal loads applied
Nominal
Power
Area
Heat Flux [W/mm2]
Pix array
1.44500 289.00000
0.005000000
Analog Shunts 0.05000 0.01950
2.564102564
Analog LDO 0.07500 0.01275
5.882352941
Digital Shunt 0.05000 0.01950
2.564102564
Digital LDO 0.07500 0.01275
5.882352941
Power
Area
Heat Flux [W/mm2]
Pix array
2.02300 289.00000
0.007000000
Analog Shunts 0.10000 0.01950
5.128205128
Nominal X 1.5 Analog LDO 0.37500 0.01275
29.411764706
Digital Shunt 0.05000 0.01950
2.564102564
Digital LDO 0.37500 0.01275
29.411764706
Worst case
CO2 Refrigerant
Temperature = -30oC
Heat transfer coefficient = 5000 W/m2-K
hLaird film = 0.0475 W/mm2-K
h3M2216 = 0.0100 W/mm2-K
hTC5022 = 0.0800 W/mm2-K
Power
Area
Heat Flux [W/mm2]
Pix array
0.00000 289.00000
0.000000000
Analog Shunts 0.45000 0.01950
23.076923077
Analog LDO 0.37500 0.01275
29.411764706
Digital Shunt 0.45000 0.01950
23.076923077
Digital LDO 0.37500 0.01275
29.411764706
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