Bandwidth Management in
DM816x
Version 1.1
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DM8168 Interconnect Diagram
HDVICP2
DSP 674+ SS
MDMA
Cortex-A8
M0
HDVICP3
M1
SGX530
HD
VPSS
M0 M1
PCIe
HDVICP1
Ducati
DSP CFG
EDMA
GMAC
250 MHz
0
GMAC
1
Debug SS
4 Channels
MMU
128
64
128
Security
SS
R0 W0 R1 W1 R2 W2 R3 W3
128
128
32
128
128
64
64
DAP
SATA
32
32
32
USB0/1
32
32
32
32
L3S
( 125 MHz)
32
128
L3M
(250 MHz)
64
128
x2
32
L3F ( 500 MHz)
32
32
EMIF 0/1
Probe
128
E
128
DBG
Port
128
128
128
128
32
64
T0
T1
R0 DMM R1
EDMA
EMIF0
64
64
64
32
32
32
32
32
L4 Periph
Fast
32
32
L4
Periph
Slow
Security
SS
HDVICP2
HST
OCM
RAM0
DSP
SDMA
32
OCM
RAM1
PCIe
HDVICP1
SL2
128
64
OCP-WP
128
EMIF1
HDVICP0
SL2
HDVICP2
SL2
Ducati
HDVICP1
HST
Instrumentation L3
VICP
Firewall
DMM Tiler0 Port Connection
DMM Tiler1 Port Connection
0 /1 /2 SMSET IF
HDVICP0
HST
Debug SS
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32
McASP0
GPMC
32
32
McASP2
McASP1
32
32
HDMI
32
32
USB
McBSP
L4
Firewall
L 4 config
HW Debug Sel
SGX530
32
Bandwidth Management Overview
DM816x has Cortex-A8 , HDVICPs , HDVPSS , EDMA , Ducati , DSP , USB ,
GMAC , SGX , etc as data traffic initiators.
•Above initiators transfer data to/from targets such as DDR memory, OCMC
RAM , other processors memory & peripherals.
•Each initiator have programmable
–
pressure control for interconnect.
–
priority control for EMIF
–
This would enable each initiator to get latency and/or bandwidth they
require.
•
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Pressure Control for Interconnect
Data from initiators to targets goes through shared switches.
•When Multiple Initiators are going to single target through shared switch, there will be
arbitration.
•“Pressure” determines which initiator’s request wins arbitration in interconnect switch
•
For same pressure round robin arbitration is performed.
•Interconnect supports 3 levels of pressure
– 0x0 low pressure
– 0x1 medium pressure
– 0x3 high pressure
– Note: 0x2 pressure value is illegal
–
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Pressure Control for Interconnect
•
Pressure is controlled in 3 ways:
1. Static Pressure value specified in INIT_PRESSURE_0 &
INIT_PRESSURE_1 registers for PCIe, Ducati , SATA, USB , GMAC , ARM
, EDMA ( channels 2 & 3 only )
2. Dynamic pressure values determined by Bandwidth Regulator – for
HDVICP*, SGX, DSP, EDMA ( channels 0 & 1 only )
3. Pressure value determined dynamically based on combination of HDVPSS
internal FIFO levels and Static Pressure value specified in
INIT_PRESSURE_0 for HDVPSS ( described in slide 16 )
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Static Interconnect Pressure
Settings
Registers to set Interconnect Pressure setting INIT_PRESSURE_0 &
INIT_PRESSURE_1 in control module.
Valid values for each initiator ( except HDVPSS ) are 0x0 ( low ) , 0x1 ( medium) , 0x3
(high)
HDVPSS has 2 ports on interconnect and 1 bit per port in INIT_PRESSURE_0, valid
values are 0x0 , 0x1 ( see slide 16 for details )
INIT_PRESSURE_0 : 0x4814_0608
INIT_PRESSURE_1 : 0x4814_060C
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Bandwidth Regulator
Bandwidth regulator increases pressure when the actual consumed bandwidth is
lower than expected bandwidth and decreases the pressure once the expected
bandwidth is reached.
Mechanism
A counter is incremented by number of bytes transferred ( read + write )
At each clock cycle, a quantity corresponding to expected bandwidth is subtracted from the counter.
A Watermark value for the counter is programmed.
When counter value is less than Watermark high pressure (as define by PressHigh) is applied for
minimum latency,
Else low pressure (as defined by PressLow) is applied.
Pressure = PressLow
Watermark ( in Bytes )
Pressure = PressHigh
Transfers
Counter Value
* Traffic pattern is for illustration only
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time
Configuring Bandwidth Regulator
Bandwidth : 0x08
Required Bandwidth
15.625
Watermark: 0x0C
Press: 0x10
Watermark in bytes
should be less than
4096
Press Low should be
less than Press High,
Value of “00”(low) ,
“01”(medium) , “11”
(high )
Clear History : 0x014
Write 1 after
updating bw
regulator registers
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Bandwidth Regulator Base Address
* When EDMA channel0 transaction is routed through MMU
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Example for DSP Bandwidth
Regulator programming
Intent - DSP accesses should have low latency & should not take excessive
bandwidth
•Method
–
Highest Pressure for DSP accesses by default ( for low latency )
–
Low Pressure if Bandwidth requirement goes above a limit – say 100 MB/s
–
Compute watermark over a short interval – say 200 cycles of 500 MHz
•Calculation
–
Bandwidth register => 100MB/s /15.625 = 6.4 => 7
–
Watermark register => 100 MB/s * 200 cycles * 2 ns = 40 (0X28)
–
Pressure Register => { PressLow = 0x0 ,PressHigh = 0x3 }
–
Clear History by writing 0x1 to Clear history register after writing above 3
registers.
•
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Example for HDVICP Bandwidth
Regulator programming
Intent - HDVICP should have 1GB/s bandwidth & should not take excessive
bandwidth
•Method
–
High Pressure for HDVICP accesses by default ( to ensure bandwidth)
–
Low Pressure if Bandwidth requirement goes above a limit
–
Compute watermark over approximately 1 MacroBlock interval ~1000
cycles of 500 MHz
•Calculation
–
Bandwidth register => 1000MB/s /15.625 = 64 ( 0x40 )
–
Watermark register => 1000 MB/s * 1000 cycles * 2 ns = 2000 (0X7D0)
–
Pressure Register => { PresLow = 0x0 ,PressHigh = 0x1 }
–
Clear History by writing 0x1 to Clear history register after writing above 3
registers.
•
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Priority Control in EMIF
Every initiator except HDVPSS there is a priority configuration in DMM PEG
registers
HDVPSS priority is programmed in VPDMA descriptor ( see slide 16 )
Priority is 3 bit field ( 0 ... 7 ) , 0 is highest priority
Priority determines prioritization of data transfers in EMIF
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Configuring PEG
the 3-bit priority coded on the 3 least significant bits (0 is the higher priority)
A “W” field-specific active-high local write enable bit, always read as 0
The role of the W bit is to allow the modification of a single entry without requiring a
read-modify-write sequence.
PRIOx mapping is listed on next page
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DMM PEG Registers
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EMIF Priority setting through DMM example
Set Ducati Priority of 0x1
Register DMM_PEG_PRIO1 , Field PRIO14 ( Bits 27-24 ) would be used to
change ducati priority
DMM_PEG_PRIO1 address = 0x4E00_0624
Data to be written (0b1001) << 24 = 0x0900_0000
Once Data is written , Field PRIO14 (Bits 27-24 ) would reflect value as 0b0001
Note: DMM_PEG_PRIOx registers doesn’t need read-modify-write
sequence
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HDVPSS pressure & priority
settings
HDVPSSHDVPSS VPDMA Descriptor
HDVPSS Pressure Generation
2
INIT_PRESSURE_0
Pressure[1]
Pressure[0]
1
0
Tie 0
MReqPriority[2] MReqPriority[1] MReqPriority[0]
Pressure bits Used in Interconnect arbitration
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Priority bits Used in EMIF arbitration