Embedded FPGA
for Tomorrow’s Applicaitons
May10,
10,2017
2017
May
1
The Problem/Need
Chip design taking longer
Mask costs increasing
1. Standards and customer needs keep changing
and/or
2. Chips need to be customizable
May 10, 2017
2
Why Now?
Embedded FPGA has been tried in the past
Lacked Density of FPGA chips (LUTs/sq mm)
Integration issues: metal stack, IP not silicon proven, scalability
Business: Lack of focus and/or lack of proven management
Flex Logix is focused 100% on embedded FPGA
CEO was Sr VP AMD >500 people & founding CEO Rambus
EFLX density similar to Xilinx/Altera at 28nm/16nm
SW & Silicon proven, minimum metal stack, 100 to >100K LUTs
May 10, 2017
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3
Applications for Embedded FPGA
Networking: programmable protocols
Data Center: accelerators
Machine Learning: programmable algorithms
Base Stations: reconfigurable DFE
MCU/IoT – battery life, programmable I/O, accelerators
… many more
May 10, 2017
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4
FPGA versus Embedded FPGA
Embedded FPGA should be:
- 4-6 metal to be compatible with all stacks
- Adjustable VT
- The size you need in your process node
May 10, 2017
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5
Benefits of Embedded FPGA
Eliminate SERDES (power)
Eliminate pins
High Bandwidth
Low Latency
6
May 10, 2017
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On-Chip Bandwidth
Can Increase Performance
May 10, 2017
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7
Multiple Ways to Integrate
Embedded FPGA
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Requirements for Embedded FPGA
Compatible with metal stack: IP 4-6 metal
Compatible with VT choices: IP flexible
High bandwidth: 100’s – 1000’s fast CMOS pins
High performance: ~1GHz (single stage, 16nm)
Power management
High density: similar LUTs/sq mm as Xilinx
Right size & the right features (MACs & RAM)
May 10, 2017
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9
3 Programmable Building Blocks in a
Programmable Interconnect Network
LOGIC
6-in 2-out
Look-up-table
6
6-in 2-out
Look-up-table
2
2
2
2
6
6-in 2-out
Look-up-table
2
LUT
6
6-in 2-out
Look-up-table
Carry Arithmetic
Data Mutiplexer
From Interconnect Network
LUT
LUT
2
Aux. Input
2
2
LUT
4
DSP
3
FFFF
FFFF
FFFF
FFFF
3
3
To Interconnect Network
Cout
6
I/O
Reconfigurable
Building Block
CE/Reset
Output Selection
2
3
Cin
RBB L
RBB M
RBB L
∙∙
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RBB L
DSP
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RBB M
DSP
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RBB L
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May 10, 2017
10
Software in Use at Dozens of Companies
.cpp
C/C++
.v
RTL
machine code
for processor
Compiler
Synopsys
Symplify
ARM/MIPS...
.edif Flex Logix .bit
bit file
EFLX
for EFLX
Your SoC
Compiler
EFLX
Determine resources needed  EFLX array size
Analyze worst-case timing
Generate the bit file for EFLX embedded FPGA
May 10, 2017
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11
4 Cores enable Arrays of any size
EFLX
100
Logic
EFLX
100
DSP
EFLX-100
Logic: 120 LUTs
DSP: 88 LUTs + 2DSPs
EFLX-2.5K
EFLX 2.5K
Logic
Logic: 2,520 LUTs
DSP: 1,860 LUTs + 40 DSPs
EFLX 2.5K
DSP
DSP
22b x 22b/48b MAC
Can concatenate for larger MAC
Supports complex math
May 10, 2017
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Cores tile to support any LUT count
May 10, 2017
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Arrays can mix Logic and DSP
EFLX
100
Logic
EFLX
100
Logic
EFLX
100
Logic
EFLX
100
Logic
EFLX
100
DSP
EFLX
100
Logic
EFLX
100
DSP
EFLX
100
DSP
EFLX
100
DSP
EFLX
100
Logic
EFLX
100
Logic
EFLX
100
Logic
EFLX
100
DSP
EFLX
100
Logic
EFLX
100
Logic
EFLX
100
DSP
EFLX
100
DSP
EFLX
100
DSP
EFLX
100
Logic
EFLX
100
Logic
EFLX
100
Logic
EFLX
100
Logic
EFLX
100
DSP
EFLX
100
DSP
EFLX
100
DSP
EFLX
100
DSP
EFLX
100
DSP
EFLX
100
Logic
EFLX
100
DSP
EFLX
100
Logic
In Any Shape
EFLX
100
Logic
EFLX
100
Logic
May 10, 2017
EFLX
100
Logic
EFLX
100
Logic
EFLX
100
Logic
14
RAM integration in EFLX array
Put RAM around the EFLX
array or in the EFLX array
EFLX
2.5K
EFLX
2.5K
Integrate any kind of RAM
Any width
Any size
Single or dual port
ECC, parity or neither
Room for RAM
EFLX
2.5K
May 10, 2017
EFLX
2.5K
15
Power Management by Use Case
EFLX Core
VDDH
PG
VDDL
Logic, DSP
Interconnect Switches
Configuration
Circuitry +
Bitcells
(U)HVT
SVT, HVT, or UHVT
VSS
VBP
VBN
EFLX Core
PG
VDDL
Logic, DSP
Interconnect Switches
40nm
Power-gate dynamic logic
Multiple power modes
Back biasing option
State retention at 0.5V
VDDH
Configuration
Circuitry +
Bitcells
(U)HVT
(SoC VDD)
28nm
Power-gate dynamic logic
SVT, HVT, or UHVT
16nm
Always-on applications
Use all IR drop for max performance
May 10, 2017
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Embedded FPGA IP Design Checks
100% Logic DRC
Performance simulations at all process corners
IR drop simulations for worst case switching RTL
DFT > 98% (options for >>99%)
May 10, 2017
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Customer Success
Flex Logix proves out IP in each node: 40, 28, 16
Multiple licensed customers
Two customers initiating second design already
Lead customer has fully working product silicon
Multiple customers taped out in multiple nodes
Dozens more customers in evaluation: using
EFLX Compiler to see size/speed of their RTL
May 10, 2017
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