Designing Space Cube® 2
with ELEGANT Framework
Hiroki Hihara,
NEC TOSHIBA Space Systems, Ltd.
Shuichi Moriyama, Tatsuya Takezawa,
NEC Soft.
Yuuji Nishihara,
JAXA/JEDI(JAXA's Engineering Innovation Center)
Masaharu Nomachi,
Osaka Univ.
Tadayuki Takahashi, Takeshi Takashima,
JAXA/ISAS
6th Nov. 2008
1
Introduction
 Space Cube® 2
– The first SpaceWire based satellite onboard system
controller in Japan
– The first real application of ELEGANT framework
(ELEGANT: Electric Design Guidance Tool for Space Use)
Flight model
6th Nov. 2008
Software Development Platform
2
ELEGANT Environment
 Electronic Design Guidance Tool for
Space Use (ELEGANT)
– Embedded HW/SW system design
– Focus on correctness and reliability
 Tool set for Modeling, Simulation, Synthesis and Verification
– Model generation, High-level synthesis for productivity and
flexibility
– Rapid prototyping, performance evaluation and functional
validation
 Joint R&D project with JAXA, Universities and Industries
– Joint development under JAXA leadership
– Developed by InterDesign Technologies, NEC, Fujitsu,
The University of Tokyo, University of California at Irvine
– VisualSpec and SER are sold by InterDesign Technologies
– CyberWorkBench is available from NEC System Technologies
6th Nov. 2008
3
ELEGANT Tool Set
 Seamless tool chain from top-level specification
to RTL (HDL)
– Integrated tools based on common SpecC framework
Specification
Specification model
model
VisualSpec
SER
Venus
Specification model
simulation
CECS
Fujitsu
Formal verification
InterDesign Technologies
TLM
Co-simulation
Exploration
and
Refinement
TLM
TLM
PE
PE // CE
CE // Bus
Bus
database
database
CyberWorkBench
NEC
Software synthesis
High-level
synthesis
Cycle-accurate
Co-simulation
Software
Software
source
source code
code
Hardware
Hardware RTL
RTL
ELEGANT : Electronic Design Guidance Tool for Space Use
6th Nov. 2008
4
Assertion/Property
checking
Design written in SpecC
(ex) RMAP implementation
• Sequential process with Software is
converted in parallel description in SpecC
Main
Receive
Data
CRC
check
Read/Write
Memory
CRC
generation
Main
Transmit
Data
CRC check
6th Nov. 2008
Receive
Data
Read/Write
Memory
5
void main(void)
{
par{
rmap_rx.main();
rmap_host.main();
tx_control.main();
crcchk.main();
crcgen.main();
}
}
Transmit
Data
CRC
generation
Partitioning Trial (1)
 Design Process
GBUS
– A behavior is divided into
several Hardware/Software
partitioning
– Software processing time and
hardware footprint are
evaluated for each behavior
A
B
C
SW
HW
HW
: Behavior
HW / SW partitioning
Receive
Data
Read/Write
Memory
Transmit
Data
CRC check
CRC
generation
Pattern 1
SW
HW
HW
HW
HW
Pattern 2
HW
SW
HW
HW
HW
Pattern 3
HW
HW
SW
HW
HW
Pattern 4
HW
HW
HW
SW
HW
Pattern 5
HW
HW
HW
HW
SW
6th Nov. 2008
6
Partitioning Trial (2)
 Performance evaluation
– Software processing cycle evaluation with simulator
– Hardware footprint evaluation with behavioral synthesis
Read CMD
result
Processing
Cycle
Write CMD
result
5923
+6636
+6762
=19321
Read/Modify/Write
CMD result
JAXA ELEGANT
FPGA
(NEC Cyber) Synthesis Tool
behavior Main(void)
{
signal unsigned bit[1] a;
c_double_handshake b;
void main(void)
{
par{
dut.main();
spwip_get.main();
}
}
}
6th Nov. 2008
SpecC
(A)
Verilog
BDL
(B)
7
or
VHDL
(C)
FPGA
program
data
SpaceCube
Partitioning Trial (3)
 Hardware / Software partitioning trial result
Validation
Pattern
Behaviors
Pattern 1
Receive Data
Pattern 2
Read/Write
Memory
Pattern 3
Transmit Data
Pattern 4
CRC check
Pattern 5
CRC generation
Software processing
cycle
Hardware footprint
FPGA Logic
ElementNumber
5,394
Small
2,428
Small
19,321
Medium
3,128
Medium
Large
3,761
Medium
16,689
Medium
4,507
Large
674,255
Large
4,452
Large
1,022,650
– Software processing cycle in Pattern 1 is small
– Hardware footprint in Pattern 1 is small
Quantitative result for all partitioning model
6th Nov. 2008
8
Tradeoff
★
ELEGANT Status
 ELEGANT development history and future plan
2004FY
ELEGANT（phase1）
Design
2005FY
Development
2006FY
2007FY
2008 & after
Test
ELEGANT （phase2）
New DB component models
Evaluation result upgrades
Requests
New project (plan)
Requests
Model-based design (Matlab)
Software synthesis
Third-party evaluations
NEC Toshiba Space Systems
Mitsubishi Space
2
Public Seminar
General marketing
6th Nov. 2008
5
Preview
（SpaceWire）
Satellite design,
production use
Survey
Image compression、
etc..
Public Seminar
SIG-ELEGANT
9
Summary
 SpaceWire is suitable for top-down design
– SpaceWire is realized in digital implementation, it is
one of the most suitable application for system level
verification and validation as well as behaviour
synthesis.
 Rapid, early design space exploration
– Fast and accurate models at varying levels for virtual
prototyping are explored by ELEGANT.
– Reasons for H/W and S/W partitioning
can be traced.
 Fast realization
– Prompt hardware and software
realization with algorithm development
6th Nov. 2008
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