Compute Node
Tutorial(2)
22.07.2010
Agenda
Introduce to RocketIO
 How to build a optical link connection
 Backplane and cross link communications
 How to boot up compute node
 A demo system from optical link to ddr2
memory

Introduce to RocketIO
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A high serial IO technology introduced by Xilinx for
multiple Gigabit application
SERDES solution in FPGAs
8b/10b coding
256(out of 1024) used for data encoding, 12 used for Kcharacters
MGT module

Tx data path

Rx data path
Relative issues
Rx/Tx signal polarity
 Byte boundary checking
 Bytes arrangement in data
 Clock correction
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Clock correction
Optical link demo
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Random data is generated by TRB board and
received by compute node
Data pattern
 prbs<=(prbs
(14 downto 0)&(prbs (0) xor prbs (5) xor
prbs (10) xor prbs (15)))
 2Gbps, 16bit in user interface
 3 data+1align code
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Used for bit error rate measurement (long term
stability)
Results are checked with ChipScope
ChipScope
A way to view signals inside FPGA (using
unused memory resources)
 Two way to use ChipScope

 Implement
a ChipScope ipcore in design
 Insert probe signals into netlist file but without
change the design

Logic slot and
physical slot
J2.0
J2.1
J2.2
J2.3
J2.4
P1.0
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Backplane connectors
Cross link and backplane connections
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Pre-emphasis
 To
compensate the high frequency part of
original signals
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Differential swing
 To
compensate the line lose
Connections on front
panel
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Configuration St.
LED
UART
 care
Power St. LED
about the cable
Optical link
 about
the labels
Gigabit Ethernet
 JTAG

 use
Gigabit Ethernet
Optical Links
pin connectors
UART port
JTAG
How to boot up compute node
Start up Linux file server
 Start a Hyper Terminal
connection(9600,8bit, no parity, 1 stop bit,
no Flow control)
 Power up ATCA shelf
 Press RST_CPLD button (current situation)
 All Power LEDs St. ok? All FPGA
configuration St. LEDs turn to green? HT
message comes?

Boot up sequence
Linux system demo
Stdin, stdout
 Flash read and write (expert mode)
 User program

How to program an FPGA on CN

Devices in JTAG chain
 CPLD->FPGA0->FPGA1->…->FPGA4
Configure the unused FPGA with a demo
bit file (uart_top.bit)
 Download user bit file to dedicate FPGAs

From optical link to DDR memory
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Data pattern
 D[i+1]=D[i]+1

512KByte per interrupt, 100 interrupt per data
check
Data check is completed by a c program running
on PPC
Data Generator
O/E
MGT1
FIFO
O/E
MGT0
FPGA
FIFO
Master
PLB
PPC
MPMC
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Compute Node
Questions?