Computer Architecture I: Digital Design
Dr. Robert D. Kent
Logic Design
Medium Scale Integration and
Programmable Logic Devices
Part I
Review
• We have studied and developed several techniques for simplifying
Boolean expressions.
• These are based on the axioms, definitions and theorems of the
Boolean Algebra, applied through the Boolean Calculus.
• Powerful tabular techniques have been developed for rapid
reduction to some minimal cost forms (ie. Karnaugh maps)
• Now it is time to apply our knowledge and understanding to
practical problems, eventually leading us to an understanding of
the design issues and approaches in modern computer and network
engineering.
Goals
• At the outset of designing a complex system, such as a modern
computer or network, it is clear that design is extraordinarily
difficult and computationally challenging when performed at the
level of fundamental Boolean logic gates.
• For these reasons modern design approaches are based on
hierarchical, component based methods.
– Leading to simplified, localized component design,
– lowering of design costs,
– shifting some aspects of design to the component interface (the
compatibility problem).
• We will now begin to study logic design in the contexts of Medium
Scale Integration (MSI) of gate devices and programmable logic
devices (PLD).
Goals
• We begin our study with simple, but functional circuits
– we will construct a small library of useful components
– we will seek to identify these components for their re-use potential
Goals
• We begin our study with simple, but functional circuits
– we will construct a small library of useful components
– we will seek to identify these components for their re-use potential
• At this stage we will have shifted our understanding from a model
based on small-scale integrated circuits (SSI) to a different model
based on medium-scale integrated circuits (MSI)
Goals
• We begin our study with simple, but functional circuits
– we will construct a small library of useful components
– we will seek to identify these components for their re-use potential
• At this stage we will have shifted our understanding from a model
based on small-scale integrated circuits (SSI) to a different model
based on medium-scale integrated circuits (MSI)
• We must consider two distinct types of MSI circuits
– Combinational circuits
– Sequential circuits
• We continue now with a study of Combinational circuits.
Circuit # 1 : Half-Adder
Circuit # 1 : Half-Adder
• We begin by designing a circuit that will perform numeric (integer)
addition of two input values.
Circuit # 1 : Half-Adder
• We begin by designing a circuit that will perform numeric (integer)
addition of two input values.
• Assume that A and B each represent a single data bit, with possible
numeric values 0 and 1.
Circuit # 1 : Half-Adder
• We begin by designing a circuit that will perform numeric (integer)
addition of two input values.
• Assume that A and B each represent a single data bit, with possible
numeric values 0 and 1.
• The problem is to design a circuit that is able to model the addition
operation:
– Assume two inputs, A and B,
C
+
A
B
S
Circuit # 1 : Half-Adder
• We begin by designing a circuit that will perform numeric (integer)
addition of two input values.
• Assume that A and B each represent a single data bit, with possible
numeric values 0 and 1.
• The problem is to design a circuit that is able to model the addition
operation:
– Assume two inputs, A and B,
– Output:
• a sum bit, S,
C
+
A
B
S
Circuit # 1 : Half-Adder
• We begin by designing a circuit that will perform numeric (integer)
addition of two input values.
• Assume that A and B each represent a single data bit, with possible
numeric values 0 and 1.
• The problem is to design a circuit that is able to model the addition
operation:
– Assume two inputs, A and B,
– Output:
• a sum bit, S,
• and, a carry bit, C.
C
+
A
B
S
Circuit # 1 : Half-Adder
• We begin by designing a circuit that will perform numeric (integer)
addition of two input values.
• Assume that A and B each represent a single data bit, with possible
numeric values 0 and 1.
• The problem is to design a circuit that is able to model the addition
operation:
– Assume two inputs, A and B,
– Output:
• a sum bit, S,
• and, a carry bit, C.
C
A
B
+
S
HA
C
A
B
S
Circuit # 1 : Half-Adder
• We begin the design by constructing a 2-input/2-output truth table
A
0
B
0
S
0
C
0
0 + 0 = 0
(no carry)
Circuit # 1 : Half-Adder
• We begin the design by constructing a 2-input/2-output truth table
A
0
0
B
0
1
S
0
1
C
0
0
0 + 1 = 1
(no carry)
Circuit # 1 : Half-Adder
• We begin the design by constructing a 2-input/2-output truth table
A
0
0
1
B
0
1
0
S
0
1
1
C
0
0
0
1 + 0 = 1
(no carry)
Circuit # 1 : Half-Adder
• We begin the design by constructing a 2-input/2-output truth table
A
0
0
1
1
B
0
1
0
1
S
0
1
1
0
C
0
0
0
1
1 + 1 = 0 (with a carry = 1)
Circuit # 1 : Half-Adder
• We begin the design by constructing a 2-input/2-output truth table
A
0
0
1
1
B
0
1
0
1
S
0
1
1
0
C
0
0
0
1
• We derive the following expressions for the S and C circuits:
Use algebra for
simple cases with
only a few variables.
Circuit # 1 : Half-Adder
• We begin the design by constructing a 2-input/2-output truth table
A
0
0
1
1
B
0
1
0
1
S
0
1
1
0
C
0
0
0
1
• We derive the following expressions for the S and C circuits:
S = A’B + AB’
Circuit # 1 : Half-Adder
• We begin the design by constructing a 2-input/2-output truth table
A
0
0
1
1
B
0
1
0
1
S
0
1
1
0
C
0
0
0
1
• We derive the following expressions for the S and C circuits:
S = A’B + AB’ = A xor B
Circuit # 1 : Half-Adder
• We begin the design by constructing a 2-input/2-output truth table
A
0
0
1
1
B
0
1
0
1
S
0
1
1
0
C
0
0
0
1
• We derive the following expressions for the S and C circuits:
S = A’B + AB’ = A xor B
C = AB
Circuit # 1 : Half-Adder
• We begin the design by constructing a 2-input/2-output truth table
A
0
0
1
1
B
0
1
0
1
S
0
1
1
0
C
0
0
0
1
• We derive the following expressions for the S and C circuits:
S = A’B + AB’ = A xor B
C = AB
• This circuit is called a Half-Adder.
Circuit # 1 : Half-Adder
• Using the S and C circuit expressions for the Half-Adder circuit:
S = A’B + AB’ = A xor B
A
B
C = AB
S
HA
C
we can represent the circuit schematically in terms of gate logics.
Circuit # 1 : Half-Adder
• Using the S and C circuit expressions for the Half-Adder circuit:
S = A’B + AB’ = A xor B
A
B
C = AB
S
HA
C
we can represent the circuit schematically in terms of gate logics.
Half-Adder
AND/OR logic
A
HA
S
B
C
Circuit # 1 : Half-Adder
• Using the S and C circuit expressions for the Half-Adder circuit:
S = A’B + AB’ = A r B
A
B
S
HA
C = AB
C
we can represent the circuit schematically in terms of gate logics.
Half-Adder
AND/XOR logic
Half-Adder
AND/OR logic
A
HA
A
HA
S
B
S
B
C
C
Circuit # 2 : Full-Adder
Circuit # 2 : Full-Adder
• The problem is to design a circuit, called a Full-Adder, that is able
to model the addition operation, assuming:
– three inputs:
A, B and Cin ,
– and two outputs: a sum bit, S, and a carry bit, Cout .
Circuit # 2 : Full-Adder
• The problem is to design a circuit, called a Full-Adder, that is able
to model the addition operation, assuming:
– three inputs:
A, B and Cin ,
– and two outputs: a sum bit, S, and a carry bit, Cout .
• Assume that A, B and Cin each represent a single data bit, with
possible numeric values 0 and 1. The input Cin corresponds to a
carry bit generated from prior bit additions.
Circuit # 2 : Full-Adder
• The problem is to design a circuit, called a Full-Adder, that is able
to model the addition operation, assuming:
– three inputs:
A, B and Cin ,
– and two outputs: a sum bit, S, and a carry bit, Cout .
• Assume that A, B and Cin each represent a single data bit, with
possible numeric values 0 and 1. The input Cin corresponds to a
carry bit generated from prior bit additions.
• We will eventually generalize the variables
– Inputs:
AK , BK and CK
Outputs:
SK and CK+1
Circuit # 2 : Full-Adder
• We begin the design by constructing a 3-input/2-output truth table:
Cin
A
B
S
Cout
Circuit # 2 : Full-Adder
• We begin the design by constructing a 3-input/2-output truth table:
Cin
0
0
0
0
A
0
0
1
1
B
0
1
0
1
S
0
1
1
0
Cout
0
0
0
1
Circuit # 2 : Full-Adder
• We begin the design by constructing a 3-input/2-output truth table:
Cin
0
0
0
0
1
1
1
1
A
0
0
1
1
0
0
1
1
B
0
1
0
1
0
1
0
1
S
0
1
1
0
1
0
0
1
Cout
0
0
0
1
0
1
1
1
Circuit # 2 : Full-Adder
• We begin the design by constructing a 3-input/2-output truth table:
Cin
0
0
0
0
1
1
1
1
A
0
0
1
1
0
0
1
1
B
0
1
0
1
0
1
0
1
S
0
1
1
0
1
0
0
1
Cout
0
0
0
1
0
1
1
1
• This leads to the expressions:
S = Cin’A’B + Cin’AB’ + CinAB + CinA’B’
Circuit # 2 : Full-Adder
• We begin the design by constructing a 3-input/2-output truth table:
Cin
0
0
0
0
1
1
1
1
A
0
0
1
1
0
0
1
1
B
0
1
0
1
0
1
0
1
S
0
1
1
0
1
0
0
1
Cout
0
0
0
1
0
1
1
1
• This leads to the expressions:
S = Cin’A’B + Cin’AB’ + CinAB + CinA’B’
Cout = CinAB + Cin’AB + CinA’B + CinAB’
Circuit # 2 : Full-Adder
• We begin the design by constructing a 3-input/2-output truth table:
Cin
0
0
0
0
1
1
1
1
A
0
0
1
1
0
0
1
1
B
0
1
0
1
0
1
0
1
S
0
1
1
0
1
0
0
1
Cout
0
0
0
1
0
1
1
1
Cin
A
FA
B
• This leads to the expressions:
S = Cin’A’B + Cin’AB’ + CinAB + CinA’B’
Cout = CinAB + Cin’AB + CinA’B + CinAB’
S
Cin
Circuit # 2 : Full-Adder
• Proceeding from the expressions:
S = Cin’A’B + Cin’AB’ + CinAB + CinA’B’
Cout = Cout = CinAB + Cin’AB + CinA’B + CinAB’
and recalling that x’y+xy’ = x xor y, we derive the alternative
expressions:
Circuit # 2 : Full-Adder
• Proceeding from the expressions:
S = Cin’A’B + Cin’AB’ + CinAB + CinA’B’
Cout = AB + CinA’B + CinAB’
and recalling that x’y+xy’ = x xor y, we derive the alternative
expressions:
S
=
Cin’ (A xor B) + Cin (A xor B)’
Circuit # 2 : Full-Adder
• Proceeding from the expressions:
S = Cin’A’B + Cin’AB’ + CinAB + CinA’B’
Cout = AB + CinA’B + CinAB’
and recalling that x’y+xy’ = x r y, we derive the alternative
expressions:
S
=
Cin’ (A xor B) + Cin (A xor B)’
=
Cin xor
A xor B
Circuit # 2 : Full-Adder
• Proceeding from the expressions:
S = Cin’A’B + Cin’AB’ + CinAB + CinA’B’
Cout = AB + CinA’B + CinAB’
and recalling that x’y+xy’ = x r y, we derive the alternative
expressions:
S
=
=
Cin’ (A xor B) + Cin (A xor B)’
Cin xor
A xor B
Cout = CinAB + Cin’AB + CinA’B + CinAB’
Circuit # 2 : Full-Adder
• Proceeding from the expressions:
S = Cin’A’B + Cin’AB’ + CinAB + CinA’B’
Cout = AB + CinA’B + CinAB’
and recalling that x’y+xy’ = x r y, we derive the alternative
expressions:
S
=
=
Cin’ (A xor B) + Cin (A xor B)’
Cin xor
A xor B
Cout = CinAB + Cin’AB + CinA’B + CinAB’
= (Cin + Cin’)AB + Cin(A+A’)B + CinA(B+B’)
Circuit # 2 : Full-Adder
• Proceeding from the expressions:
S = Cin’A’B + Cin’AB’ + CinAB + CinA’B’
Cout = AB + CinA’B + CinAB’
and recalling that x’y+xy’ = x r y, we derive the alternative
expressions:
S
=
=
Cin’ (A xor B) + Cin (A xor B)’
Cin xor
A xor B
Cout = CinAB + Cin’AB + CinA’B + CinAB’
= (Cin + Cin’)AB + Cin(A+A’)B + CinA(B+B’)
= AB + CinB + CinA
Circuit # 2 : Full-Adder
• The representation of the Full-Adder circuit using gate logics is:
S =
Cin xor
Cin
A
B
FA
S
Cout
A xor B
Cout
= AB + CinB + CinA
Circuit # 2 : Full-Adder
• The representation of the Full-Adder circuit using gate logics is:
S =
Cin xor
A xor B
Cout
= AB + CinB + CinA
Binary Full Adder
FA
Cin
A
B
FA
S
Cout
Cin
A
B
S
Cout
Circuit # 2 : Full-Adder
• Adapting the notation to a general set of input and output bits:
SK =
CK xor
AK xor BK
CK = AKBK + CKBK + CKAK
Binary Full Adder
FA
CK
AK
BK
FA
SK
CK+1
CK
AK
BK
SK
CK+1
Circuit # 3 : Multi-bit Adder
Circuit # 3 : Multi-bit Adder
• We may now use the previous results to construct a circuit to
perform addition of two multi-bit inputs, A and B.
Circuit # 3 : Multi-bit Adder
• We may now use the previous results to construct a circuit to
perform addition of two multi-bit inputs, A and B.
– Inputs: A = {A3 , A2, A1, A0} and B = { B3, B2, B1, B0 }
Restrict attention to the 4-bit case (easy to generalize to N-bits).
Circuit # 3 : Multi-bit Adder
• We may now use the previous results to construct a circuit to
perform addition of two multi-bit inputs, A and B.
– Inputs: A = {A3 , A2, A1, A0} and B = { B3, B2, B1, B0 }
Cout C3 C2 C1
A3 A2 A1 A0
+
B3 B2 B1 B0
S3 S2 S1 S0
Circuit # 3 : Multi-bit Adder
• We may now use the previous results to construct a circuit to
perform addition of two multi-bit inputs, A and B.
– Inputs: A = {A3 , A2, A1, A0} and B = { B3, B2, B1, B0 }
Cout C3 C2 C1
A3 A2 A1 A0
+
B3 B2 B1 B0
S3 S2 S1 S0
– Outputs: S = { S3, S2, S1, S0 } and Cout.
Circuit # 3 : Multi-bit Adder
• We may now use the previous results to construct a circuit to
perform addition of two multi-bit inputs, A and B.
– Inputs: A = {A3 , A2, A1, A0} and B = { B3, B2, B1, B0 }
Cout C3 C2 C1
A3 A2 A1 A0
+
B3 B2 B1 B0
S3 S2 S1 S0
– Outputs: S = { S3, S2, S1, S0 } and Cout.
Circuit # 3 : Multi-bit Adder
• We may now use the previous results to construct a circuit to
perform addition of two multi-bit inputs, A and B.
– Inputs: A = {A3 , A2, A1, A0} and B = { B3, B2, B1, B0 }
Cout C3 C2 C1
+
A3 A2 A1 A0
A
B3 B2 B1 B0
B
S3 S2 S1 S0
S
HA
C
There is no
initial Carry bit.
– Outputs: S = { S3, S2, S1, S0 } and Cout.
Circuit # 3 : Multi-bit Adder
• We may now use the previous results to construct a circuit to
perform addition of two multi-bit inputs, A and B.
– Inputs: A = {A3 , A2, A1, A0} and B = { B3, B2, B1, B0 }
Cout C3 C2 C1
A3 A2 A1 A0
+
B3 B2 B1 B0
S3 S2 S1 S0
– Outputs: S = { S3, S2, S1, S0 } and Cout.
Circuit # 3 : Multi-bit Adder
• We may now use the previous results to construct a circuit to
perform addition of two multi-bit inputs, A and B.
– Inputs: A = {A3 , A2, A1, A0} and B = { B3, B2, B1, B0 }
Cout C3 C2 C1
CK
AK
BK
FA
A3 A2 A1 A0
SK
CK+1
+
B3 B2 B1 B0
S3 S2 S1 S0
– Outputs: S = { S3, S2, S1, S0 } and Cout.
Circuit # 3 : Multi-bit Adder
• We may now use the previous results to construct a circuit to
perform addition of two multi-bit inputs, A and B.
– Inputs: A = {A3 , A2, A1, A0} and B = { B3, B2, B1, B0 }
Cout C3 C2 C1
CK
AK
BK
FA
SK
CK+1
+
A3 A2 A1 A0
A
B3 B2 B1 B0
B
S3 S2 S1 S0
– Outputs: S = { S3, S2, S1, S0 } and Cout.
S
HA
C
Circuit # 3 : Multi-bit Adder
• Applying our previously determined HA and FA circuits:
CK
AK
Cout C3 C2 C1
SK
FA
A3 A2 A1 A0
CK+1
BK
+
B3 B2 B1 B0
S3 S2 S1 S0
B3 B2 B1 B0
A3 A2 A1 A0
4-bit Binary Adder
Cout
S3
S2
S1
S0
A
B
S
HA
C
Circuit # 3 : Multi-bit Adder
• Applying our previously determined HA and FA circuits:
CK
AK
Cout C3 C2 C1
SK
FA
A3 A2 A1 A0
CK+1
BK
A
+
B
S
HA
B3 B2 B1 B0
C
S3 S2 S1 S0
B3 B2 B1 B0
B3 B2 B1 B0
A3 A2 A1 A0
A3 A2 A1 A0
4-bit Binary Adder
FA
FA
FA
S2
S1
HA
Cout
Cout
S3
S2
S1
S0
S3
S0
Summary - Part I
• We have begun to study logic design in the contexts of Medium
Scale Integration (MSI) of gate devices and programmable logic
devices (PLD).
• We have studied the design of a number of specific, practical
functional circuits, expressed in terms of Boolean expressions and
their equivalent logic gates (SSI: Small Scale Integration) with a
view to re-using those circuits as components in MSI design.
– 1-bit Half-Adder
– 1-bit Full-Adder
– Multi-bit Ripple Adder