Xilinx 9500/9500XL
CPLD Testing CNGS 2009
TE/MPE/MI
Radiation Working Group
18th September 2009
B.Todd, M. Zerlauth, I. Romera, A. Castaneda
0v4
CPLDs Used in the Interlock Systems
Beam Interlock System
(5V)
500nm
XC95288 x 300
UA, UJ, RR
(3.3V) 350nm
XC95288XL x 34
UA, SR
Power Interlock Controllers
(5V)
500nm
XC95144 x 36
UA, UJ, RR
95288/144 failure = maintenance required = not machine critical
95288XL failure = can compromise safety
N.B. Whole BIS is redundant = needs two identical failures during a mission
95288XL in VME chassis
TE/MPE/MI has installed a Radiation Test Bench in CNGS
XC95144 x 32
Almost = # in LHC
XC95288XL x 32
[email protected]
CPLDs Used in the Interlock Systems
Beam Interlock System
(5V)
500nm
XC95288 x 300
UA, UJ, RR
(3.3V) 350nm
XC95288XL x 34
UA, SR
Power Interlock Controllers
(5V)
500nm
XC95144 x 36
UA, UJ, RR
95288 failure = maintenance required = not machine critical
95288XL failure = compromises safety
N.B. Whole BIS is redundant = needs two identical failures during a mission
95288XL in VME chassis
TE/MPE/MI has installed a Radiation Test Bench in CNGS
XC95144 x 32
Almost = # in LHC
XC95288XL x 32
[email protected]
Results
Without adjustment of values from monkey program!
Daniel - you should adjust for your factor!
XC95288XL - 3.3V - 350nm
4 x 1012 >20MeV Hadrons per cm2
9972 Single Event Effects observed in all devices
80% = FALSE DUMP
1 device = 1 cm2
20% LOSS OF REDUNDANCY
8 x 10-11 Glitches per device, per >20MeV Hadron
79 Grays Total Dose still OK
XC95144 - 5V - 500nm
8 x 1011 >20MeV Hadrons per cm2
9 Single Event Effects observed in all devices
11% = FALSE DUMP
88% INCONSISTENT MONITOR
3 x 10-13 Glitches per device, per >20MeV Hadron
77 Grays Total Dose then 1 oo 4 boards developed short-circuit
[email protected]
Impact for TE/MPE/MI
Power Interlock Controllers
XC95144 x 36
This is not a critical part, it works in parallel to the Programmable Logic Controller (move
already prepared away from UJ56, UJ14 and UJ16)
Beam Interlock System
XC95288 x 300
not a critical part, it provides monitor data to the Beam Interlock Controller
XC95288XL x 34
Needs two to be effected simultaneously to be critical, even so:
requested move away from UJ56 (DIF/DIC)
TZ76/UA63/UA67 now shielded
BIC will not be in a ‘critical’ area
77 Gy = many 10’s of years of LHC operation
Working on contingencies – shorter turn around to replace affected HW
[email protected]
In reality…
XC9500XL - 3.3V - 350nm
assume Cross-Section 1 x 10-10 Per >20 MeV Hadron
assume UA = 1 x 107 >20 MeV Hadrons per year (0.01 Gy/y)
For all (34) devices, MTBSEU ≈ 30 years
≈ once in LHC lifetime, FALSE BEAM DUMP
≈ 10% chance in LHC lifetime that REDUNDANCY is LOST for one mission
Same order of magnitude as ‘normal’ electrical failure of CPLD (Xilinx Documents)
XC9500 - 5V - 500nm
assume Cross-Section 1 x 10-12 Per >20 MeV Hadron
assume RR = 1 x 109 >20 MeV Hadrons per year (1 Gy/y)
For all (336) devices, MTBSEU ≈ 3 years
≈ 6-7 INCONSISTENT MONITOR DATA READINGS in LHC lifetime (BIS+PIC),
≈ 10% chance of FALSE DUMP in LHC lifetime (PIC),
Same order of magnitude as ‘normal’ electrical failure of CPLD (Xilinx Documents)
[email protected]
Prior to movements this year…
CIBU : User Interface Locations
IR1
IR2
IR3
IR4
IR5
IR6
IR7
IR8
other
SR1
SR2
SR3
SR4
SR5
SR6
SR7
UA83
CCR
US151
UA23
UJ33
UA43
UJ56
UA63
UJ76
UA87
USA151
UA27
UA47
USC55
UA67
TZ76
UX85
USA152
SX4
RR53
US65
RR73
US851
RR13
CR4
RR57
US651
RR77
RR17
US451
UJ14
UJ16
“critical areas”
BIC : Beam Interlock Controller Locations
IR1
IR2
IR3
IR4
IR5
US15
IR6
IR7
IR8
other
CCC
SR2
SR3
UA43
UJ56
UA63
SR7
SR8
UA23
UJ33
UA47
UCS55
UA67
TZ76
UA83
UA27
UA87
[email protected]
Prior to movements this year…
PIC : Powering Interlock Controller – PLC Locations
IR1
IR2
IR3
IR4
IR5
IR6
UJ14
UA23
UJ16
UA27
UJ33
UA43
UJ56
UA63
UA47
UCS55
UA67
PIC : Powering Interlock Controller – XC95144 Locations
IR1
IR2
IR3
IR4
IR5
IR6
RR13
UA23
UJ14
UA27
UJ33
IR7
IR8
TZ76
UA83
UA87
IR7
IR8
UA43
RR53
UA63
RR73
UA83
UA47
UJ56
UA67
RR77
UA87
UJ16
UCS55
RR17
RR57
“critical areas”
[email protected]
FIN
[email protected]