邏輯電路設計 (電機一 A)
1.
第三次單元考
Consider the given network shown in Fig. 1.
(a) Construct a state table and graph. (15%)
(b) Let the clock be triggered with falling edge, and
assume that X changes midway between clock
pulses. Construct a timing chart (including
the waveforms of Clock, X, Q1 , Q2 and Z) for
the network for an input sequence X = 10011.
Initially, Q1  Q2  0 . (10%)
2.
89,6,7
Fig. 1
A Mealy sequential network has 1 input, 1 output, and 2 flip-flops. A timing chart for the network
follows (Fig. 2). Construct a state table and state graph for the network. (12%)
Fig. 2
3.
Construct a state graph for the shifter
register shown in Fig. 3. (X is the
input and Z is the output.) (10%)
4.
Design a Moore sequential network
as a sequence detector so that the
output Z should be 1 if the input
Fig. 3
sequence ends in 110, and Z should
be 0 otherwise.
(a) Derive the Moore State Graph for the sequence detector. (8%)
(b) Design the Moore sequential network using T flip-flops. (15%)
5.
Design a Mealy sequential network as a sequence detector so that the output Z should be 1 if the input
sequence ends in either 010 or 1001, and Z should be 0 otherwise.
(a) Derive the Mealy State Graph for the sequence detector. (12%)
(b) Design the Mealy sequential network using D flip-flops. (18%)
2. （參考波形）