TECHDAYS
15-16-17 September 2016, Aveiro
A Time Synchronization MAC Protocol
for Low Power Wearable Systems
Fardin Derogarian
João Canas Ferreira
Vítor Grade Tavares
Jose Machado da Silva
Fernando J. Velez
© 2014, it - instituto de telecomunicações. Todos os direitos reservados.
Outline
•
•
•
•
•
•
Introduction
Motivation
Synchronization method
Protocol Implementation
Experimental results
Conclusion
Nome da conferência ou subtítulo da apresentação
2 | Data e local da apresentação
Introduction
• Time synchronization is essential part of any distributed data
acquisition system such as sensor network and BANs
•
•
•
The main challenge
•
Overcome to non-deterministic delay effects on synchronization.
Synchronization protocols or dedicated hardware
•
•
Establish time synchronization
Compensate of frequency drift of each node due to tolerance of
oscillators.
Synchronization methods
•
•
Two-way
One-way
Nome da conferência ou subtítulo da apresentação
3 | Data e local da apresentação
Motivation
•
A time synchronization method for a wearable system with the
following considerations:
•
•
•
Energy efficiency
•
•
•
•
Portable
Consume very small amount of energy while keeping
synchronization during system running.
Small batteries.
BS
Energy harvesting systems.
Accuracy
•
•
Simplicity
•
•
Avoid calculation
Small hardware size.
5
6
Nome da conferência ou subtítulo da apresentação
4 | Data e local da apresentação
7
2
Avoid cumulative end-to-end delay.
MAC sub-layer
Clock Reference Node
8
3
4
9
Synchronization Method, IEEE 1588
•
IEEE 1588 (Precision Time Protocol (PTP))
(𝑇2 − 𝑇1 ) + (𝑇4 − 𝑇3 )
𝑑𝑒𝑙𝑎𝑦 =
2
(𝑇2 − 𝑇1 ) − (𝑇4 − 𝑇3 )
𝑜𝑓𝑓𝑠𝑒𝑡 =
2
•
In synchronized mode with deterministic delay:
𝑑𝑒𝑙𝑎𝑦 = 𝑠 × τ
𝑜𝑓𝑓𝑠𝑒𝑡 = 0
•
•
•
s is the number of clock cycle required to send a message
𝜏 is system clock period.
Equations show that with eliminating non-deterministic delay sources,
PTP as a two-way protocol does not provide extra information.
Nome da conferência ou subtítulo da apresentação
5 | Data e local da apresentação
Synchronization Method, Proposed protocol
•
The idea is based on eliminating the sources of non-deterministic
delays during the time information exchange and compensating the
deterministic delays at the receiver.
𝑇2 = 𝑇1 + 𝑠 × 𝜏 + 𝑑𝑙 + 𝑆𝑟(𝑡)
⟨Sr(t)⟩ = τ
dl: signal propagation delay from sender to receiver
Sr: delay due to the phase difference between
sender and receiver clocks.
Nome da conferência ou subtítulo da apresentação
6 | Data e local da apresentação
Synchronization Method
•
If the deterministic delay value adds to the Sync message then the
clock skew between master and slave nodes will be
𝐶𝑠 𝑡 = 𝑇2 − 𝑇1 + (𝑠 + 1) × 𝜏 = 𝑑𝑙 + 𝑆𝑟 𝑡 − 𝜏
•
The Average value of Cs:
⟨Cs(t)⟩ = dl+⟨Sr(t)⟩- τ = dl
•
Therefore the average clock skew will be the same as propagation time
between two nodes. In a multi-hop connection, the instant and average
clock skew in a node with h hop distance from the reference node will be
Cs(t) = h(dl+Sr(t)-τ)
⟨Cs(t)⟩ = h.dl
Nome da conferência ou subtítulo da apresentação
7 | Data e local da apresentação
8
MAC layer Message Exchange
8
9
Protocol Implementation
• A synchronized clock Clk_sync is needed in all sensor
nodes
•
Frequency of Clk_sync is smaller than the system frequency.
• An auto-reload counter is used to generate Clk_sync:
•
when the value of a down counter TC reaches zero, an active
transition of Clk_sync is generated and the counter is reloaded
with a predefined value TCPR.
• For synchronization of Clk_sync, the value of TC must be
synchronized:
•
Each sensor periodically updates its TC value with the TC
value received from the timing message.
• In each sensor Time stamps are used to label the acquired
data.
•
9
The current time stamp at each sensor is maintained by an up
counter TS, which is driven by the synchronized clock signal
Clk-Sync.
1
0
Synchronization Circuit
• Block diagram of IC including time synchronization
module(Time Sync).
10
1
1
Block diagram of the circuit
add
data
Signal
Detector
6
Control
4
Line
Driver
8
Clk-sync
TC-Counter
(16 bit)
16
TS-Counter
(16 bit)
11
Sender
Receiver
TX
Line
SW
Lines
1
2
Circuit
Counters: a) TC-Counter, b) TS-counter
The frequency of Clk_sync is:
𝑓𝑠𝑦𝑛𝑐
𝑓𝑠
=
1 + 𝑇𝐶𝑃𝑅
The time interval between TS
overflows is
𝑇𝑜𝑣
12
65536
=
𝑓𝑠𝑦𝑛𝑐
1
3
Sender-Receiver Module
1- Request for timing information: start the
synchronization process by sending a request
message;
Configuration of Sender Receiver to send a request.
13
1
4
Sender-Receiver Module
2- Reply to a Request: reply to a timing request message
Configuration of Sender-Receiver for reply to a timing
information request.
14
1
5
Sender-Receiver Module
3- Reception of timing message: receive timing
information in response to a request message.
Configuration of Sender Receiver to receive timing
message.
15
1
6
Experimental Results
Main Characteristics of the experimental results
16
Parameter
Value
Technology
CMOS 0.35 𝜇m
# logic cells
971
Total area
0.138 mm2
Supply voltage
3.3 V
Clock frequency
20 MHz
Data rate
10 MHz
Clk_sync frequency
1 KHz
CMOS ASIC (0.35 µm) microphotograph with
indication of the synchronization circuit (TS).
TS
17
17
1
8
Experimental Results
Physical layer signals during timing message exchange
between SN2 and BS.
18
1
9
Experimental Results
One-hop clock skew with offset = 0x002F.
• The average clock skew is
4.6 ns which is delay due to
signal propagation between SN2
sender and receiver nodes.
50 ns
4.6 ns
BS
19
2
0
Experimental Results
Multi-hop clock skew with offset = 0x0030.
• In a multi-hop network, the
global average time skew
grows linearly with hop
count.
20
2
1
Experimental Results
Multi-hop clock skew with offset = 0x002F.
• The average clock skew is
4.6 ns which is due to signal
propagation between sender
and receiver nodes.
21
2
2
Experimental Results
The circuit current consumption for Clk_sync frequency up to 5 MHz
22
2
3
Conclusion
• By directly sending and processing the timing information
without buffering, the proposed approach leads to an
average clock skew of a few nanoseconds.
• The circuit generates two synchronized values:
•
•
a programmable clock signal
a real-time counter for time stamping purposes.
• In a multi-hop network, the global average time skew grows
linearly with hop count.
• The low skew values provided by this approach satisfy the
requirements of many BAN applications.
• The circuit achieves the maximum synchronization
performance that could be achieved by PTP, but with fewer
timing messages and calculations, less complexity and
better energy efficiency.
23
Thank you for your attention
Nome da conferência ou subtítulo da apresentação
24 | Data e local da apresentação