I run Vivado.
GUI is clear.
No programs loaded. Nothing.
I downloaded the Cmod A7 35T Project Repository from GIT Repo
I copy the path for the tcl file into my clipboard
C:\VivadoProjects\Cmod-A7-35T-GPIO-master\proj
back slashes changed to forward slashes
cd C:/VivadoProjects/Cmod-A7-35T-GPIO-master/proj
source ./create_project.tcl
completely new project opens in the workspace
I see a warning.
WARNING: [Runs 36-337] The following IPs are either missing output products or output
products are not up-to-date for Implementation target. Since these IPs are locked, no update to
the output products can be done.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command
'report_ip_status' for more information.
C:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/ip/clk_wiz_0/clk_wiz_0.xci
Error report:
Implementation (2 errors, 1 critical warning)
Design Initialization (1 criticAL WARNING)
[Project 1-486] Could not resolve non-primitive black box cell 'clk_wiz_0'
instantiated as 'inst_clk' ["C:/VivadoProjects/Cmod-A7-35T-GPIOmaster/src/hdl/GPIO.vhd":267]
Opt Design (2 ERRORS)
[DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'inst_clk' of
type 'inst_clk/clk_wiz_0' has undefined contents and is considered a black box.
The contents of this cell must be defined for opt_design to complete successfully.
[Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
Complete List of messages
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Analysis Results
sources_1
sim_1
Synthesis
Command: synth_design -top GPIO_demo -part xc7a35tcpg236-1 -flatten_hierarchy
none -directive RuntimeOptimized -fsm_extraction off
[Vivado_Tcl 4-391] The following IPs are missing output products for Implementation
target. These output products could be required for synthesis, please generate the output
products using the generate_target or synth_ip command before running synth_design.
C:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/ip/clk_wiz_0/clk_wiz_0.xci
[IP_Flow 19-2162] IP 'clk_wiz_0' is locked: * IP definition 'Clocking Wizard (5.3)' for IP
'clk_wiz_0' (customized with software release 2016.2) has a different revision in the IP
Catalog. * This IP has board specific outputs. Current project board
'digilentinc.com:cmod_a7-35t:part0:1.1' and the board 'unset' used to customize the IP
'clk_wiz_0' do not match. * Current project part 'xc7a35tcpg236-1' and the part
'xc7a15tcpg236-1' used to customize the IP 'clk_wiz_0' do not match. Please select
'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for
more information.
[Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
[HDL 9-1061] Parsing VHDL file "C:/VivadoProjects/Cmod-A7-35T-GPIOmaster/src/hdl/GPIO.vhd" into library xil_defaultlib ["C:/VivadoProjects/Cmod-A7-35TGPIO-master/src/hdl/GPIO.vhd":1]
[Synth 8-637] synthesizing blackbox instance 'inst_clk' of component 'clk_wiz_0'
["C:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/hdl/GPIO.vhd":267]
[Synth 8-638] synthesizing module 'GPIO_demo' ["C:/VivadoProjects/Cmod-A7-35TGPIO-master/src/hdl/GPIO.vhd":65]
[Synth 8-614] signal 'clk100' is read in the process but is not in the sensitivity list
["C:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/hdl/GPIO.vhd":326]
[Synth 8-3491] module 'debouncer' declared at 'C:/VivadoProjects/Cmod-A7-35T-GPIOmaster/src/hdl/debouncer.vhd:42' bound to instance 'Inst_btn_debounce' of component
'debouncer' ["C:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/hdl/GPIO.vhd":290]
[Synth 8-256] done synthesizing module 'debouncer' (1#1) ["C:/VivadoProjects/CmodA7-35T-GPIO-master/src/hdl/debouncer.vhd":50]
[Project 1-486] Could not resolve non-primitive black box cell 'clk_wiz_0' instantiated as
'inst_clk' ["C:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/hdl/GPIO.vhd":267]
[Device 21-403] Loading part xc7a35tcpg236-1
[Project 1-236] Implementation specific constraints were found while reading constraint
file [C:/VivadoProjects/Cmod-A7-35T-GPIOmaster/src/constraints/CmodA7_Master.xdc]. These constraints will be ignored for
synthesis but will be used in implementation. Impacted constraints are listed in the file
[.Xil/GPIO_demo_propImpl.xdc]. Resolution: To avoid this warning, move constraints
listed in ['Undefined'] to another XDC file and exclude this new file from synthesis with
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the used_in_synthesis property (File Properties dialog in GUI) and re-run
elaboration/synthesis.
[Synth 8-5545] ROM "txState" won't be mapped to RAM because address size (31) is
larger than maximum supported(25)
[Synth 8-5544] ROM "READY" won't be mapped to Block RAM because address size
(2) smaller than threshold (5)
[Synth 8-4471] merging register 'rgbLedReg2_reg[2:2]' into 'rgbLedReg1_reg[2:2]'
["C:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/hdl/RGB_controller.vhd":169]
[Synth 8-3886] merging instance 'strEnd_reg[0]' (FDSE) to 'strEnd_reg[1]'
[Synth 8-3333] propagating constant 1 across sequential element (\strEnd_reg[4] )
[Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the
messages will be disabled. Use the Tcl command set_msg_config to change the current
settings.
[Synth 8-3332] Sequential element (txData_reg[9]) is unused and will be removed from
module UART_TX_CTRL.
[Project 1-571] Translating synthesized netlist
[Netlist 29-17] Analyzing 47 Unisim elements for replacement
[Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
[Project 1-570] Preparing netlist for logic optimization
[Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
[Project 1-111] Unisim Transformation Summary: No Unisim elements were
transformed.
[Common 17-83] Releasing license: Synthesis
[Common 17-1381] The checkpoint 'C:/VivadoProjects/Cmod-A7-35T-GPIOmaster/proj/GPIO.runs/synth_1/GPIO_demo.dcp' has been generated.
[Common 17-206] Exiting Vivado at Fri Apr 28 00:28:44 2017...
Implementation
Design Initialization
Opt Design
[Vivado_Tcl 4-136] Directive used for opt_design is: RuntimeOptimized
Command: opt_design -directive RuntimeOptimized
[Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
[DRC 23-27] Running DRC with 2 threads
[DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'inst_clk' of type
'inst_clk/clk_wiz_0' has undefined contents and is considered a black box. The contents
of this cell must be defined for opt_design to complete successfully.
[Project 1-461] DRC finished with 1 Errors
[Project 1-462] Please refer to the DRC report (report_drc) for more information.
[Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
[Common 17-83] Releasing license: Implementation
[Common 17-206] Exiting Vivado at Fri Apr 28 00:29:00 2017...