An Efficient Layout Style For 2-Metal CMOS Leaf Cells
And Their Automatic Generationt
Chi-Yi Hwang* Yung-Ching Hsieh** Youn-Long Lin* Yu-Chin Hsu*
* Department of Computer Science
** Computer and Communication Laboratories
Tsing Hua University
Hsh-Chu, Taiwan 30043, R.O.C.
Industrial Technology Research Institute
Hsin-Chu, Taiwan 31015, R.O.C.
ABSTRACT We propose a new layout style that enables an
automatic layout synthesizer to take full advantage of the second
metal layer available from today’s technology. Our style not only
facilitates power/ground-diffusion overlapping but also simplifies
the intra-cell routing problem. We have implemented an
automatic layout synthesizer, called THEDA.P fJsing Hua Electronic Design Automation), based on the proposed style. Using
the same transistor placement algorithm, THEDA.P outperforms a
synthesizer based on [Ueh81]’s style by almost 20% in layout
compactness across a wide range of SSI circuits. THEDA.P has
been used to build a standard cell library that was previously
handcrafted. Results from designing two ASIC modules show
that THEDA.P’s layout quality is very.competitive.
layout style specifically designed for 2-metal CMOS leaf cell layout.
1. INTRODUCTION
A leaf cell in a VLSI design is a subcircuit of approximately
the complexity of an SSI component such as flip-flop, one-bit full
adder, A-0-1 gate, 8-to-1 multiplexer, etc. Instead of using parts
off-the-shelf, system users are designing their own Application
Specification Integrated Circuits(AS1C). Cell-based layout
methodology is good for ASIC designs because the layout process
can be fully automated, the turn-around time is short, and the
manufacturing reliability is high. A major weak point of this
methodology is in the design and maintenance of the cell library
for every upgrade to the fabrication process. Moreover, some
desirable cells may not exist in the library because both the
number and the variations in driving capability of cells are limited. Therefore, it is highly desirable to have a CAD tool that is
capable of automatically generating high quality layout for any
SSI circuits that not only are arbitrary structured but also have
arbitrary sized transistors.
We present THEDA.P, a successor to LiB [Hsi90]. Input to
THEDA.P is a SPICE file. Output from THEDA.P is a mask layout file (in CIF format) that meets the design rules specified in
another file. THEDA.P outperforms LiB by employing a novel
t This work was supported in part by the National Science Council,
R.O.C.. under contract no. NSC 80-0404-EW-19and the Ministry of
Economic Affairs, R.O.C., under contract no. OP21-32F1000.
Permission to copy without fee all or part of this material is granted
provided that the copies are not made or distributed for direct commercial
advantage, the ACM copyright notice and the title of the publication and
its date appear, and notice is given that copying is by permission of the
Association for Computing Machinery. To copy otherwise, or to republish,
requires a fee and/or specific permission.
To minimize the layout area of a cell, we have to reduce not
only its width but also its height. The most. effective way to
reduce the cell width is to maximize the number of drain-source
abutments between adjacent transistors (i.e. to minimize the
number of diffusion gaps) as suggested by [Ueh81]. Much work
has been done to address this problem (e.g. [Ueh81] [Mad901
[Naif341 [wim87] [Bar891 [Che88] [HwBO]). However, they
mostly concentrate on minimiziig of the number of diffusion gaps
only. In this paper, we propose a hybrid chaining algorithm that
considers both wiring density and transistor abutments simultaneously. Other notable work on leaf cell layout synthesis can be
found in [Bar891 [Dom89] [Hi1851 [Hi1901 [IC01881 [Lin88]
[Poi891 [Sta88] [Sun891 [Lef90].
The rest of this paper is organized as follows. In Section 2,
the new layout style will be presented and compared with the traditional one proposed by Uehara and Van Cleemput. The
THEDA.P system will be described in Section 3. Experimental
results are shown in Section 4. A disscussion on the limitations of
this work and suggestions for future research is given in Section
5. Finally, we draw a conclusion in Section 5.
2. LAYOUT STYLES
In this section we proposed a new layout style (also called
layout architecture) suitable for laying out leaf cells targeting
towards 2-metd CMOS fabrication technologies. We compare
this style against the traditional one proposed by Uehara and Van
Cleemput [Ueh81]. We shall use an XOR gate circuit depicting in
Fig. 1 throughout this paper to illustrate our presentation.
2.1. The Traditional Layout Style
Up to date, almost all leaf cell synthesizers reported in the
literature follow [UehSlI’s layout style or its variations. From
now on we shall call it the traditional layout style. The traditional
layout style is also employeed by some layout designers to handcraft standard cell libraries (e.g. [Hei87]). In this layout style,
there are two parallel horizontal diffusion rows, one for the P-type
transistors and the other for the N-typetransistors. This style and
its variations share a common attribute in that both the power and
ground rails lie outside the diffusion rows on the cell boundary.
According to the places where interconnection wires of the signal
nets run in, there are several variations to the style found in the
literature:
(1)
As shown in Fig. 2(a), the power (ground) rail and the PMOS
(NMOS) diffusion row are overlapped while all the signal
28th ACM/IEEE Design Automation Conference@
’1991 ACM 0-89791-395-7/91/0006/0481$1.50
Paper 29.2
481
A
-
8
Fig. 1 An XOR Leaf Cell Circuit
nets are connected in the region between these two diffusion
rows (e.g. [wim87]);
As shown in Fig. ab), same as ( 1 ) except that a selected set
of nets (subnets) are routed on the diffusion rows (e.g.
[~i$91);
As shown in Fig. 2(c). both the power and ground rails are
separated from the diffusion rows while, in addition to the
major region between the diffusion rows, two minor regions
(i.e. one between the power rail and the PMOS diffusion row
and the other between the ground rail and the NMOS diffusion row) are used for routing (e.g. [Shi88] [Che89] [HsiW]
[Blo90]).
Fig. 2(a) Variation 1: All Nets Are Routed in the Middle
2.2. Problems with the Traditional Layout Style
There are two major weaknesses with the traditional layout
style: the intra-cell routing is difficult and the second metal layer
is poorly utilized. For all the variations to the traditional style
mentioned in the previous subsection, none of the routing regions
is obstacle-free. If we route all signal nets in the major region
between the diffusion rows (variation l), the horizontal wire segments are very likely to change their layers quite frequently,
hence, introduce a lot of via holes, because there exist already
many polysilicon (connecting aligned gates) and metal-1 (connecting aligned drain-sources) wire segments in the vertical direction. To avoid jumping horizontal wires up and down, some system (e.g. [Wim87] [Che89]) opt to unify the layer of the pins
before they go into the routing region by introducing vias at the
boundary between the diffusions and the routing region. The
consequence is that both the width and the height of the cell are
increased due to the presence of vias.
Routing either on the diffusion rows or in the minor regions
between the power/ground rails and the diffusion rows could help
ease the routing in the major (middle) region to some extent.
However, the price we have to pay first is the loss of the
power/grounddiffusion overlapping. This will increase the cell
height significantly. Moreover, the minor routing regions also
contain some obstacles (i.e. the connection for powa supply
between the power/ground rails and the diffusion rows).
When Uehara and Van Cleemput proposed the traditional
layout style in 1981. the dominating CMOS fabrication technologies offered only one layer of metal. As the fabrication technology advancing, a second (even third) layer of metal becomes commonly available. Leaf cell layout synthesizers based on the traditional layout style or its variation cannot take full advantage of the
Paper 29.2
482
Fig. 2@) Variation 2 Some Nets Are Routed
on the Diffusion Rows (Size: 7.00x 6.40 = 44.80)
Fig. 2(c) Variation 3: Power and Ground Are
Separated From the Diffusions (Size: 6.35 x 7.20 = 45.72)
second metal layer. Instead the second metal layer is used mostly
for built-in feed-through in the cell level and channel routing in
the module (placement-and-route) level.
2.3. The New Layout Style
As mentioned previously, all the layouts based on the traditional layout style have the diffusion rows sandwiched by the
power and the ground rails. This is understandable in a one-metal
CMOS technology. Since both the power and the ground rails are
already in the first metal layer, placing them between the diffusion
rows will prevent the aligned drain-sources (pin out at metal-1
layer) from W i g connected. Now, with the second metal layer
available, the issue of layout style deserves a re-investigation.
If we connect the aligned drain-sources using metal-2 wires
the L regions.
In the cell we use the metal-2 layer vertically only to connect
aligned drain-sources pairs and to enter the U or the L regions for
drain-source signal pins. All the columns where no abovementioned situations occur can be used for implementing built-in
feed-throughs. Even the columns of transistor gates can be so
used.
2.4. Advantages of the New Layout Style
vertically, the power/ground rails can be moved from the cell
boundary into the region between the diffusion rows. Consequently, we can route the signal nets in the obstacle-free regions
both above the PMOS diffusion row and below the NMOS diffusion row.
For the four different layouts (Fig. 2(a). 2(b), 2(c) and 3) of
the XOR circuit, their area ratio is 1.51 : 1.30 : 1.33 : 1.00. Obviously, the layout based on the proposed layout style is much
smaller than those based on the traditional layout style. The principal advantages of the new layout style are summarized as follows:
Based on the above-mentioned observations. we propose the
new layout style as depicted in Fig. 3. In the new layout style,
transistors are still placed in two parallel rows. All P-type transistors are in one row while all N-type- transistors are in the other.
The power/groundrails are routed in the first metal layer beween,
instead of outside, the diffusion rows. For intra-cell routing, there
are three regions:
(1) Overlapping of the powerlground rails and the diffusion
rows: Because there is no metal-1 object between the power
rail and the center line of the PMOS diffusion row nor
between the ground rail and the center line of the NMOS diffusion row, the diffusion layer of the large sized transistors
can be extended directly to beneath the power/ground rails.
This feature can reduce the cell height quite significantly.
(1) U Region: the upper region above the PMOS diffusion row.
(2) M Region: the middle region between the PMOS diffusion
row and the NMOS diffusion row, and
(2) Simplification of the routing problem: Our routing problem is very simple because both the U and the L regions are
obstacle-free and the pins along the region boundaries do not
vertically constrain each other. Therefore, the left-edge algorithm [Has711 is adequate for obtaining the optimal solution.
(3) L Region: the lower region below the NMOS diffusion row.
All vertically aligned signals are routed in the M region.
Every pair of aligned P-typeand N- type transistor gates is connected directly using a vertical polysilicon wire across the
powerlground rails without introducing any via hole. Every pair
of aligned drain-sources is connected using a vertical metal-2 wire
across the power/ground rails after making connection to each diffusion with two consecutive vias (one from diffusion to metal-1;
and the other from metal-1 to metal-2). A horizontal track is
reserved between the power and ground rails for routing short
polysilicon wire segments to break the cyclic vertical constraints
introduced by the cascaded pairs of transmission gates.
Both the U and L regions are obstacle-free and used to route
the signal nets. Since the transistors are usually of unequal sizes,
the routing regions are rectilinear, instead of rectangular, shaped.
We employ the VHV layering model for routing both the U and
(3) Localized polysilicon wire usage: Since the polysilicon
layer has relatively poor conductivity. a layout engineer is
usually asked not to run in it too long a wire. In our layout
style, the polysilicon layer is used exclusively in the vertical
direction except the short segments for breaking the cyclic
constraints in the M region or saving contacts in the U and L
regions. This is essential to high performance layout design.
(4) Relaxed cell height constraint: In order to be abutted with
its neighboring cells, a cell must has the distance between its
power and ground rails fixed. Moreover, its well region must
also follow a prescribed constraint, otherwise, there may
exist design rule violations between its well and some diffusion objects outside the well of its neighboring cells.
According to our experiencewith the traditional layout style,
these constraints often lead to either wasted area in small
cells or layout failure in large cells. In the new layout style,
these constraints can be relaxed because both the
power/ground rails and the well boundary are in the middle.
The alignment between any two cells is natural no matter
what their cell heights are. Therefore, a small cell will leave
the area for intercell (channel) routing while a large cell will
be easier to complete. This is, in some sense, a kind of
delayed binding strategy. After placing cells into rows, the
channels become, instead of rectangularly, rectilinearly
shaped.
3. THE THEDA.P SYSTEM
3.1. System Overview
Fig. 3 Layout of The XOR Cell Based on
The New Layout Style (Size: 5.65 x 6.10 = 34.465)
THEDA.P consists of ten subtasks:
(1) Clustering
(2) Cluster Placement
Paper 29.2
483
Transistor Pairing
Hybrid Chaining
Chain Placement
Routing Region Modeling
Large Transistor Folding
Net Assignment
Detailed Routing
(10) Compaction and Geometry Transfer
Due to the space limitation, only cluster placement, hybrid chaining, net assignment, and detailed routing will be presented here
(Sections 3.2. 3.3 and 3.4). The remaining algorithms can be
found in [HsiW].
3.2. Cluster Placement and Hybrid Chaining
These algorithms place the transistors into two parallel rows:
the PMOS diffusion row and the NMOS diffusion row. The
objectives include to minimize the number of diffusion gaps and
to minimize the wiring density.
There may be more than one chaining solution with the
minimum number of diffusion gaps. Since their transistor pair
orderings are different, their wiring densities could be different.
As stated in Section 1, failure to address either issues will lead to
an inferior layout. Here we propose a hybrid algorithm that combmes both theplacement-based (i.e. to reduce the wiring density,
e.g. min-cut[Ker70], relaxation-based) and the chaining-based
(i.e. to reduce the number of diffusion gaps, e.g. [Wm87]
[HwBO]) methods. The algorithm is augmented with a
parameterized control scheme to make trade-offs between the two
objectives.
We firstly use the min-cut technique to order the clusters of
the cell into an onedimensional array such that the maximum
number of nets across a cluster boundary is minimized. A cluster
consists of a set of paired strongly connected transistor (e.g. those
constituent a primitive gate) and is identified by the transistor
clustering subtask
Starting with the leftmost cluster, a maximum set of consecutive clusters whose total number of transistor pairs is no greater
than aK a parameter, aK,is collected and fed into the chaining
algorithm of [HwaW] at a time. For those short chains (i.e. length
< a parameter. aL)resulted from the chaining, we can mix them
with the next set of clusters to partition in, hopefully, more abutments. However, in order not to distort the decision made by the
cluster placement procedure, we will only do so when a chain is
not too far away from its original location decided by the clustering procedure (again, according to a parameter, aD).
Parameters aK,aL and a, are used to make trade-offs
between the number of diffusion gaps and the wiring density. The
larger their values are the more important the number of diffusion
gaps is.
3.3. Net Assignment
All horizontal nets except those serving as cyclic constraint
breakers will be routed in either region U or L while all vertical
nets between the PMOS and the NMOS will run in region M. We
classify all nets into five types:
(1) VDDorvss;
Paper 29.2
484
gate # p e d or source/drain aligned nets;
horizontal nets which can be routed in region U (or region L)
only (called singular nets);
horizontal nets which must be routed in both regions U and
L; and
horizontal nets which can be routed in either region U or L.
Since both VDD and VSS connections can be made directly by
introducing vias from the power/ground rails to the diffusion mws
and there is only unique choice for nets of type 2, 3 and 4. we
focus on type 5 nets only. Om primary objective is to minimize
the number of tracks needed. In addition, we also take into
account the total wire length as well as the balance between the
number of tracks of region U and region L. In order to solve this
problem, we use the Left Edge Algorithm (LEA) [Has711 and a
bipartite graph model (refer to [Hsi90]).
Fig. 4(a) shows the transistor placement together with the
interconnection requirement of our XOR circuit example, where
Net 8 is VDD while Net 0 is Vss. Nets 4 and 9 form a cyclic constraint in the middle. After connecting power/ground using 4 vias
(i.e. 0 and 8). connecting vertically aligned gates using 4 polysilicon wires (i.e. 2, 7. 5 and 9) and aligned drain-sources using 5
metal-2 wires (i.e. 3, 5, 2, 6 and 4), and breaking the cycle by
routing Net 9 in the M region using a short polysilicon wire, the
remaining connections to be made using Regions U and L are
Nets 2.4,5 and 9. Since Net 4 needs to be routed in both the U
and L regions (type 4) and Net 2 can share the same track with
Net 4 in the U region, what left for the net assignment procedure
me Nets 5 and 9 (type 5) (Fig. 4(b)). It should be noted that the
wires of Net 4 in Regions U and L are connected via a vertically
aligned drain-source pair. In case such a pair is absent, a feedthrough has to be inserted. Fig. 4(c) shows the bipartite graph
modeling the situation after attempting to route both Nets 5 and 9
in the U and L regions using the LEA.
3.4. Detailed Routing
The detailed router complete the interconnection in both
Regions U and L. The new layout style makes the task of detailed
routing very easy because there is neither obstacle in the routing
regions nor vertical constraint among terminals (pins). The simple LEA is adequate for obtaining a solution consuming only the
minimum number of horizontal tracks. However, in order to
make the symbolic layout more compactable, we augment the
LEA with some ad hoc rules. For example, assigning a short wire
segment to the track close to the diffusion rows could result in
saving some layer changing, hence, via holes and, eventually, the
cell area
4. EXPERIMENTS
We have implemented the THEDA.P system in C programming language on a SUN-3/60 workstation under UNIX operating
system. To test the efficiency of the proposed layout style, we
firstly let both LiB and THEDA.P synthesize a set of 20 typical
SSI circuits. Both LB and THEDA.P use the same transistor
placement algorithm as well as the same symbolic compactor.
Therefore, the difference in layout quality is solely due to the
differences in the layout styles and the intra-cell routings. Shown
in Table 1 are the cell height, width, and area as well as the computer time consumption of every circuit. The target technology is
a 1.2 pm 2-metal CMOS process. In all cases, THEDA.P did
better than LiB. Overall. THEDA.P reduced the layout area by
19%. THEDA.P also consumed less CPU time than LiB did due
3
2
8
7
5
9
2
4
6
5
8
9
4
THEDA.P's layout is about 4% bigger than the manual layout.
We then used these two libraries separately to design two ASIC
modules: mute and receiver, using SYMBAD/SBB, a commercial
placement-and-routing tool. Module mute consists of 332 cells
(4919 transistors) while module receiver consists of 304 cells
(4829 transistors). The modules based upon the library created by
THEDA.P are only 7% and 5% bigger, respectively, than those
based upon the manually crafted library.
5. DISCUSSIONS
3
2
0
7
5
4
2
9
6
5
0
9
4
(a) Transistor Placement and Interconnection Requirement
3
2
8
7
5
9
2
4
6
5
8
9
4
3
2
0
7
5
4
2
9
6
5
0
9
44
Unlike the standard cells of a library, the cells laid out by
THEDA.P are not characterized. Therefore, to use THEDA.P
on-the-fly, a circuit tunner (or called transistor sizer) is needed to
interact with THEDA.P by iteratively extracting and analyzing
THEDA.P's layout then giving THEDA.P the size of each individual transistor.
In THEDA.P's layout style, transistors are placed into two
parallel rows and oriented homogeneously. For some circuits,
using multiple rows or rotating transistors may be advantageous.
Although THEDA.P is capable of handling circuits of unequal
number of P- and N-type transistors, it is not designed for circuit
families such as pseudo NMOS or dynamic CMOS. To layout
those NMOS dominated circuits, we need a new layout style.
5
9
(b) After Breaking the Cyclic Constraint and
Making Unique Choice
Fig. 5(a) La's Layout of DFF30
(c) The Bipartite Graph
Fig. 4. The XOR Circuit Example for Net Assignment
to its simpler routing task. Fig. 5 shows the layouts for DFF30
generated by both LiB and THEDA.P.
Secondly, we let both LiB and THEDA.P to generate the 44
leaf cells of the benchmarks of the 1989 Module Generation and
Silicon Compilation Workshop (described in the file "db.vpnr").
The number of transistors in this set of benchmarks is much
smaller (the largest circuit consists of 16 transistors) than that in
the previous one. On the average, THEDA.P's layouts are 19%
smaller than those of LiB.
We also used THEDA.P to create a %-cell library that was
previously handcrafted (using SYMBADPEDS, a polygon-level
layout editor) based on the txaditional layout style. Overall,
Fig. 5(b) THEDA.P's Layout of DFF30
* SYMBAD
is a trademark of Cadence Design System, Inc.
Paper 29.2
485
When being used in a module environment, the cell
locations should be determined in a topdown rather than bottom-up
fashion. Although, THEDA.P does support top-down partitioning. it provides the users no control over the U 0 pin locations.
Instead it assigns U 0 pins in the traditional standard cell fashion.
This allows us easily integrating THEDA.P into a standard cell
placement-and-routesystem. However, we would like to support
more flexible U 0 specification in the future.
6. Conclusions
An efficient layout style for 2-metal CMOS leaf cells has
been presented. It not only facilitates the overlapping between
power/ground and diffusions but also simplifies the intra-cell routing problem. An automatic layout generator, called THEDA.P,
has been developed. Experimental results show that THEDA.P
outperfom LiB. a generator based on the traditional style, and is
very close to the human layout quality when building a standard
cell library.
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[Bar891 Bar-Yehuda, R., J. A. Feldman, R. Y. Pinter and S.
Wimer, "Depth-First-Search and Dynamic Programming
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[Che88] Chen, C.Y.R.. and C.Y. Hou, "A New Layout Optimization Methodology for CMOS Complex Gates," ICCAD-88,
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[Hi1901 Hill, D. D., M. A. Aranha, and D. D. Shugard, "Placement
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.
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[Ma901 Maziasz. R. L. and J. P. Hayes, "Layout Optimization of
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Table 1. Comparison between LiB(L) and THEDA.P(T)
C
IN12
- ,- wid rrm) - m
w (Bm) 1- L
L
L
T
L
T
Ix'tas
ILL -- -1.78
57.2 54.4
31.2
321
1.75 m 7 3
a33
Arc
4
633
56.0
105.0
NAW
4
AN31
Mux2
XORU
lRl1
OR41
DLOO
AOlW
OAIM
NA81
m 4
NO81
DPIUO
DIT30
JKFlT
FAO1
DLHx4
8
12
12
12
14
18
513
602
521
620
523
633
88.4
48.8
53.0
493
57.2
47.4
58.1
56.9
64.6
698
535
648
63.2
66.2
795
793
n.6
73.1
565
495
58.2
575
64.2
705
620
67.2
628
23.4
21.3
31.8
30.6
55.5
50.1
49.2
43.8
522
60.6
624
522
87.3
83.4
80.1
720
822
74.4
87.6
77.7
90.0
99.9
71.7
69.0
113.7 108.9
130.8 1326
117.2 116.2
129.6 1215
157.2 150.4
225.4 210.9
"14
U)
22
22
22
22
31
34
34
36
44
70
58.0
113.1
6.65
1.U)
1.91
289
3.05
3.17
3.95
5.97
5.17
5.74
4.69
6.47
453
753
10.40
9.29
10.06
llA9
1.W
1.62
247
251
247
3.03
4.75
4.18
4.m
3.85
5.w
3.97
6.99
935
7.m
8.16
9.45
0.95
3.7
0.81
1.4
1.4
38
0.85
0.85
0.82
0.78
om
0.80
0.81
0.73
0.82
0.81
0.88
0.93
0.90
0.78
0.81
0.82
0.86
0.84
24
28
26
1.8
5.8
25
4.4
29
m.4
145
10.7
16.1
10.4
163
69.0
56.6
16.43 - - 843
- - 19.00
-- E104.99 - Total
-
20
24
20
3.6
5.8
4.2
8.7
49.0