Identification of Critical Parameters for Plasma Process-Induced Damage
in 130 and 100 nm CMOS Technologies
*HHUW9DQGHQERVFK%ULFH'H-DHJHU=VROW7 NHLDQG*XLGR*URHVHQHNHQ
IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
[email protected]
Abstract
Plasma process-induced damage (P2ID) in advanced
CMOS down to the 100 nm node is investigated both
conceptually and experimentally. An antenna layout that
takes into account the two-dimensional aspect ratio
dependence of P2ID in single or dual damascene
interconnect is proposed and experimentally validated.
The sensitivity limitations of conventional P2ID
assessment with gate leakage are overcome by a more
discriminating evaluation procedure that includes a
short pre-stress. Experiments on selected damascene
process steps indicate that their P2ID can be kept under
control in most cases. Temperature is identified as a
critical process parameter. Using the pre-stress method,
sound evidence of vanishing P2ID in ultrathin oxides
below 2 nm has been obtained. In addition, the impact of
P2ID on long-term product reliability is calculated to be
reduced in thinner oxides.
P2ID of a selection of process modifications is reported.
Finally, the oxide thickness dependence of P2ID is
investigated as well as the impact on product reliability.
2.
Antennas for SD and DD BEOL
Plasma process-induced charging is evaluated with
antennas. To separate the contributions of different
process levels, protection is added one interconnect level
above the level of interest. Next to the conventional plate
and comb antennas with various antenna ratios (AR) at
poly and metal level, additional contact and via antennas
are needed that specifically assess the two-dimensional
aspect ratio dependence of P2ID in a SD or DD flow [2].
Fig. 1 shows the possible layout options labeled plate,
DAM0 up to DAM4, corresponding to increasingly
higher confinement of the contact/via holes (which act as
charge collectors) by the trench walls of the interconnect
metal trench grid on top of the holes.
1. Introduction
Downscaling of CMOS technology continues with a
rate that is even increasing in recent years. In the front
end, nitrided gate oxide thickness is reaching the lowest
achievable limits with respect to leakage current and
long-term reliability. In the back-end-of-line (BEOL), the
conventional aluminum/oxide interconnect is replaced by
copper/low-k dielectric to reduce RC delay. This requires
not only new process steps but also novel integration
schemes to adopt a damascene approach for Cu.
In order not to compromise long-term gate oxide
reliability, all aspects of the aforementioned evolution
need to be characterised for plasma process-induced
damage (P2ID), as the main manifestation of P2ID in
ultrathin oxides is a consumption of available time-tobreakdown (tBD) due to charging [1]. In this paper, the
critical P2ID issues in advanced CMOS down to the 100
nm node are identified, both on the level of assessment
methodology as well as process technology. An antenna
layout for single (SD) and dual damascene (DD) P2ID
assessment is presented first. Then, the limitations of
conventional P2ID evaluation with low-bias gate leakage
current in thin oxides are demonstrated, and a more
powerful alternative is introduced. Next, the impact on
Figure. 1. Damascene grid antennas.
The confinement of the charge collecting area of a
given grid can be quantified by its opening angle to the
plasma [2]. This opening angle depends on whether the
grid is created in a SD or a DD scheme: in the SD
scheme (grid-on-contact), the top of the contact plugs
collect the charge, while in the DD scheme (grid-on-via)
charge collection is at the bottom of the vias. The value
depends on the dimensions of hole and trench, and on the
thickness of the dielectric stack. In particular, the angle
decreases with higher aspect ratio holes and smaller
trench-to-hole overlap. Experimental validation of these
antennas is provided in Section 4.
3.
P2ID evaluation in thin oxides
While gate leakage provided satisfying results in less
advanced technologies, in thin gate oxides (below 5 nm)
interpretation of the data becomes less straightforward
due to emerging “soft” failures [3]. Typical gate leakage
current distributions obtained on contact antennas with
gate oxide thickness tox = 3.5 nm are shown in Fig. 2a.
Evaluation was at 2 V in accumulation, i.e. Vdd+10%. In
Fig. 2a, the damage tends to increase with the number of
contacts. This antenna effect points to plasma charging.
However, the current level is generally low and the
distributions are featureless. As a consequence it is hard
to quantify the antenna effect with actual yield numbers.
Moreover, at the conventional level of 1 nA, the yield is
always close to 100%, suggesting only minor damage.
10-5
2 contacts
100 contacts
1e3 contacts
1e4 contacts
Ileak (A)
10-7
damaged during plasma stress. The transition between
the two ranges is sharp. As a consequence, the yield
numbers are insensitive to the actual failure criterion.
Fig. 2 demonstrates that in thin oxides below 5 nm the
conventional low-bias gate leakage measurement may
severely underrate plasma charging damage.
4.
As low-k intermetal dielectric (IMD) will be needed
from the 130 nm node on, a first issue is the type of IMD
material. An inorganic PECVD deposited SiOC:H film
and an organic spin-on polymer, both with k = 2.7, were
compared to conventional PECVD SiO2. As far as film
deposition is concerned, the type of dielectric is not
expected to have a significant impact on P2ID. On the
other hand, trench etch and strip vary with the material in
the IMD stack. A dedicated SD experiment, the results of
which are shown in Fig. 3, did not reveal appreciable
differences in P2ID performance of these steps.
10-9
100
Antenna Yield (%)
10-11
10-13
0.001
Ileak (A)
10-5
10-7
2 contacts
100 contacts
1e3 contacts
1e4 contacts
80
60
40
20
0
10-9
oxide
SiOC:H
organic
type of IMD dielectric
Figure 3. Dependence of yield of nMOS plate
contact antennas on type of IMD dielectric.
10-11
10-13
Critical steps and modules
0
20
40
60
80
100
Percent
Figure 2. Contact antenna gate leakage current
measured (a, top) at 2V (b, bottom) at 2V in
accumulation after 5V pre-stress for 1.8s.
To resolve this apparent sensitivity problem a shorttime pre-stress at high bias is applied before the actual
leakage measurement at low bias. Gate leakage of the
same devices measured at 2 V after a 5 V pre-stress for
1.8 s is shown in Fig. 2b. Under these conditions the
intrinsic failure rate of the undamaged oxide is still
negligibly small. In the antennas, the pre-stress is seen to
cause primarily “hard” failures (i.e. with current many
orders of magnitude higher than prior to stress), the
amount of which is increasing with antenna ratio. Gate
leakage essentially shows two distinct ranges: a high
range on the one hand, from devices that have been
heavily damaged or broken during plasma stress; on the
other hand a very low range, from devices minimally
The application of an Ar sputter preclean prior to the
metallic barrier deposition is one of the sources of P2ID
in damascene. An experiment has been set up in which
the preclean time was varied at the DD level. As shown
in Fig. 4, a 30 s preclean introduces significantly more
damage than a 10 s preclean. Fig. 4 also illustrates the
dramatic effect on P2ID yield of the layout of the gridon-via antennas of Fig. 1, as quantified by the relative
opening angle to the plasma. From P2ID point of view,
the preclean time should be kept to the minimum
required for efficient cleaning.
Ta(N) Cu-barrier PVD itself is another potentially
hazardous step. The negative impact of wafer bias power
on the one hand, and of a bottomless barrier approach on
the other hand has already been demonstrated in ionized
PVD (I-PVD) of the first generation [2]. Next generation
I-PVD approaches provide superior barrier and seed
processes and are expected to extend PVD at least down
to the 100 nm node [4]. There is concern for P2ID as the
conditions of the new approach in terms of plasma power
and wafer bias are significantly different from those of
first generation I-PVD. In favour of the new approach is
the lower temperature during deposition (see further). A
benchmarking experiment has been set up. As shown in
Fig. 5, at the SD level P2ID response fortunately turned
out to be similar for the two generations.
Antenna yield (%)
100
1e3 vias
10s preclean
30s preclean
40
20
0
4
5
6
7
8
9
Figure 4. Yield of DD grid-on-via antennas for
two preclean times.
tox (nm)
Vpre-stress (V)
next generation I-PVD
first generation I-PVD
100
AR=1e3
Antenna yield (%)
60
40
20
2
1e2
1e3
1e4
AR=1e5
100
Short cool time
Long cool time
80
60
80
60
40
20
100
Antenna yield (%)
Figure 5. Yield of pMOS contact antennas for two
types of barrier deposition.
Antenna yield (%)
AR=1e4
1.5
3.1
0
Antenna size (#contacts)
80
60
40
20
0
40
5.0nm 3.5nm 3.0nm 2.0nm 1.8nm 1.5nm
Gate oxide thickness
Figure 7. Yield in pMOS poly antennas. (a, top)
conventional method (b, bottom) after pre-stress.
20
0
Table 1. Pre-stress bias
5.0
3.5
3.0
2.0
1.8
6.4
5.0
4.6
3.6
3.4
100
80
0
Gate oxide thickness dependence
10
opening angle (%)
Antenna yield (%)
5.
Gate oxide thickness dependence of P2ID was studied
in the range 5.0 nm to 1.5 nm equivalent oxide thickness
(250 to 100 nm technology node). For a fair comparison
of P2ID performance across different tox, the pre-stress
bias is to result in an equal time-to-breakdown (much
higher than the pre-stress time) across the tox. Pre-stress
bias is listed in Table 1, time was fixed at 1.8s.
Evaluation bias was at the respective Vdd+10%.
80
60
be concentrated in the center of the wafers where the
temperature is expected to be highest. The temperature at
which the charging occurs is crucial in ultrathin oxides as
it determines the available tBD [5].
2
1e2
1e3
1e4
Antenna size (#contacts)
Figure 6. Yield of pMOS contact antennas for two
wafer temperatures at barrier deposition.
A general issue is the wafer temperature during
plasma processing. The significance of this parameter is
illustrated by the following contact barrier experiment. In
the sequence, a high-temperature degas step precedes the
actual deposition at lower chuck temperature. The cool
time in between degas and barrier PVD was varied. It is
clear from Fig. 6 that the wafers with long cool time
consistently show less P2ID than the wafers with short
cool time. In addition, the remaining damage turns out to
In Fig. 7, P2ID at the poly level is shown. A clear
oxide thickness dependence is revealed which is already
reasonably well revealed by the conventional evaluation,
indicating mainly hard failures. The major damaging step
was identified to be the pre-metal dielectric deposition, a
high-temperature, high density plasma process. P2ID is
most severe at 3.5nm and gradually recovers at lower tox.
At 1.5nm P2ID has very nearly disappeared.
In Fig. 8, P2ID at the contact level is shown. Here, the
failures are so soft that conventional evaluation hardly
reveals any damage. After pre-stress severe damage is
seen to persist down to 3.0nm, at still lower tox a sharp
recovery occurs. The apparent absence of damage in this
region was confirmed by TDDB tests.
In globo, with processing steps as well as layout rules
still compatible with today’s technology, these findings
nevertheless provides a realistic preliminary indication of
P2ID alleviation in ultrathin oxides of future nodes.
100 cts
1e3 cts
This relation is graphically represented in Fig. 9 for a
fixed Fspec and with β hence tox as a parameter. For given
F0, the impact on product lifetime is seen to decrease
with smaller tox. In the limiting case of β = 1, there is no
impact of P2ID yield on long-term reliability at all.
1e4 cts
1
Relative lifetime τ/τref
100
Antenna yield (%)
80
60
40
20
0
100
Antenna yield (%)
60
20
7.
5.0nm 3.5nm 3.0nm 2.0nm 1.8nm 1.5nm
Figure 8.Yield in pMOS contact antennas. (a, top)
conventional method (b, bottom) after pre-stress.
Impact on long-term reliability
Plasma charging consumes part of the oxide lifetime
causing a fraction F0 of the population to fail after
plasma stress [6]. Using weibull wearout statistics [7],

 t
F0 = 1 − exp−  ch
  t 63%

β

 

 

(1)
where tch is the plasma charging time and t63% the oxide
lifetime. β is the shape factor of the distribution and is an
increasing function of tox [7]. The cumulative failure
distribution Fs of the survivors of the plasma stress is [6]
Fs (t ) = 1 −

 t + t ch
1
⋅ exp− 
  t 63%
1 − F0

β

 

 


1/ β
 t
1
= 1−
⋅ exp− 
+ [− ln(1 − F0 )]
  t 63%
1 − F0

(2)
β

 

 

Eq. 2 relates long-term reliability to P2ID yield. The
product lifetime τ is commonly defined at Fs = Fspec =
100ppm. From Eq. 2 the lifetime τ with respect to the
undamaged reference lifetime τref can be expressed as
τ ref
Fspec=100ppm
0.001
0.01
0.1
Figure 9. Reduction in long-term reliability versus
initial plasma charging yield loss.
40
τ
β=4.9
(tox~5nm)
β=1.8
(tox~3.5nm)
Plasma charging induced yield loss F0
Gate oxide thickness
6.
0.1
0.01
0.0001
80
0
β=1.2
(tox~1.5nm)
1/ β
1/ β
[
− ln ((1 − Fspec )(1 − F0 ))]
− [− ln(1 − F0 )]
=
[− ln(1 − Fspec )]1 / β
Conclusions
The critical parameters of P2ID in advanced CMOS
with damascene back end and gate oxide thickness down
to 1.5 nm have been investigated. With suitable antennas,
the 2-D aspect ratio dependence of P2ID in SD and DD
interconnect is experimentally verified. To overcome the
sensitivity limitations of conventional P2ID evaluation
with low-bias gate leakage in thin oxides below 5 nm, a
more discriminating evaluation procedure that includes a
short pre-stress has been introduced. Experiments on
selected damascene process steps indicate that their P2ID
can be kept under control in most cases. On the other
hand, the wafer temperature is identified as a critical
parameter. With the pre-stress method, sound evidence
of vanishing P2ID in ultra-thin oxides of 2 nm and below
has been obtained. In addition, the impact of P2ID on
long-term product reliability is calculated to be reduced
in thinner oxides.
Acknowledgements
The authors are indebted to C. Demeurisse, E. Augendre,
M. Jurczak, I. Debusschere and M. Van Hove. Part of this
work was funded by projects IWT-PINDA and MEDEA-T201.
References
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1445 (1999)
[4] B.L. Chin et al., Semiconductor International May 2001,
p.107
[5] R. Degraeve et al., Proc. 1999 Symp. VLSI Technology, p.
5B-2
[6] P.W. Mason et al., Proc. 2000 P2ID, p. 2
[7] R. Degraeve et al., IEEE Trans. Electron Devices vol. 45,
p. 904 (1998)