Verilog
Sequential Circuits
Ibrahim Korpeoglu
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Verilog can be used to describe storage elements and
sequential circuits as well.
So far continuous assignment statements are used in
a behavioral description.
A continuous assignment in Verilog is a statement
that executes every time the right hand side of the
an assignment changes.
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(executes here means executing in simulation;
Hardware counterpart already simulates that behavior)
Continuous assignment
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The continuous assignment is used to assign a value onto a wire
in a module. It is the normal assignment outside of always or
initial blocks.
Continuous assignment is done with an explicit assign statement
or by assigning a value to a wire during its declaration.
Note that continuous assignment statements are concurrent and
are continuously executed during simulation. The order of
assign statements does not matter. Any change in any of the
right-hand-side inputs will immediately change a left-hand-side
output.
Continuous statements
Process
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A process can be viewed as a replacement for
continuous assignment statement hat permits
considerably greater descriptive power.
Multiple processes may execute concurrently and a
process may execute concurrently with continuous
assignment statements.
 i.e. we can have a continuous statement X outside
of the procedure Y executing concurrently with Y
Process
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Within a process, procedural assignment statements,
which are not continuous assignments, are used.
Because of this, the assigned values need to be
retained over time. This can be achieved by using
reg type (register type) rather than wire type.
Procedural Assignments
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Procedural assignments are assignment statements
used within Verilog procedures ( always and initial
blocks). Only reg variables and integers (and their
bit/part-selects and concatenations) can be placed
left of the “=” in procedures.
The right hand side of the assignment is an
expression which may use any of the operator types
we have seen earlier.
Process
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There are two basic types of processes
 initial process
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Used only in simulations
executes only once, beginning at time t = 0.
always process
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Used in simulations and synthesis
Also executes at time t=0; but also executed repeatedly
afterwards.
Timing control is done by events of delay
Timing control
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# integer
 Can be used to specify a delay
 Example: # 100 means wait 100 simulation time
units.
@ event
 Can be used to wait for an event, and then
execute
 @ expression
The occurrence of event causes the process to
execute.
Process
begin
end
procedural assignment statements;
…
…
assignment statements can be blocking or non-blocking.
Assignment statements
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Blocking assignment
 Uses =
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Next statement has to be executed after the current
statement completed (sequential execution of statements)
Non-Blocking assignment
 Uses <=
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Next statement executes at the same time with the current
statement. (parallel) execution of statements)
Assignment statements
Example Process
begin
B = A;
C = B;
end
Example Process
begin
end
B <= A;
C <= B;
Example Run
A = 1; B = 3; C = 7
A = 1; B = 3; C = 7
Process Execution
Process Execution
A = 1; B = 1; C = 1
A = 1; B = 1; C = 3
Example Run
Assignment statements
Example Process
begin
C = B;
B = A;
end
Example Process
Begin
end
C <= B;
B <= A;
Example Run
A = 1; B = 3; C = 7
A = 1; B = 3; C = 7
Process Execution
Process Execution
A = 1; B = 1; C = 3
A = 1; B = 1; C = 3
Order matters!
Example Run
Order does not matter!
Process
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With the @always keyword, you can make a process
like a continuous statement
module test (z, x, y)
output z;
input x, y;
assign z = x + y;
endmodule
module test (z, x, y);
output z;
input x, y;
reg z;
always @ (x, y)
begin
z = x + y;
end
endmodule;
Verilog Code be be written for:
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Simulation
 Create the corresponding circuit (logic diagram,
etc.)
Synthesis
 Create a simulation program
Some features are not available for synthesis. For
example: wait, initial, etc.
Sequential Design
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In sequential design, that includes flip-flops,
registers, etc., we will usually use non-blocking
assignments.
Verilog code: D flip flop
module dff_v (CLK, RESET, D, Q)
input CLK, RESET, D;
output Q;
reg Q;
always @ (posedge CLK or posedge RESET)
begin
if (RESET)
Q <= 0;
else
Q <= D;
end
event control
statement
process
Verilog
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In the body of a process, additional Verilog conditional
statements can appear.
 For example: if-else
if (condition)
begin
procedural statements
end
else if (condition)
begin
procedural statements
end
else
begin
procedural statements
end
Verilog for Sequence Recognizer
0/0
A
1/0
1/0
B
1/0
0/0
C
0/0
D
1/1
0/0
Present
State
Next State
x=0 x=1
Output
x=0 x=1
00
00
01
0
0
01
00
10
0
0
10
11
10
0
0
11
00
01
0
1
Verilog for Sequence Recognizer
RESET
Input
(X)
D
FF
Next
State
Determination
Logic
D
FF
Circuit State
CLK
Output
Logic
Output
(Z)
Verilog for Sequence Recognizer
module seq_rec_v (CLK, RESET, X, Z)
input CLK, RESET, X
output Z;
reg [1:0] state, next_state;
parameter A = 2’b00, B = 2’b01, C = 2’b10, D = 2’b11;
reg Z;
Verilog for Sequence Recognizer
// implements state storage
always @ (posedge CLK or posedge RESET)
begin
if (RESET == 1)
state <= A;
else
state <= next_state;
end
Verilog for Sequence Recognizer
// next state functionality implementation
always @ (X or state)
begin
case (state)
A:
B:
C:
D:
end
endcase
if (X == 1)
next_sate <= B;
else
next_state <= A;
if (X) next_state <= C;
else next_state <= A;
if (X) next_state <= C;
else next_state <= D;
if (X) next_state <= B;
else next_state <= A;
Verilog for Sequence Recognizer
// output functionality implementation
always @ (X or state)
begin
case (state)
A: Z <= 0;
B: Z <= 0;
C: X <= 0;
D: Z <= X ? 1 : 0;
endcase
end
endmodule
References
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Textbook, Mano and Kime, 4th edition.
Verilog Book by Peter Nyasulu