King Abdul Aziz University
Faculty of Computing and Info Tech
Computer Science Department
LAB MANUAL
CPCS 211
Digital Logic Design
Prepared By:
Aman Ullah
2012(1) - 1433
Term
Spring 2012
Lab 6: Combinational Circuit
Statement Purpose:
In this lab we shall discuss about the combinational circuits. We shall also learn how to design different
combinational circuits. Two of the basic combinational circuits, viz, adders and subtractors will also be
discussed.
Activity Outcomes:
The students will learn about





The combinational circuits
Adders-half adders and full adders
Subtractors-half subtractors and full subtractors
Converter circuits
Implementation of combinational circuits
Instructor Note:
The students should read the lab notes carefully and thoroughly. All the examples have been solved in an
easy to understand manner. They should not find it difficult to learn the topics given in these lab notes. The
students should try to solve all the exercises themselves that are given at the end of notes. These exercises
will certainly help them achieving the objectives of this lab.
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
Combinational Circuit:
 A combinational circuit consists of logic gates whose outputs at any time can be
determined only from the present combination of inputs.
 A combinational circuit performs a specific information processing operation fully
specified logically by a set of Boolean functions.
Adders:
 Digital computers perform a variety of information processing tasks such as arithmetic
operations.
 A combinational circuit that performs the addition of two bits is called a “half adder”
whereas a combinational circuit that performs the addition of three bits (two
significant bits and a previous carry) is called a “full adder”.
 Two half adders can be employed to implement a full adder.
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
Half Adders:
 The combinational circuit for half adder requires two inputs and two binary outputs.
 The input variables designate the augend and addend bits whereas the output variables
produce the Sum and Carry.
 The truth table for half adder is as follows:
Inputs
Outputs
X
Y
C
S
0
0
0
0
0
1
0
1
1
0
0
1
1
1
1
0
 The simplified Boolean functions for C and S are
C = XY
S = X’Y + XY’
 The logic diagram for these functions is as follows:
 The other implementation of half adder can be obtained by writing the Boolean
functions for S and C in Product of Sum form by writing Maxterms against 0’s in the
above truth table as
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
S = (X + Y)(X’ + Y’)
C = XY
(Draw K-Map for C and combine 1’s to get C’)
 The implementation of half adder in product of sum form is as follows:
 Now, we know that X + Y = X’ Y + XY’. So, using exclusive-OR gate, half adder
can also be implemented as
Full Adder
 A full adder is a combinational circuit that forms the arithmetic sum of three input
bits.
 It consists of three inputs and two outputs.
 Two of the input variables, denoted by X and Y represent the two significant bits to be
added. The third input Z represents the carry from the previous lower significant
position.
 The two outputs are designated by the symbols, S (for sum) and C (for carry).
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
 The binary variable S gives the value of least significant bit of the sum whereas the
binary variable C gives the output carry.
S = X’Y’Z + X’YZ’ + XY’Z’ + XYZ
C = XY + XZ + YZ
The implementation of full adder in Sum of Product form is as follows:
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
 In order to find the Product of Sum implementation of full adder, we combine 0’s in
the above K-maps and get
S = (X+Y+Z) (X+Y’+Z’) (X’+Y+Z’) (X’+Y’+Z)
C = (X+Y)(X+Z)(Y+Z)
 The implementation of full adder in Product of Sum form is as follows:
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
 A full adder can be implemented with two half adders and one OR gate as follows:
Subtractors
 The subtraction of binary numbers may be obtained by taking the complement of the
subtrahend and adding it to the minuend. By this method, the subtraction operation
becomes the addition operation requiring full adders for its machine implementation.
Half Subtractors
 A half subtractor is a combinational circuit that subtracts two bits and produces their
difference.
 It also has an output to specify if a 1 has been borrowed.
 If we designate the minuend by X and the subtrahend bit by Y, then there will be two
outputs i.e. D for difference and B for borrow.
 The truth table for half subtractor is as follows:
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
Inputs
Outputs
X
Y
B
D
0
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
 The simplified Boolean expressions for B and D are as follows:
D = XY’ + X’Y
B = X’Y
 The implementation of half subtractor in Sum of Product form is as follows:
 The implementation of half subtractor using exclusive-OR gate is as follows:
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
Full Subtractor
 A full subtractor is a combinational circuit that performs subtraction between two bits,
taking into account that a 1 may have been borrowed by a lower significant stage.
 This circuit has three inputs and two outputs.
 The three input X, Y and Z denote the minuend, subtrahend and previous borrow
respectively.
 The two outputs D and B represent the difference and borrow respectively.
 The truth table for full subtractor is as follows:
X
0
0
0
0
1
1
1
1
Inputs
Y
0
0
1
1
0
0
1
1
Z
0
1
0
1
0
1
0
1
Outputs
D
B
0
0
1
1
1
1
0
1
1
0
0
0
0
0
1
1
 The K-Maps for D and B are shown as follows:
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
Y
YZ
00
X
01
11
10
1
1
1
X
1
Z
D = X’Y’Z + X’YZ’ + XY’Z’ + XYZ
Y
YZ
X
00
01
11
10
1
1
1
1
X
B = X’Z + X’Y + YZ
Z
 The implementation of full subtractor in Sum of Product form is as follows:
 We can simplify the Boolean expressions for D and B as
D = X’YZ’ + XY’Z’ + XYZ + X’Y’Z
= Z’(X’Y + XY’) + Z(XY + X’Y’)
= Z’(X + Y) + Z (X + Y)’
= Z + (X + Y)
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
B = Z (X’
+
Y) + X’ Y
 Implementation of full subtractor using two half subtractors and one OR gate is as
follows:
Code Converter
 The availability of large variety of codes for the same discrete elements of information
results in the use of different codes by different digital systems.
 A conversion circuit must be inserted between the two systems if each uses different
codes for the same information.
 Thus a code converter is a circuit that makes the two systems compatible even though
each uses a different binary code.
BCD to Excess-3 Code Converter
 Since both these codes use four bits each to represent a decimal digit, there must be
four input variables and four output variables. The truth table relating the input and
output variables is shown below:
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
Input
BCD
B
0
0
0
0
1
1
1
1
0
0
A
0
0
0
0
0
0
0
0
1
1
C
0
0
1
1
0
0
1
1
0
0
D
0
1
0
1
0
1
0
1
0
1
Output
Excess-3
X
Y
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
W
0
0
0
0
0
1
1
1
1
1
Z
1
0
1
0
1
0
1
0
1
0
 Since BCD code exists for digits from 0 to 9, therefore the above truth tables contains
ten bit combinations for 0 to 9 digits.
 The remaining six bit combinations not listed in the above truth table are the don’t
care combinations.
 The K-Maps for the four output variables W, X, Y and Z are as follows:
C
CD
AB
00
01
11
10
1
1
1
00
01
11
X
X
X
X
10
1
1
X
X
A
B
D
So, W = A + BC + BD
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
C
CD
00
AB
00
01
11
01
11
10
1
1
1
X
X
X
1
X
X
1
X
A
10
B
D
So, X = B’C + B’D + BC’D’
C
CD
AB
00
11
01
1
1
01
1
1
11
X
10
1
00
A
X
10
X
X
X
X
B
D
So, Y = CD + C’D’
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
C
CD
AB
00
11
01
10
1
1
01
1
1
11
X
10
1
00
A
X
X
X
X
X
B
D
So, Z = D’
 In order to implement the above functions, we manipulate them algebraically in order
to use common gates for two or more outputs as
Z = D’
Y = CD + C’D’ = CD + (C+D)’
X = B’C + B’D + BC’D’ = B’(C + D) + BC’D’ = B’(C+D) + B(C + D)’
W = A + BC + BD = A + B(C + D)
 The logic diagram of the above expressions is as follows:
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
Exercise:
Design a combinational circuit that accepts a three bit number and generates an
output binary number equal to the square of the input number.
Example:
Construct a combinational circuit that multiplies two binary numbers, each two bits
long, and represented by a1, a0 and b1, b0.
Solution:
 The truth table for the required combinational circuit is as follows:
a1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Input
a0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
b1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Ouput
X
Y
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
1
0
1
1
0
0
0
1
1
1
0
0
Z
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
 The K-Maps for W, X, Y and Z are as follows:
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
b1
b1 b0
a1 a0
00
11
01
10
00
01
a0
1
11
a1
10
b0
So, W = a1 a0 b1 b0
b1
b1 b0
a1 a0
00
11
01
10
00
01
1
11
a1
1
10
a0
1
b0
So, X = a1 a0’ b1 + a1b1 b0’
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
b1
b1 b0
00
a1 a0
01
11
10
1
1
00
01
11
1
10
1
a1
1
a0
1
b0
So, Y = a1’ a0 b1 + a0b1 b0’+ a1 b1’ b0 + a1a0’ b0
b1
b1 b0
01
11
01
1
1
11
1
1
a1 a0
00
10
00
a0
a1
10
b0
So, Z = a0 b0
 The logic diagram for the above combinational circuit is as follows:
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
Exercise:
Repeat the above question to form the sum (instead of product) of two binary
numbers.
Solution:
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
Example:
Design a combinational circuit with four input lines that represent a decimal digit
in BCD and four output lines that generate the 9’s complement of the input digit.
Solution:
The truth table for the required combinational circuit is as follows:
Ouput (9’s Complement)
W
X
Y
Z
1
0
0
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
Don’t Care
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Input (in BCD)
B
C
D
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
 The K-Maps for W, X, Y and Z are as follows:
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
C
CD
AB
00
00
01
1
1
X
X
11
10
X
X
X
X
01
11
A
10
B
D
So, W = A’B’C’
C
CD
AB
00
01
00
01
1
1
11
X
X
A
10
11
10
1
1
X
X
X
X
B
D
So, X = BC’ + B’C
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
C
CD
00
AB
01
00
01
11
X
X
A
10
11
10
1
1
1
1
X
X
X
X
B
D
So, Y = C
C
CD
AB
00
11
01
10
1
1
01
1
1
11
X
10
1
00
A
X
X
X
X
X
B
D
So, Z = D’
The logic diagram for the required combinational circuit is as follows:
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
Exercise:
Design a combinational circuit that multiplies by 5 an input decimal digit represented
in BCD. The output is also in BCD. Show that the outputs can be obtained from the
input lines without using any logic gates.
Solution:
 The truth table for the required combinational circuit is as follows:
Input (in Binary)
F8
F4
F2
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
F1
0
1
0
1
0
1
0
1
0
1
0
1
S8
0
S4
0
Ouput (Decimal in BCD)
S2
S1
L8
L4
L2
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
1
0
1
0
1
Don’t Care
Don’t Care
CPCS-211 Digital Logic Design
L1
0
Term
Spring 2012
Lab 6: Combinational Circuit
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Don’t Care
Don’t Care
Don’t Care
Don’t Care
 The K-maps for the output variables are as follows:
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
Exercise:
Design a combinational circuit that converts a decimal digit from the 2 4 2 1 code to
the 8 4 -2 -1 code.
Solution:
 The truth table for the required combinational circuit is as follows:
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
 The K-maps for the output variables are as follows:
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
 The logic diagram for the required combinational circuit is as follows:
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
Exercise:
Design a combinational circuit that converts a four digit binary number to a decimal
number in BCD. Note that two decimal digits are needed since the binary numbers
range from 0 to 15 for four input bits.
Solution:
 The truth table for the required combinational circuit is as follows:
Input (in Binary)
W
X
Y
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Z
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
Ouput (Decimal in BCD)
E
W
X
Y
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
1
 The K-maps for the output variables are as follows:
CPCS-211 Digital Logic Design
Z
0
Term
Spring 2012
Lab 6: Combinational Circuit
CPCS-211 Digital Logic Design
Term
Spring 2012
Lab 6: Combinational Circuit
 The logic diagram for the required combinational circuit is as follows:
Assignment No 4
Due Date: April 17, 2012
Q. No. 1: Design a combinational circuit whose input is a four bit number and whose output
is the 2’s complement of the input binary number.
Q. No. 2: Design a combinational circuit that converts a decimal digit from 8 4 -2 -1 code to
BCD code.
Q. No. 3: Implement the following four Boolean functions using three half adder circuits.
D=A + B + C
E = A’BC + AB’C
F = ABC’ + (A’ + B’)C
G = ABC
Hint: Try to simplify these functions in the form of exclusive-OR operators.
Use Cedar logic simulator to draw all the circuits.
Note: Submit the assignment in proper way with title page. No late submission of
assignment will be entertained.
CPCS-211 Digital Logic Design