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Lab 10: Finite State Machines
Ian Callahan ([email protected])
Purpose
The goal of this lab was to create and implement a finite state machine based on the given
output of the system. The design was to be an asynchronous sequential circuit. An asynchronous
sequential circuit is a circuit where the outputs change directly in response to the change in the
inputs. In comparison to a synchronous sequential circuit, which depends on the clock signal for
the change in output, asynchronous sequential circuits are faster and processing change. For this
lab, it was decided that we would use a Mealy Machine to design the finite state machine. The
Mealy Machine requires less states and fewer inputs to perform the same action as a Moore
Machine. The only disadvantage is that a Mealy Machine is more difficult to generate the logic
for.
In this lab, we will generate a Mealy Machine to express the relationship between given
inputs and outputs. We will discuss the procedure taken to complete the lab. We will then create
a schematic of the machine virtually and create a waveform to predict the behavior of the system.
We will then create the finite state machine on a protoboard and analyze the output signals.
Finally, we will compare the simulated results and the generated results to verify the operation of
the finite state machine.
Procedure
The procedure for the lab was as follows:
1. First, we began by analyzing the initial input and output data given by Table 1.
A
0
0
1
1
B
0
1
0
1
Z
000000010000000100…
000001110000011100…
000111110001111100…
01111111011111110…
Table 1: This table illustrates the initial inputs and corresponding outputs given for the design of
the Finite State Machine.
2. From Table 1, we drew a state transition diagram showing the next state for each
combination of the present states and the input signals.
3. We analyzed which edge of the clock would be used to cause the output Z to change. We
also determined how many states were needed to implement our design as well as how
many state bits were needed.
4. Next, we drew a state transition table. It was given that we would be implemented D FlipFlops for out design. Therefore, we extended the state transition table to include the
required D inputs for the Flip-Flops.
5. We implemented K-maps to generate the logic for each of the outputs.
6. From the generated material, we created a sketch of the design. From the sketch, we
made a list of the number and types of logic components required for the design.
7. Next, we translated our sketch into a schematic by using the Graphic Editor of Quartus II.
We used the 7474 Flip-Flops for the D Flip-Flops and set the Presets and Clears to high.
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8. Once the schematic was complete, we created a waveform of all of the inputs and
outputs. We set Preset and Clear inputs to high and gave different clock signals to clock,
B, and A inputs. We then ran a simulation with the schematic and the created waveform
to generate the simulated outputs.
9. After the schematic was tested, we began to build the finite state machine on the
protoboard. To generate the clock signal, we used the 555 timer. We also used 7474 (D
Flip-Flop), 7408 (AND Gate), 7432 (OR Gate), and (4-to-1 Multiplexer) chips to create
the desired design.
10. Once the finite state machine was completed, we observed the output and clock signal on
the oscilloscope to ensure that the desired output was obtained, and we had our work
checked by a TA. We then optimized the circuit to minimize the length of wires required.
11. Finally, we connected the inputs clock, B, and A as well as the outputs Q0, Q1, Q2, and Z
to a Logic analyzer. Using the analyzer, we generated a display to illustrate that the
counter and the outputs were functioning properly.
Results
For the lab, we had to implement five different chips. The first chip that we used was the
74LS74A D flip-flop chip. The circuit diagram is shown in Figure 1. The second chip we used
was the 555 timer circuit. The circuit diagram is shown in Figure 2. The third chip we used was
the 74153 4-to-1 Multiplexer. The circuit diagram is shown in Figure 3. The fourth chip we used
was the 7408 AND Gate. The circuit diagram is shown in Figure 4. The last chip we used was
the 7432 OR Gate. The circuit diagram is shown in Figure 5.
Figure 1: This figure demonstrates the circuit diagram for a 74LS74A chip.
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Figure 2: This figure illustrates the circuit diagram for the 555 timer circuit.
Figure 3: This figure illustrates the pin configuration for the 74153 4-to-1 Multiplexer.
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Figure 4: This figure illustrates the pin configuration and logic diagram for the 7408 AND Gate.
Figure 5: This figure illustrates the pin configuration and logic diagram for the 7432 OR Gate.
Following the procedure, we created a transition diagram from the given input-output
relationship given by Table 1 (previously introduced). We determined that the output Z would
change based on the rising-edge of the clock. We also determined that the finite state machine
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would require eight states and it would require eight bits. The transition diagram was then used
to create a transition table. We determined that the most efficient way to sequence through the
states was to implement a three-bit counter. Therefore, the next state for each of the eight states
is the next number in a sequence of 0 to 7. From our knowledge gained from Lab 9, we know
that a counter can successfully be built by using D Flip-Flops. We then extended the transition
table to include the required D inputs for the Flip-Flops. The final transition table is shown
through Table 2.
A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
B
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Q2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Q1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Q0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Q(t+1)2 Q(t+1)1 Q(t+1)0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
Table 2: This table shows all of the input and output combinations.
Z
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
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From the transition table in Table 2, we created K-maps to determine the logic for the
output Z based on the inputs A and B. Table 3 shows the K-map for Z when A=B=0. Table 4
shows the K-map for Z when A=0 and B=1. Table 5 shows the K-map for Z when A=1 and B=0.
Table 6 shows the K-map for Z when A=B=1.
Q2\Q1Q0
0
1
00
0
0
01
0
0
11
0
1
10
0
0
11
0
1
10
0
1
Table 3: This table illustrates the K-map for Z when A=B=0.
Q2\Q1Q0
0
1
00
0
0
01
0
1
Table 4: This table illustrates the K-map for Z when A=0 and B=1.
Q2\Q1Q0
0
1
00
0
1
01
0
1
11
1
1
10
0
1
Table 5: This table illustrates the K-map for Z when A=1 and B=0.
Q2\Q1Q0
0
1
00
0
1
01
1
1
11
1
1
10
1
1
Table 6: This table illustrates the K-map for Z when A=B=1.
By examining the K-maps, the logic functionality can be from for Z for each of the
corresponding inputs. When A=B=0, Z=Q2Q1Q0. When A=0 and B=1, Z=Q2(Q1+Q0). When
A=1 and B=0, Z=Q2+Q1Q0. Finally when A=B=1, Z=Q2+(Q1+Q0). To implement these
equations, we determined that it would be best to feed the output signals into a 4-to-1
Multiplexer with the inputs being A and B. We created a sketch of the design for the finite state
machine and it is shown in Figure 7. From the sketch, we determined that we would need a
minimum number of gates and transistors, given by Table 7.
Figure 7: This figure illustrates a sketch of the design for the finite state machine.
Gate Logic Functionality
7474
D Flip-Flop
7432
OR Gate
7408
AND Gate
74153
4-to-1 MUX
Number of Gates
3
4
4
1
Number of Transistors
2
1
1
1
Table 7: This table illustrates the number and type of chips needed for the design.
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With all of this information, we were able to create a schematic by using the Graphic
Editor of Quartus II. We made the proper connections so that the D Flip-Flops would operate as
a three-bit counter. We made operations to the Qs to create the necessary outputs based on the
inputs. Finally, we connected all of the possible outputs and inputs into a 4-to-1 Multiplexer.
When possible, we used buses to condense the data. The schematic is shown in Figure 8.
Figure 8: This figure illustrates the schematic for the finite state machine.
After the schematic was complete, we generated a waveform with all of the nodes of the
schematic. We set Preset and Clear equal to high so that the Flip-Flop would depend on the clock
and D signals. We set clock to a clock signal of 20 ns, B to a clock signal of 320 ns, and A to a
clock signal of 640 ns. A and B were set to these clock signals so that the counter can go through
all eight states for each case. The waveform helps show that the design works in accordance with
the desired output. The resulting waveform that was simulated is shown in Figure 9.
Figure 9: This figure illustrates the waveform generated from the schematic.
With the schematic created and tested, we moved on to create the finite state machine on
the protoboard. We wired the protoboard in accordance with the schematic. For the clock signal,
we used the 555 timer. We used the resistor values of R1=3000Ω and R2=1500Ω. We used the
capacitor value of C=0.022µF. To calculate the period obtained by these resistors, we used the
following equation:
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𝑇 = .693(𝑅1 + 2𝑅2 )𝐶 (1)
Using equation (1), it can be found that the period for the clock signal is 91.476 µs.
Inputs A and B were connected to the inputs of the multiplexer. Switches were used to allow the
inputs to vary from high to low. When the switch is open, the signal is low, and when the switch
is closed, the signal is high. Then, the clock signal and the output Z were connected to the
oscilloscope to verify operation. Once the circuit was complete, the wire lengths were optimized
so that the smallest length of wire was used.
With the circuit complete, we wired the clock, A, B, Qs, and Z signal to an Intronix
LogicPort Logic Analyzer. We connected D0 to Q0, D1 to Q1, D2 to Q2, D3 to A, D4 to B, D5 to
Z, and Clock 1 to clock. We analyzed the circuit for each of the A and B combinations. Figure 10
shows the output Z when A=B=0. Figure 11 shows the output Z when A=0 and B=1. Figure 12
shows the output Z when A=1 and B=0. Figure 13 shows the output when A=B=1.
Figure 10: This figure illustrates the finite state machine inputs and outputs when A=B=0.
Figure 11: This figure illustrates the finite state machine inputs and outputs when A=0 and B=1.
Figure 12: This figure illustrates the finite state machine inputs and outputs when A=1 and B=0.
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Figure 13: This figure illustrates the finite state machine inputs and outputs when A=B=1.
Conclusion
The purpose of this lab was to design and implement a finite state machine based on the
given input-output relationship illustrated in Table 1. We determined that the most efficient way
to create the proper amount of states was to implement a counter by using D Flip-Flops. We then
generated logic outputs for each of the possible inputs of A and B. We wired those outputs to a
multiplexer that was triggered based on A and B. By comparing the waveforms that we
simulated and the waveforms that we generated, we were able to obtain similar results. The only
difference between the two waveforms was that the waveforms generated had a significantly
larger clock period. The reason that the clock period was larger was so that it would be easier to
measure the results. Overall, the finite state machine that we designed fulfilled the requirements
of the lab and was successful.
References
Professor Helen Li’s lecture slides
Circuit diagrams for circuits from Courseweb
Lab Partner: Brandon Jones