Thermal Dissipation in Bonded
Structures
Rajiv V. Joshi ,T. Smy1,
K. Banerjee2, A. Topol
IBM T. J. Watson Research Center
Yorktown Heights, NY
1University of Carleton, Ottawa, Canada
2University of California, Santa Barbara, CA
OUTLINE
• Introduction
• Multilayer Devices
¾ 3-D Thermal Modelling
¾ Self heating in SOI
3-D Thermal Modeling of Interconnects
•
• Temperature Measurement Techniques
• Real 3D structures
¾ Oxide Bonded
•
¾ Copper bonded
Thermal impact on Circuit Performance
• Summary
R. V. Joshi (2)
INTRODUCTION
• Considerable interest in increasing on die device density by
using wafer level 3D integration.
• One aspect of the new technologies that has to be addressed
is the thermal impact of the front and backend technology.
• Some of the issues that need to be investigated are:
¾ Self-heating effect on SOI wafers
¾ Joule heating in the backend (electrical resistance increases
with T – nonlinear).
¾ Low-k materials (Thermal conductivity scales with k).
¾ Heat flow through the interconnect (complex geometry).
¾ Use of thermal vias and design rules to minimize
temperature rises (optimization).
R. V. Joshi (3)
3-D ICs : Multiple Active Si Layers
( K. Banerjee et al., Proc. IEEE 2001)
z Advantages
z Reduce Interconnect Length
by Vertically Stacking Multiple
Si Layers
Optical I/O
Analog / RF
z Improve Chip Performance
z Reduce Chip Area
DRAM
z Heterogeneous integration
possible, e.g., memory, digital,
analog, optical, etc.
Distributed Memory
Logic
R. V. Joshi (4)
Partially Depleted SOI
•PROS
•
IBM's Choice for SOI
• Manufacturability, Compatibility & Scalability
• De-coupling VT from tSi
• Reduced Sensitivity to tSi
• Profile Can Be Tailored for Any Desired VT
• More Compatible with Bulk CMOS
• Potentially Better SCE Down to Leff < 0.1 μm
•CONS
• Floating-Body Effect
• DC I-V Kink
• Parasitic Bipolar Effect &
• Reduced VT Leakage
• Hysteretic VT Variation
• Self-Heating Effect
Gate Oxide
Junction
tSi
Depletion Region
R. V. Joshi (5)
Self-Heating in SOI
• Self heating in SOI increases device junction temperature
• Modeled for single channel FET using 1-D thermal
conduction model (Su et al)
• Analysis using 2-D heat conduction through SiO2 for
simple single channel devices (Goodson et al.)
• Device geometries studied in the literature are not representative
of those typically used in high performance, large fan out circuits
R. V. Joshi (6)
Self Heating Examples
IS U
FXU
FPU
FXU
• Circuits with high power densities are prone to self-heating
¾ Clock buffers, I/O, Large drivers with high fan-out etc.
IS U
FPU
ID U
ID U
LSU
L3 Directory/Control
IF U
BXU
L2
LSU
L2
Chip Floorplan
•
IF U
BXU
L2
Chip Thermal Profile
POWER 4 Server: 2 CPU and CACHE (CPU can be hotter than CACHE)
R. V. Joshi (7)
Circuits Used for Analysis
Clock Tree
Output Buffers : NFET width - 2800μm
NFET fingers - 280
PFET width - 5600μm
PFET fingers - 280
Output load - 30pf
(wire + device)
PFET
NFET
R. V. Joshi (8)
Numerical Model for Thermal Analysis
• Use of continuum based thermal analysis
• Analysis of:
¾ Temperature field in device geometry by solving
λ T+q=0
numerically 3-D poisson's equation...
(where T -temperature, q -heat/volume, λ-thermal conductivity)
• Assumptions
¾ Heat dissipation in vias and MCBAR neglected due to
smaller volume
¾ Reduction of thermal conductivity due to micro-scale
effect is ignored
T
=1°C
Boundary Conditions:
z = -4μm
λ T
= C(T – To)
z = LM
LM(last metal)
Adiabatic on sides (x,y)
Δ Δ
Δ
R. V. Joshi (9)
Physical Design Used in the
Thermal Model
Layer
BOX
STI
Body
Channel
PC
MCBAR
CA
M1
V1
M2
V2
M3
V3
M4
V4
M5
Thickness
(μm)
0.4
0.2
0.2
0.1
0.2
0.3
0.6
0.4
0.7
0.4
0.7
0.5
0.7
0.6
0.7
0.8
Width
(μm)
0.15
0.26
0.25
0.25
1.1
0.44
1.35
0.5
2.24
0.5
1.35
0.75
2.6
Material
Thermal
Conductivity
(W/m-°C)
SiO2
SiO 2
Si
Si
Silicide
Tungsten
Tungsten
Cu / Al
C u / Al
Cu / Al
Cu / Al
Cu / Al
Cu / Al
Cu / Al
Cu / Al
Cu / Al
1.4
1.4
120
120
40
170
170
390 / 210
390 / 210
390 / 210
390 / 210
390 / 210
390 / 210
390 / 210
390 / 210
390 / 210
Volumetric
heating
(mW/ μm3 )
0.06**
0.0136
0.0218
0.0268
0.0444
0.0154
**heat dissipation per μm of channel width.
R. V. Joshi (10)
Temperature Distribution
• Four finger active
• Metal interconnect (MCBAR to M5) with four fingers active.
¾High temperatures are limited to body compared to interconnects
SiO2 Dielectric (k = 1.4 W/m-K)
Copper Interconnect
12
TemperatureRise (°C)
10
8
6
Junction
M1
4
2
Bulk Devices
0
0
2
4
6
Number of Active Fingers
R. V. Joshi, S. Kang, C. Chuang,, SISPAD 2001, pp. 242-245.
8
10
R. V. Joshi (11)
Temperature Measurement Techniques
¾ Use of Poly gate resistor as a sensor for temperature rise
•
Device Leakage Based Temperature Measurement
R. V. Joshi (12)
EXPERIMENTAL
¾ Use of Poly sensor for temperature rise
• Four Point Probe – 2 Pads for voltage, 2 Pads for current for poly
sensor
• Measurement of poly resistance due to self-heat
• Calibrate the poly resistance as a function of chuck temperature.
Temperature-power curves measured on two die of the same wafer
5
4.5
Temperature change (oC)
4
die (4,4)
3.5
3
2.5
2
1.5
lot: 1FC28I41BC
wafer: VV14EXY
macro: RJ_TRGATETEMP
device: PFET
condition: only sensor active
die (5,5)
1
0.5
0
0
90 nm Node
20
40
60
80
Power (μW)
100
120
140
R. V. Joshi (13)
Temperature Measurement Techniques
¾ Use of Poly gate resistor as a sensor for temperature rise
¾
Device Leakage Based Temperature Measurement
R. V. Joshi (14)
Leakage Based Temperature Modeling
• Leakage varies super linearly with
temperature and power supply voltage
– However, on chip variations of temperature and
voltage are limited
– Leakage as a function of temperature and voltage
is modeled as a second order
I ( Δ V , Δ T ) = I ( 0 , 0 )[ 1 + a 1 Δ T + a 2 Δ T
+ b1 Δ V + b 2 Δ V
2
2
+ c1 Δ T Δ V ]
Su et al.,” Full chip lekage estimation, considering power supply and
temperature variation” ACM Intl. Low Power Symp. 2003, pp.210-215.
R. V. Joshi (15)
Results: Thermal profile
Thermal map of 9mm x 9mm ASIC chip
Su et al.,” Full chip lekage estimation, considering power supply and
temperature variation” ACM Intl. Low Power Symp. 2003, pp.210-215.
R. V. Joshi (16)
3-D Modeling of Interconnects
• 3-D Temperature Modeling for Interconnects:
• Development of a tool to model thermal effects
• Impact of various variables on Temperatures
¾ Joule heating in the backend (electrical resistance increases
with T – nonlinear).
¾ Low-k materials (Thermal conductivity scales with k).
¾ Heat flow through the interconnect (complex geometry).
¾ Use of thermal vias and design rules to minimize
temperature rises (optimization).
D. Celo, et al.,” Backend implications for thermal effects in 3D integrated SOI
structures,” Advanced Interconnect Conference, 2003, pp.200-206.
R. V. Joshi (17)
Modeling approaches
• A number of approaches to the analysis of this heating in
electrical devices have been taken including analytical and
numerical models.
• The problem is quite complex with a need to solve both the
device heating on the surface of the wafer and the line heating in
the backend itself.
• The physics involved in solving for the conductive heat flow in
a VLSI structure requires solving the following partial differential
equation:
•gdev – constant, α = TCR
R. V. Joshi (18)
Atar – A thermal simulator
• Our solution to this problem is a simulator that given a
technology description and layout information will automatically
generate a 3D model of the device, discretize the model, and
solve for the temperature distribution in the device.
• Atar is thermal simulation tool that uses a technology
description and layout information to automatically generate a full
3D model, complete with discretization, and then solves for the
temperature distribution.
• Very flexible non-uniform, multi-model meshing allowing for
meshes spanning the deep-submicron to the package.
• Produces a self-consistent solution incorporating the
temperature dependance of the ohmic heating in the lines.
D. Celo, et al.,” Backend implications for thermal effects in 3D integrated SOI
structures,” Advanced Interconnect Conference, 2003, pp.200-206.
R. V. Joshi (19)
3D Silicon on Insulator Technology
• 3D integration scheme
• Bonding of SOI based devices directly on top of the backend of
SOI devices.
• The bonding layer used in this scenario is a thin dielectric layer
(0.3 mm thick).
R. V. Joshi (20)
Atar Model of 2 layer device
¾ Side and perspective view of Atar model with filling material
being removed
Side view
perspective view
R. V. Joshi (21)
Atar Model of 4 layer device
• Perspective view of four layer structure with bonding layers
shown.
R. V. Joshi (22)
Results: Typical Contour Plots
• Temperature contours simulated with Atar for two layer device.
Side View
top Device View
R. V. Joshi (23)
Results: Joule heating in the backend
• Volumetric heat dissipation in the metal were assigned varying from
0.0136 to 0.0444 mW/μm3 corresponding to M1 through to M4.
• TCR (Temp. Coeff. Of resistivity) value of Copper = 0. 43%/K
• Temperature increase due to the effect of ρ=f(T) is in the range of 6% for a
structure with two stacked devices and increases for number of device
stack increases.
D. Celo, et al.,” Backend implications for thermal effects in 3D integrated SOI
structures,” Advanced Interconnect Conference, 2003, pp.200-206.
R. V. Joshi (24)
Temperature as Function of the Number of Device Layers
• Plot of the nodal temperatures in the vertical z-direction from 10
μm below the silicon to the top of the backend
• Four models with 1-4 Device Layers
• Three and four level devices are becoming quite hot
(unaccaptable)
•Temp drop as a function z is due to the heat spreading to ambient
R. V. Joshi (25)
The Effect of low-k Materials
• Much lower thermal conductivity then SiO2.
• Two device layer structure plotted in z-direction variety of
thermal conductivities.
• Dramatic increase in temperature rise.
R. V. Joshi (26)
The Effect of low-k Materials
• Much worse for one to four stacked devices
• 75K rises are occurring with a 25% reduction in the thermal
conductivity of the backend material for even two layer device
• Three and four level structures above 200K rises
R. V. Joshi (27)
Removing Local Interconnect Layers
• Two device layer structure
• Linear Variation as local interconnect layers removed.
• Almost 50% reduction in temperature of top device.
•Larger no. metal layer means more oxide on the active device.
• Thicker oxide means increase in temperature.
R. V. Joshi (28)
Off-setting the Top Device
• Two device layer structure
• Two cases 1) bottom device powered; 2) bottom device off.
• Substantial drop in temperature is obtained if the device is
offset by 20 μm or more
• Cooling effect at zero offset due the local interconnect for
case 2 (lower device off).
R. V. Joshi (29)
Device Layout and Backend Structure
• The examples before were worst case simulations (stacked
high powered devices)
• Possible solutions to lower these temperature rises?
• Reduce the number of local layers of interconnect from 4 to 3-1
and decrease thermal resistance to Si substrate.
• Use design rules to disallow stacking and forcing a minimum
offset between devices.
• Use of metal lines as heat spreaders and thermal vias.
D. Celo, et al.,” Backend implications for thermal effects in 3D integrated SOI
structures,” Advanced Interconnect Conference, 2003, pp.200-206.
R. V. Joshi (30)
Effect of Nearby line
• Atar model built with upper layer metal line present.
• Two cases powered and un-powered bottom device.
• This line can have one of two effects on the simulation.
• Heat Spreader (line un-powered)
• Heater (line powered)
R. V. Joshi (31)
Device Layout and Backend Structure
• Contour plot depicting heat spreading for un-powered line.
• Significant raising of the device temperature by powered
line.
D. Celo, et al.,” Backend implications for thermal effects in 3D integrated SOI
structures,” Advanced Interconnect Conference, 2003, pp.200-206.
R. V. Joshi (32)
Device Layout and Backend Structure
• Offset of 100 μm is need to reduce the heating effect to
negligible level.
• Cooling effect less significant.
R. V. Joshi (33)
Low Temperature Fusion Bonding
GLASS
SiO2
Bonded Interface
10 nm
Si
• Low temperature fusion
bonding (≤ 300 °C) used
to attach top circuit layer
to new substrate
• No non-standard
materials introduced into
final bonded interface
K. W. Guarini et al., “ The impact of wafer-level, layer transfer
on high performance devices and circuits for 3D IC fabrication,”
ECS Symp. 2003 Presentation.
IR image
R. V. Joshi (34)
Thermal Impact on Device/Circuit Performance
•
•
•
SOI BOX thickness: ~150 nm (originally) Æ 500 nm (after transfer)
Long-channel FET and back-end characteristics undisturbed
Some degradation in short channel device behavior attributed to device
self heating
LINEAR
SATURATION
K. W. Guarini et al., “ The impact of wafer-level, layer transfer on high performance devices
and circuits for 3D IC fabrication,” ECS Symp. 2003 Presentation.
R. V. Joshi (35)
•Thermal Impact on Device/Circuit Performance
Input power
density 0.1
mW/μm2
• SOI temperature
depends strongly on
BOX thickness and
heater size
• Clock buffer circuit
performance degrades
1.2 % per 10 oC change
in SOI temperature
R. V. Joshi (36)
Analytical Die Temperature Model
(1)
z Temperature Rise of
•
•
•
P2
the jth Active Layer
in an n-layer 3-D Chip
Si_2
P1
j=2
z
Cu + ILD
Si_1
Package
⎡ ⎛ n Pk ⎞ ⎤
ΔT j = ∑ ⎢Ri ⎜ ∑
⎟⎥
i =1 ⎣ ⎝ k = i A ⎠ ⎦
j
Cu + ILD
n = Total Number of
Active Layers
j=1
z
Ri = Thermal Resistance
Between Adjacent Layers
z
Pk = Power Dissipation
in the kth Layer
Heat Sink
z No Interconnect Joule Heating
( S. Im and K. Banerjee IEDM 2000)
R. V. Joshi (37)
Case
Case Study
Study :: Wafer-Bonded
Wafer-Bonded Two-Layer
Two-Layer 3-D
3-D ICs
ICs
Case I
Case II
(P. Ramm et al., 1997)
Cu + ILD
2 μm
Cu + ILD
Inter-Wafer
Via
Si_2
Glue
(A. Fan et al., 1999)
10 μm
Layer
Si_2
Cu
Cu + ILD
Inter-Wafer
Via
Air Cu Air
Cu
1.4 μm
Cu + ILD
Si_1
550 μm
z Wafer Bonding with Glue Layer
Si_1
z Metal Thermocompression Bonding
(Usage of polymer adhesive)
( S. Im and K. Banerjee IEDM 2000)
R. V. Joshi (38)
Case
Case Study
Study :: Wafer-Bonded
Wafer-Bonded Two-Layer
Two-Layer 3-D
3-D ICs
ICs
Interconnect Joule
Full
Full Chip
Chip Simulation
Simulation
Heating Included
Temperature [°C]
400
Tmax (Case I)
TSi_2 (Case I)
Tmax (Case II)
350
TSi_2 (Case II)
Each Layer Based on
ITRS 100 nm node
300
250
TSi_1 (Case I & II)
200
150
Φ2D < Φ3D < 2 Φ2D
Φ2D= 0.3 W/m2
•Φ3D
0.30
0.40
0.50
0.60
Power Density (3-D) [W/mm2]
Heat sink- Si_1 layer only.
Thus, Tmax occurs at top
layer
( S. Im and K. Banerjee IEDM 2000) R. V. Joshi (39)
Case
Case Study
Study :: Wafer-Bonded
Wafer-Bonded Two-Layer
Two-Layer 3-D
3-D ICs
ICs
Temperature
Temperature Distribution
Distribution
420
404 °C
Temperature [°C]
Case I
399 °C
400
380
Case II
360
340
Si_2
320
Si_1
300
317 °C
Case I
280
0
5
10 15 20 25 30
Distance from Substrate [μm]
Φ3D ≈ 2 Φ2D
( S. Im and K. Banerjee IEDM 2000)
317 °C
Case II
R. V. Joshi (40)
Impact of Electrothermal Coupling on 3D ICs
(K. Banerjee et al., IEDM 2003)
R. V. Joshi (41)
Summary
• 3-D thermal analysis shows significant coupling between
adjacent fingers of multi-finger SOI devices. The junction
temperature rise in multi-finger devices was a factor of
three higher than single finger devices.
• Junction temperature rise in SOI due to self-heating in
high power devices like clock buffers can be 100-200C.
• Conduction from the channel can raise the M1 temperature
10°C above that of the silicon.
• Self-heating degrades the performance incrementally.
R. V. Joshi (42)
SUMMARY OF 3-D Modeling
• Simulation results clearly indicate the importance of the
thermal effects in 3D integration structure.
• The inclusion of Joule heating in the backend is found to be
important.
• Detailed thermal analysis needs to be performed in early design
stages including choice of materials.
• Layout issues and design rules need to be analysed in the light
of thermal impact.
R. V. Joshi (43)
SUMMARY OF 3D (Cu BONDED)
z Analytical Modeling and Full Chip Thermal Analysis of
3-D ICs
z Peak Temperature Increases Linearly with Number
of Layers
z Cu-Bonded 3-D ICs Show Better Thermal
Performance
z Advancement in Chip Packaging / Cooling Technology
and Thermal Properties of Low-k Dielectric Materials
Needed for Both 2-D and 3-D ICs
( S. Im and K. Banerjee IEDM 2000) R. V. Joshi (44)
Summary
• Temperature Measurement techniques are shown
to evaluate device/chip temperatures.
• 3-D Real devices using bonded Si show some signs of
Self-heating effect (as an indirect measure of degradation
in circuit/device performance).
•
Electrothermal coupling is important in predicting the
junction temperature.
• Further Work is essential to understand the thermal
effect at device and circuit level.
R. V. Joshi (45)
References
P. Ramm et al., “ 3-D metallization for vertically integrated Circuits,” Microelectronics Eng.
37/38, 1997, pp.39-47.
R. J. Gutmann et al.,”3D Ics: A technology platform for integrated systems and opportunities for
new polymeric adhesives,” Proc. IEEE Intl.of Conf. On Polymers and adhesives in
microelectronics and photonics, 2001, pp.173-180.
K. W. Guarini et al.,” Electrical Integrity of state of the art 0.13 mm SOI CMOS devices and
circuits transferred to 3-D integrated circuit fabrication,” IEDM Tech Digest, 2003, pp. 943945.
K. W. Guarini et al., “ The impact of wafer-level, layer transfer on high performance devices and
circuits for 3D IC fabrication,” ECS Symp. 2003 Presentation.
D. Celo, R. V. Joshi, and T. Smy,” Backend implications for thermal effects in 3D integrated
SOI structures,” Advanced Interconnect Conference, 2003, pp.200-206.
Su, Lisa T. et. al., IEEE Transactions on Electron Devices, Vol. 41, No. 1, Jan 1994, pp. 69-75.
Workman, Glen O. et. al., IEEE Transactions on Electron Devices, Vol. 45, No. 1, Jan 1998,
pp.125-133.
R. V. Joshi et al.,” 3-D thermal analysis for SOI and its impact on circuit performance,” Proc. of
Int.Conf. Of Semiconductor Processes and Devices (SISPAD), 2001, pp. 242-245.
R. V. Joshi et al.,” A novel temperature measurement technique for sub-100 nm technologies,”
US Patent 7176508, Feb 13, 2007.
R. V. Joshi (46)
References
K. Guarini, A. Topol, V. Chan, K. Bernstein, L. Shi, R. Joshi, W. E. Haensch, M.
Ieong ,” 3D IC technology capabilities and applications,”3D Architectures for Semiconductor
Integration and Packaging Conference April 13-15, 2004.
R. Rehman and R. Reif,” Thermal analysis of 3D integrated circuits,” Proc. of International
Interconnect Conf., 2001, pp. 157-159.
M. Ieong, K. Guarini, V. Chan, K. Bernstein, R. V. Joshi, J. Kedzierski, W. Haench .,” Three
Dimensional CMOS Devices and Integrated Circuits,” Proc. of CICC 2003.
Su et al.,” Full chip leakage estimation, considering power supply and temperature
variation” ACM Intl. Low Power Symp. 2003, pp.78-83.
R. V. Joshi (47)
Relevant Publications
z S. Im and K. Banerjee, "Full chip thermal analysis of planar (2-D) and
vertically integrated (3-D) high performance ICs," IEEE International
Electron Devices Meeting (IEDM), pp. 727-730, 2000.
z K. Banerjee et al., "3-D ICs: A novel chip design for improving deep
submicron interconnect performance and systems-on-chip integration,"
Proceedings of the IEEE, Vol. 89, pp. 602-633, 2001.
z K. Banerjee, S-C. Lin, A. Keshavarzi, S. Narendra and V. De, “A Selfconsistent junction temperature estimation methodology for nanometer
scale ICs with implications for performance and thermal management,”
IEEE International Electron Devices Meeting (IEDM), pp. 887-890, 2003.
R. V. Joshi (48)