255
IEEE TRANSACTIONS ON COMPUTERS, VOL. C-34, NO. 3, MARCH 1985
Dynamic
Accessibility Testing and Path Length
Optimization of Multistage Interconnection Networks
DHARMA P. AGRAWAL,
SENIOR MEMBER, IEEE, AND
JA-SONG LEU,
STUDENT MEMBER, IEEE
mutations [9], [10], algorithmic adaptability characteristics
[11], and understanding relative advantages and disadvantages of MIN's [12]. But not much attention has been paid to
the aspect of fault tolerance which is crucial to the successful
operation of a multiple processor system. It has become
extremely important, as MIN's are considered the heart of
parallel systems. This paper is concerned with the faulttolerant capability of MIN's when employed to provide interprocessor communication in a multiprocessor environment.
The network should be implemented in such a way that a
noncatastrophic fault may not force a complete shut-off and
the system should continue working with reduced capacity.
This graceful degradation characteristic is not only dependent on the processors failure, but also on the MIN's.
Similarily, the path length required to provide a logical link
between two processors indicates the time delay involved in
transmitting the information from a source to any desired
destination.
Thus, average path lengths in both MIN's and
Index Terms -Adjacency matrix, average distance, connetworks (SSIN's) [13] seem to
interconnection
single-stage
nectivity, dynamic full access capability, graph model, multistage
interconnection networks, reachability matrix, stuck-at faults. be a good representative of their communication delays.
The type of multiple processor systems we are concerned
with is shown in Fig. 1 [1], [14]. In this system model, the
PE's with their private memory modules provide desired parI. INTRODUCTION
allelism while PE-to-PE transfer is achieved through the
R ECENT advances in VLSI technology have encouraged MIN. Thus, all PE's are connected to both sides of the netthe use of multiprocessor and multicomputer systems work so each PE can transmit data via the network input side
with a large number of processing elements (PE's) and while the output is useful in receiving data from another PE.
A brief introduction of the MIN's and an overview of
memory modules (MM's). In such systems, various techniques are utilized to support restructurable data paths existing testing techniques is covered in Section II. Our fault
between the PE's and MM's. Thus, the intercommunication model including multiple stuck-at-faults at input-output
is becoming an increasingly complex but inevitable issue. lines and control lines is described in Section III. A generSeveral design techniques for the interprocessor commu- alized test procedure and the use of adjacency and reachnication have been reviewed [1] and some of them have been ability matrices are illustrated in Section IV. Section V
constructed. The current trend is to employ multistage inter- outlines a procedure for computing the static average path
connection networks (MIN's) which requires segmentation length under various faulty conditions. Section VI provides
of the network into several stages, with each stage partially an insight to the optimum design methodology of MIN's
so that a larger number of faults can be tolerated. Finally,
satisfying the input-output connection requirements.
Various design issues of MIN's have been covered in concluding remarks are included in Section VII.
the literature. The main emphasis has been in finding their
equivalence and nonequivalence and comparing their permutation capabilities [2]-[8], designing for conflict-free per-
Abstract -The emergence of multiple processor systems has
seen the increased use of multistage interconnection networks
(MIN's), built with several stages of 2-input 2-output switching
elements (SE's). The connectivity and fault tolerance of these
networks are important problems as MIN's are expected to be
the heart of these systems. This paper employs a versatile graph
model of an SE that could represent all possible stuck type terminal faults at the control lines and input/output data lines. This
technique leads to a graph model of a given MIN, amenable to
testing of its dynamic full access (DFA) capability. The basic
strategy of employing adjacency and reachability matrices enables
testing under various combinations of multiple faults. Simulation
of various networks is carried out to evaluate the average path
lengths which illustrates the effect of connection pattern on the
network performance. A design methodology for implementing a
class of 2V-input 2V-output networks with m stages (m < n) of
2 x 2 MIN's is also outlined so that DFA capability and the
maximum availability could be ensured. Optimality of such a
network under the presence of faults is verified by the simulation
results that show a negligible increase in the average path length.
Manuscript received January 5, 1984; revised July 27, 1984. An earlier
version of this work was presented at the Fourth International Conference on
Distributed Computing Systems, San Francisco, CA, May 14-18, 1984.
The authors are with the Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27695.
II. MULTISTAGE INTERCONNECTION NETWORKS AND EXISTING
TESTING TECHNIQUES
Several of the proposed MIN's have been designed using
2 x 2 SE as a basic building block. A simple representation
of such an SE is shown in Fig. 2(a) and its two possible states
0018-9340/85/0300-0255$01.00 © 1985 IEEE
2EEE TRANSACTIONS
256
N
1CC
m
P
I.
P
0
I
0
L
B
Ab
-a
~006
N
M
*
m
ra
PE
P
I
9
-G
Interconnection Network
Fig. 1. Multiple processor system organization.
(a)
c
X1 o-
=
c
o
°Y,
I
xlo
=
=1-
1
/
Y
y
xl
X2
X
---(
2,O-
y2
Y2
(c)
(b)
H
E-4
H
(d)
Fig. 2. (a) Switching element. (b) Parallel connection with C
(c) Cross connection with C = 1. (d) Baseline network for N = 8 (n
0.
=
3).
illustrated in Fig. 2(b) and (c). The parallel and cross
connection of an SE is determined by the logical level applied
at its control line. An N-input N-output MIN (for simplicity,
N is assumed to be some power of 2; say N = 2C) is constructed in several stages with each stage consisting of
N/2 SE's. The links between successive stages of the network are assigned in such a way that each input could be
connected to as many outputs as possible. An n-stage network can provide a path between any of the N-inputs and to
each one of the N-outputs and such a MIN has been reproduced from [2] in Fig. 2(d). The control lines are not
shown for clarity of the diagram.
The problem of communication and data transfer rate tends
to be increasingly critical when either the network load is
heavy, or when some of the lines happen to be faulty. A link
between any input and an arbitrary output cannot be established if a conflict occurs or a required line happens to be
faulty. In such situations, if data are to be transferred between
any two PE's of Fig. 1, the data may have to be passed to one
are
c-34,
NO.
3,
MARCH
1985
or more intermediate PE's before reaching the destination
PE. These considerations encouraged us to look into MIN's
with m stages (m n).
The fault diagnosis for a class of switching networks has
been described by Operfman and Tsao-Wu [15]. They utilize
a sequence of tests to ensure the correct operation of the two
possible states of each SE. An unalterable state of an SE
means that the control lines are permanently stuck at 0 or 1.
Shen and Hayes [ 16] have used a graph model for demonstrating the effect of faults at the control lines. In their fault
model, they consider the output side to be fed back to the
corresponding input lines, as rerouting of data through the PE
is possible. They have modeled an SE by a node and each
interconnection link is represented by a directed edge connecting the nodes. A faulty SE is indicated by a node partitioned into two sections. Their main concern is to test
whether, under a given fault condition, each input of the
network could be logically connected to any one of the network outputs in a finite number of passes. They define this
property as the dynamic full access (DFA) capability. The
control line faults are said to be critical if they destroy the
DFA characteristics. The same model has been used [17] in
analyzing the fault tolerance of various redundant MIN's.
The major shortcoming is to assume the presence of a fault(s)
only at the control input(s). In Section III, we propose a
graph model which overcomes this limitation.
Narraway and So [18] have considered a diagnosis model
for a general switching network constructed with k-input
k-output switches (k > 2). Their basic strategy is to use
known good connecting data paths in identifying good
switches and use this progressively in defining a faulty connecting path. They do not consider faults at the control lines.
In another recent paper, Wu and Feng [19] have described a
simple testing technique for MIN's. In their paper, they have
illustrated 16 different possible states of an SE and they
consider only two states (parallel or cross connected) as faultfree situations and all others are interpreted as faults in the
SE's. In their novel scheme, they require only four sequences
for testing any MIN. In fact, only two complementary sequences are needed and are repeated for two different control settings of the network, one for parallel-connected
and another for cross-connected modes. Each sequence is
selected in such a way that a one-out-of-two code is used in
space. This means that only one input (and hence one output)
of each SE is made one while the other remains zero.
It is well known that the probability of logical faults inside
an IC chip is quite small and most of the faults occur at the
pins [20]. Thus, it is more important to consider stuck-at
faults at inputs, outputs, and control lines of the SE's. Wu and
Feng's algorithm can still test faults at the input and output
line(s) of SE(s). Further utilization of the same sequences in
testing control line fault has been covered in [21]. Another
model for the control line faults in Omega [22] and other
networks has recently been considered in [23]. Their optimum -test sequence allows location of single-stage multiple
faults and is helpful in removing the faulty SE's, if a single
IC chip constitutes a stage. In another recent work [24],
design procedures for (2n - 1) stage Benes type network
[15] that could tolerate single and multiple faults at the control lines have been outlined. A comprehensive review of
-
TH
h
ON COMPUTERS, VOL.
257
AGRAWAL AND LEU: MULTISTAGE INTERCONNECTION NETWORKS
testing techniques has appeared in a recent publication [25].
A comparison of various redundant networks has been given
in [26]. In this paper, we evaluate the DFA capabilities of
n-, single, and m-stage (m < n) MIN's under stuck-at faults
at the control lines as well as at the inputs and outputs of
the SE's.
Y.
-1
x'-1
I
X2z~~~~~:
(a)
x
III. FAULT MODEL
y
X2
The model for a 2-input 2-output SE of Fig. 2(a) is shown
Y2
in Fig. 3(a) [5], [6]. This graph model is based on the connectivity property between the input lines X1 and X2 and
(b)
output lines Y1 and Y2 of the SE. Each one of them is assigned
x1
y1
a node. As X1 (X2) of these [Fig. 2(a)] can be connected to
either Y, or Y2 (Y2 or Y1), these are shown by the directed edges
in the graph model of Fig. 3(a). It is worth mentioning that
the graph model of Fig. 3(a) [6] resembles the regular SW
X2,
2
Banyan network [27] in appearance. But, instead of using the
(c)
SE of Fig. 2(a), the Banyan is designed with individually Fig. 3. (a) Graph model of the SE of Fig. 1(a). (b) Graph model of the SE
controlled paths and its graph shows the actual link pattern.
when C S-a-O. (c) Graph model of the SE when C s-a-I.
Similarly, the graph model of cross-bar switches [28] utilizes
one edge for each cross-point and a single switch fault removes an edge in the graph. In this way, our model of a
x1
s- '
2-input 2-output SE is altogether different from the Banyan
y1
network.
x
Y2
X2
-%(
Considering the SE of Fig. 2(a) again, it could be in either
(c)
of the two operating modes, if no fault is present. But when
(a)
(b)
the control line is stuck-at-zero (s-a-0), the graph of Fig. 3(a)
is reduced to as shown in Fig. 3(b). A similar modification is
Y1.
. X1
Y1 .
x1
shown in Fig. 3(c) whenever the control line is s-a-1. The
stuck-at faults at the input and output lines of an SE have to
Y22
Y2
y2e
be treated in a different way. If a line is faulty (s-a-a,
a E 0, 1), then the line cannot be used to transmit any data.
(d)
(e)
(f)
This is reflected in the graph model by removing the corre* xI
sponding node and hence eliminating all the edges conY1 * Xx 1
necting the node. This is shown in Fig. 4(a) for s-a fault at
one of the input lines while Fig. 4(b) illustrates the model
X2
Y2
x2./
_l
*X2
when a fault is present at one of the output lines. Multiple
(i)
(g)
(h)
are
E
faults represented by a, ,B, and y (a, /3, y 0, 1). Models
4.
Fig.
model
of
the
SE
X1
(a)
Graph
when
s-a-a.
model of the SE
(b)
Graph
two
for the
possible double faults are shown in Fig. 4(c) and
when
s-a-a. (c) Graph model of the SE when X2 s-a-a and Y2 s-a-,B.
Y2
Faults
at
the
two inputs and outputs lead to the model
(d).
(d) Graph model of the SE whenX, s-a-a andX2 s-a-,8. (e) Graph model of the
shown in Fig. 4(e), while faults at all the input and output
SE when X2 s-a-a, Y, s-a-,l, and Y2 s-a--y. (f) Graph model of the SE when
control s-a- 1 and X2 s-a-a. (g) Graph model when control s-a-O. and Y1 s-a-a.
lines of an SE eliminate all the nodes from the model. If the
(h) Graph model when control s-a- 1, Xl s-a-a, and Y2 s-a-,l. (i) Graph model
control line is stuck-at-0 or -1, and one of the input or output
when control s-a-a, Y, s-a-fl, and Y2 s-a-y.
lines is also s-a-a, then the graph models are reduced as
shown in Fig. 4(f) and (g). Two possible combinations of
faults with the control line s-a-a and two of the input/output
In this way, once the SE's have been appropriately
lines s-a-a are given in Fig. 4(h) and (i). In this way, modeled, the analysis is similar for SE's with and without
Figs. 3(b) and (c) and 4(a)-(i) represent a reduced graph broadcast capability. For conciseness of the text, we will be
model under all single and multiple faults in an SE.
considering the MIN's implemented with SE's having only
The model of Fig. 3(a) could also be used [5], [6] to repre- two valid states, i.e., without having any broadcast facility.
sent the upper and lower broadcast used in Omega network
[22]. In the case of upper broadcast, the upper input X1 is sent
IV. GRAPH MODEL OF A MIN AND ITS DFA CAPABILITY
to both the outputs Y1 and Y2 while the lower broadcast provides Y1 = Y2 = X2. The graph models of Figs. 3(b) and (c)
Before we go any further, let us define two matrices, the
and 4 remain valid for various faults in the SE for Omega adjacency matrix and the reachability matrix, obtained from
network. The additional faulty situations and the correspond- the graph model we illustrated earlier. The adjacency matrix
ing reduced graphs for SE which lower and upper broadcast, A of a graph is the N x N matrix [aij] with aij = 1 if there
are shown in Fig. 5.
is a connecting link from node i to node j in the graph;
_
_
258
X
1
IEEE TRANSACTIONS ON COMPUTERS, VOL. c-34, NO. 3, MARCH 1985
-
-
_
V
Y2
X2 0
X2
(a)
YI
Y2
1
1
1
X2
1
1
1
1
1
2
yl
yl
I
X2
XI I
(a)
(b)
Y2
(b)
Y2
c
(c).-
Fig. 6. (a) Adjacency matrix of the SE of Fig. 2(a). (b) Adjacency matrix of
the SE of Fig. 2(b). (c) Adjacency matrix of the SE of Fig. 2(c).
XI *
x2
Y2
(c)
v
1
B
(d)
C
Fig. 5. (a) Graph model of an SE for Omega network when s-a upper broadcast. (b) Graph model when s-a lower broadcast. (c) Graph model when
s-a upper broadcast and X2 s-a-y. (d) Graph model when s-a lower broadcast
and Y2 s-a-y.
dDD
IE
otherwise, aij = 0. Fig. 6(a) shows the adjacency matrix of
the bipartite directed graph [29] of a 2*2 SE of Fig. 2(a).
When the control line is s-a-0 or s-a-i, the matrices are as
shown in Fig. 6(b) and (c), respectively.
The reachability matrix R of a graph is defined as an N*N
matrix [r0j] with rij = 1 if nodej is reachable from node i, and
rij = 0 otherwise. Here, the information we need from the
reachability matrix is whether an input port of MIN can reach
an output port or not, and thereafter, it is not necessary to
retain any connectivity information from the input nodes to
the intermediate nodes [e.g., node numbers 1-16 in
Fig. 7(a)]. The graph model of a 2*2 SE given in Fig. 3(a)
can be used to obtain the graph model for the baseline network of Fig. 2(d) and is shown in Fig. 7(a). The adjacency
matrices of each of the three stages are shown in
Fig. 7(b), (c), and (d), respectively.
Corollary 1: In an mr-stage MIN, let Ai be the adjacency
matrix of the bipartite directed graph of the ith stage representing its connectivity, then R, the reachability matrix from
input nodes to output nodes of the MIN, could be given by
R
m
i=1
Ai.
F
(a)
a
b
c
0
o
0
2
3
4
5
6
7
1
0
0
0 0
0
0
1
0
0
0
0
0
1
1
0
0 0
0
1
1
0
0
d
0
e
0
0
0
0
1
1 '0
f
0
0 O
0
1
1
0 0 0 O
0
1
0 0 0 0 0
1
g
h
o
o
0
(b)
0
0
9
8
0
0
0
0
0I
0
t1
10
11 12 13 14 15 16
1
1
0 0 0 0 0
2
0
0
O
0
1
1
0
0
3
1 1
0
0
0
0
0
0
4
0
O
0
1
1
0
0
5
6
7
8
0
0
O
0
0
0
1
1
0 0 0 0
0
O
O
O
0
1
1
0
1
1
0
0
0
0
0
O O O 0 1 1
(c)
Proof: The proof is obvious.
Now we can compute the reachability matrix R by multiC D E F G H
A B
C D E F G H
A B
plying the adjacency matrices AI, A2, and A3 and the resulting
I 1
9
a
1
0 0 0 0 0 0
1 1 1
R matrix is shown in Fig. 7(e). In a similar way, the model
b
1 1
1 1 1
could be obtained for a MIN with any number of stages and 10 0 0 1 1 0 0 0 0
I 1 1
with any number of arbitrarily located faults and the R -matrix 11
1
c
0 0 0 0 0 0
1.1
1 1 1
1 1 1
could be used to test for the DFA capability.
12
0 0
d
1 1
1 1 0 0 0 0
1 1 1
1 11 11
1
For example, consider the multiple single faults of 13 0 0 O 0 1 1 0 0
e
1 1
1 1 1
Fig. 8(a). As shown in the corresponding graph model of
1 1 1
f
11
1 1 1
Fig. 8(b), node 11 and 8 edges have been eliminated because 14 0 0 000 0 1 1
1 1 1
11
1 1 1
g
of the faults. The adjacency matrices for stage 1, 2, 3 are 15 0 0 O 0 1 1 0 0
1 1 1
given in Fig. 8(c), (d), and (e), respectively. The reachability 16
0
000 0 1 1
h
1 1
1 1 1
matrix, R = A1 A2 * A3 given in Fig. 8(f) shows that not all
(d)
(e)
input nodes can reach all the output nodes. If multiple passes
are allowed (i.e., output can be fed back to the input side), Fig. 7. (a) Graph model for the baseline network of Fig. 2(d). (b) A,,
first-stage adjacency matrix for MIN of Fig. 7(a). (c) A2, second-stage
then additional nodes can be accessed in successive passes.
adjacency matrix for MIN of Fig. 7(a). (d) A3, third-stage adjacency matrix
for MIN of Fig. 7(a). (e) R, reachability matrix for MIN of Fig. 7(a).
Corollary 2: Let R be the reachability matrix of a MIN,
-
259
AGRAWAL AND LEU: MULTISTAGE INTERCONNECTION NETWORKS
s-a-1
A
a
1 2
3 4
5 6
7 8
01
00
00
00
9
1 1 12 13 14 15 16
10
I
11
0 0 0 0
00
O 0
1
0 0
0 0 0 0
0 0
b
10
00
00
00
2
0 0
c
00
1 1
0 0
00
3
1
d
00
1 1
0 0
00
4
e
00
0 0
1 1
00
5
0 0
E
f
00
0 0
1 1
00
6
0 0
F
g
00
00
00
1 1
7
0 0
0 1
h
00
00
00
1 1
8
00
B
C
D
G
H
.0 0
9
10
11
12
0000
0
0
B
C
D
E
F
G
0 0
0 0
0 0 0 0
11
O
O
I
I
1
1
0
1
1
1
1
1
1
0
1' 1
1
1
F
GH
O
1
1
1
0
0 0 0 0
0
0
0
00
a
1
0
0
0
0
0
b
1
0
0
0
0
0
0
c
O
0
I 0 0 0 O
d
0
O
O
0
1
1
1
1
O
O
0
1
1
1
1
0
1
1
0
0
e
0
O
0
1
1
f
0O
15
0
O
O
0
1
1
0
0
g
0
O O
1B1
O
O 0 1 1
1FG1H
h
(e)
1
1 000000
0 1 1 1111
1 1 1
O1 101
0 1 1 1111
1 1
J
O1 101
(f) 11 11
0001
B
C
D
E
F
G
O
0
1
1
1
11
a
1
1
0
1
1
1
b
H
1
A
B000111
C D E F G11H
1
001 11.1 11
001 1 1111
(f)1 1
c
d
d
0
1>
0
O
f
E
D
1
0
e
1
0
o
b
1
C
0
0
0 0
B
0
a
0
0
1
A
0
O
0
0 -0
1
0
0
13
O
0 0
H1
14
0
0
1
1
(d)
0O
16
1
0
O
(c)
A
(a)
1
0
0
1
1
1
1
1
e
O
0
1
1
1
1
1
f
g
g
hi
h
1
BCDEF1GH1 1
(b)
(h)
(g)
Fig. 8. (a) Baseline network with faults. (b) Graph model of the baseline network of Fig. 8(a). (c) Adjacency matrix in first stage.
(d) Adjacency matrix in second stage. (e) Adjacency matrix in third stage. (f) R, the reachability matrix. (g) R2 for Fig. 8(f). (h) R3
for Fig. 8(f).
then the reachability in K passes (and hence, its DFA) could
be given by
Rk
=
Rk.
Proof: The proof is self-explanatory.
DFA is defined as a property that provides each input of the
network to be connected to any one of its outputs in a finite
number of passes (and hence, any PE to any other PE). The
R -matrix of Fig. 8(f) shows that the network of Fig. 8(a)
does not allow all input nodes to be connected to each one of
the output nodes. But by multiplying A three times, it could
be observed [Fig. 8(h)] that three passes through the network
of Fig. 8(a) are good enough to provide communication paths
from any input to any one of the output nodes. Hence, the
DFA property is satisfied. It may be noted that its DFA could
not be retained for other combinations of faults. For example,
an additional s-a-0 at the control input of SE II in the network
of Fig. 8(a) leads to a graph model of Fig. 9(a). This graph
is clearly divided into two unconnected subgraphs, one consisting of the input nodes b and c and the output nodes A, B,
and C, and the other containing the rest of the input and
output nodes. This could also be seen from the reachability
matrix of Fig. 9(b) which could be partitioned as two smaller
nonzero submatrices as shown in the figure. This will be true
for
any
such
case
if R could be partitioned
R
as
[29].
=[~R'
where R' and R" are the two nonzero submatrices. This observation could easily be verified by obtaining the reachability
matrices in two, three, and four passes of the network and is
shown in Fig. 9(c), (d), and (e), respectively.
As R6 = R5 = R4, it is clear that no matter how many
times we multiply, we will never be able to get any better
result. This means the network no longer possesses the DFA
capability.
Theorem 1: In an N-input N-output MIN, the DFA characteristic is ascertained for single or multiple faults at the
control line and/or input and output lines of one or more SE's
if there exists a reachability matrix Rk (1 S k N) in
-
IEEE TRANSACTIONS ON COMPUTERS, VOL. c-34, NO. 3, MARCH 1985
260
B
C
D
a
0 1
1
1
b
1 0 1 1
A
b
I
c
!_I _ _1
d
e
f
g
h
C
D
E
F
GH
a
'O
0
1
1
1
11
11 o o o o o
b
1
1
1
0
1
1
11
1n 0 01 01 o o
C
1
1
1
0
1
1
11
11
d
O O 0 1
1
1
11
''i
e
O O 0 1
1
1
11
f
O O 0 1
1
1
11
g
O O 0 1
1
1
11
1 1
o o0
a
R
A B
1
0
0
H
1 1 1 ?II
__
O
O
G
II
F
rO
OW
-1
1
1
0 0 10 i1 1 1 l1i
Ij
R
I
1' 1 1
0 0 0
0
O O O 0 -1I
O
II1
O%
1
1 1
11
h
0O O 0 1 1 1
(c)
(b)
A
a
b
C
d
f
g
0
I
0
0
O
0
0
h
B
C
D
E
F
G
A B
H
0
a
C
D
E
1 11
11 1
I
1
1
1
b
1 1 1 1 1
1 X
1
1
1
1
C
1
1
1
1
0 O 0
1 1
1
1
1
1 1
1.
1
1
1
O
0
1
1
1
1
1
O
0
1
1
1
1
1
e
0 O 0
O
0
1
1
1
1
1
f
0
0 0 1
1
1
1
1
g
0 O 0
0
1
1 1 1
h
0
1
0 1
0
1
1
(d)
1 1 1 1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
e
1 1 1
1
0
1
1
1
f
1 1
1 1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1 0
C D E
F
G
1
1
1
1
Fig. 9(b). (e) R'
*1 1 1
(e)
R3 for
Fig. 9(b).
such that rk = 1 for all i,j; 1 i,j N.
Proof: If a MIN has the DFA property in a minimum of
k passes then Rj = Rj_1 1 j S k. This means that any input
node of the network could reach at least one output node
(different than itself as feedback is assumed) after the first
pass, and thereafter it will be able to reach at least one
additional output node in successive passes. Thus, each input
node should be able to reach all N output nodes in at most N
passes if the network has the DFA capability. This means that
k 6 N) must exist such that rk =1 for all i,j,
an Rk (1
1 S i,j 6 N. When this is satisfied, we will be able to
connect any input node to any one of the output nodes in at
Q.E.D.
most k passes.
Corollary 3: If there are any stuck type faults at the input
side or the output side of a MIN (hereinafter called primary
k
passes,
<
-
H
a
03
3 2
1
1
1
b
10
1
3
2
2
2
2
1
1
c
-1
1
0
2
d
I
1
1
o:11 1
1
1
e
3
3
3
2
(0 1
1
1
1
1
f
3
3
3
2
1 0
g
2
2
2
1
1
h
<2
2
2
1
11
0 1
1
10w
(b)
A
B
C
a
0
X
co
b
1
0
1
c
1
1
0
E
F G
2
I
1
3
2 2 2
2
3
2 2 2
2
1
1
1
D
H
1
d
2
2
2
0.
1
e
OD
X
X
2
0
1
1
0
1
1
1
0
1
1
1 0
g
ao
Xco
h
(C)
Fig. 10. (a) Distance matrix for Fig. 7(a). (b) Distance matrix for Fig. 8(a).
(c) Distance matrix for Fig. 9(a).
1
Fig. 9. (a) Graph model of the baseline network of Fig. 8(a) with the control
input of SE-II s-a-0. (b) R, the reachability matrix. (c) R2forFig. 9(b). (d) R3
for
1
0
f
11 1
1
1
d
O
G H
0 1 1 11
0 0 1
1
F
1
(a)
(a)
E
1
1 1
AB
D
1
1 1
h
C
11
c
F
B
G
1
d
g
A
H
F
E
inputs and outputs, respectively), then the DFA property
cannot be provided.
Proof: If there is a fault at any one of its output lines,
then it is obvious that nothing can be transmitted on that line,
and hence the corresponding PE cannot receive any data. In
terms of the graph model, the output line cannot be accessed
by any one of the inputs. Similarly, if there is a fault at any
one of the input lines, then it cannot communicate to the
output lines, and hence the corresponding PE cannot send any
Q.E.D.
data.
DFA
its
destroy
may
Theorem 2: The faults in the MIN
reachability
capability if and only if there exist at least two
matrices R' and R 1+ for 1 1 < N, such that rZ = r+t' for all
i,j; 1 > i,j % N and at least one rt = 0 for any i,j;.
1 i,j -N
Proof: If some faults in the MIN cause it to lose the DFA
property, then there remains at least one pair of input and
output nodes i and j that cannot be connected in a finite
number of steps and is indicated by an entry of rk = 0. Moreover, if R'+1 = R' then all successive powers of R (i.e., R'+2
and so on) will remain equal to R'. This means that the
261
AGRAWAL AND LEU: MULTISTAGE INTERCONNECTION NETWORKS
b
(a)
(b)
Fig. 11. (a) A 16-input 16-output Omega type SSIN. (b) Modified version of SSIN.
connection from i to j can never be provided for any number
of passes.
Q.E. D.
Corollary 4: In an N-input N-output MIN, RP+', the
reachability matrix within p + 1 passes is equal to RP for all
p N.
Proof: As per Theorem 1, if there exists a path from an
input to an output node, then the maximum number of passes
required is equal to N. Hence, after N passes, we ought to
have the corresponding a$f element of RN as 1 and any further pass cannot modify the reachability elements, and hence
aij elements. Hence, RN+1 ought to remain the same
as RN.
Q.E.D.
Corollary 5: If no conflict in path length is assumed for
the random requests, then the average of the minimum path
length (called the static average and represented by SAV),
can be computed from the distance matrix D as follows:
N N
SAV =di
N 2 i=l j=l
where 6 represents the delay time needed in each pass.
After we have the entries for the reachability matrices of a
MIN, it is easy to set the distance matrix and calculate the
average path lengths. Once we have all these results, we may
examine the question of whether the network is the best from
the SAV viewpoint or not. In other words; could we have a
better SAV by changing the link connection patterns or doing
V. DISTANCE MATRIX AND AVERAGE PATH LENGTH OF
something else? This aspect could be easily examined at least
THE MIN's
for some of networks like single-stage interconnection netThe distance matrix D [29] of a MIN is defined as an work (SSIN) [4], [13]. The minimization of path lengths in an
SSIN has been covered in [13] and a few rules have been
N x N matrix [dij] with the entries
suggested for defining the connection pattern in an SSIN. But
0 when i j
the effect of faults on the SAV has never been considered.
A simulation program is implemented to observe the perdjj =the least I (if any) such that rtJ = 1 in RI; 1< I < N formance
of a 16 input 16 output SSIN (one stage of the
oo otherwise.
Omega network [22] configuration) and the modified version
The entries indicate the number of the passes needed for a as shown in Fig. 11(a) and (b). Fig. 12 indicates the effect of
request to reach the destination. Fig. 10(a), (b), and (c) changing the connection pattern when no faults are present.
shows the distance matrices of the networks of Figs. 7(a), The impact of a single fault on the SAV is shown in Fig. 13
8(a), and 9(a), respectively.
and the modified version is seen to provide better per-
262
IEEE TRANSACTIONS ON COMPUTERS, VOL.
c-34,
NO.
3,
MARCH
1985
Ur)
4.'
tol
I),Oi
1n
{L n
A1C,
4.,
9-
0)
tin
C-
IL)
(a
IN
omega tyfPC
__
rb-hmodiiied
1
I
9
7
I
10
I.
18
oad m 16
Fig. 12. The effect of changing connection patterns when no fault is
presented in 16-input 16-output SSIN.
omega type
to-
A
-modi4ied
7
10
1.3 16
l oad m 16;
Fig. 15. The effect of changing connection pattern when a single fault occurs
in the control line at the first stage of a 2-stage 16-input 16-output network.
I
I,m
4)v
a,
ILD.
in
qin.E.
a,
CL
0
'14a
,W.
'WI
to
4.) a-'
L
L
ti
0
)--_-.
7
'1
10
omega type
modified
13
type
mcd i 4 i ed
1B
C
Fig. 13. The effect of changing connection pattern when a single fault
occurs in a control line of 16-input 16-output SSIN.
]lod i
omega
7
load
16
10
I.
1L
16
Fig. 16. The effect of changing connection pattern when a single fault occurs
in the control line at the second stage of 2-stage 16-input 16-output network.
'F
C.
C.
14.,
_-4
C,
omega
-':
s @. ^
o/f
omega
type
type
mod i 4 ied
moldifie.d
;
-1
Fig. 14.
M
7
10
13
1l
load
J
The effect of changing connection pattern when no fault occurs in
the 2-stage 16-input 16-output network.
I.
1
4
7
oad d
10
16
Fig. 17. The effect of changing connection pattern when a single fault
occurs in the link between 2 stages of 2-stage 16-input network.
263
AGRAWAL AND LEU: MULTISTAGE INTERCONNECTION NETWORKS
formance. The next question to be addressed is whether such
conclusions are valid for a general MIN with several stages.
Some conclusive simulation results are obtained from the
computer program. Under no faults, Fig. 14 shows the effect
of changing connection pattern from a 2-stage 16-input
16-output Omega-type network to a modified version.
Figs. 15, 16, and 17 show the performances of these 2-stage
networks when a single fault occurs in control line at the first
stage, second stage, or at a link connecting the two stages,
respectively.
VI. OPrIMuM DESIGN OF A MIN FOR DFA CAPABILITY
The m-stage MIN design with m = n has been widely
covered in the literature [2]-[4], [7]-[12]. These networks
are designed in such a way that there is a one-to-one correspondence between input and output nodes, i.e., from each
input line, there is a unique path to each one of the output
lines, and full connectivity requirements are satisfied. Systematic ways of designing these networks have also been
described [6]. For m > n, alternate paths between each
input-output pair provides redundancy and recent work [26]
provides a detailed account of their fault-tolerant capabilities. Our main concern is to describe a design methodology
for a class of MIN's, with m < n, so that the availability and
graceful degradation of the parallel computing system could
be optimized. In other words, the network could be designed
such that the DFA property could be retained for as many
faults as possible. Although it may be possible to devise other
schemes too, the proposed methodology does provide a certain degree of optimality from the DFA view point.
The design procedure is based on set theory. The two steps
are as follows.
A) Partition the N (= 2') inputs and outputs into N/(2m)
sets with each set consisting of 2m inputs and 2" outputs.
B) Design the mr-stages of the network such that 2m-inputs
of one set could be connected to 2m-outputs of another set.
Thus, each set will consist of m stages, with each stage
formed with 2'-1 SE's. In this way, each of the subnetworks
becomes fully connected network of size 2m inputs and 2'
outputs. One such example for m = 2 and n = 4 is shown in
Fig. 18, wherein 16 inputs and 16 outputs are divided into
four subsets with each group consisting of four elements. The
input subsets are (a, b, c, d), (e,f, g, h), (i,j, k, 1), and
(m, n, o, p), while the outputs are divided into (A, B, C, D),
(E,F,G, H), (I,J,K,L), and (M,N,O,P) subsets. This
satisfies part A) of the design procedure. Part B) is assured by
assigning output nodes in such a way that there is no common
alphabet between the inputs and outputs of each subset. In
other words, the outputs from the input node subset
(a, b, c, d) are not connected to the output node subset
(A, B, C, D). It must be kmembered that for the multiple
processor system of Fig. 1, both nodes a and A are logically
the same, as the PE works as a link between the input-output
pair a and A. Hence, no advantage is gained by connecting
nodes a and A through the MIN. Such a design procedure for
an arbitrary value of m < n is shown in Fig. 19. Before we
A
B
o
~
y6a
~~~6
p
\\
0
Fig. 18. Two-stage MIN with single stuck type faults at various SE's (only
one group of 4-SE's, V, VI, VIII, and XIV, not faulty).
consider the optimality of our design procedure, three lemmas are in order.
Lemma 1: In the fault-free partition of rm 2m1 SE's connecting 2m inputs and corresponding outputs, any input can
access any one of its outputs in just one pass.
Proof: The design methodology described earlier
makes each of the partitioned networks a MIN with 2m
inputs-2m outputs. Moreover, the R-matrix of each partition
could be seen to contain all one elements and hence DFA is
satisfied in only one pass. Hence, any of its inputs can access
all of its output lines in one pass.
Q.E.D.
Lemma 2: In each partitioned group consisting of m * 2 m'
SE's and connecting 2m inputs and the corresponding output
lines, if some or all SE's have single faults (except at the
primary input and output lines), then each primary input line
can be connected to at least one of the primary output lines.
Proof: From Fig. 3(b) and (c), it is obvious that a fault
at the control line of an SE allows each input to be connected
to one output. A single fault at one of the inputs of the SE
allows the other input to be connected to both the outputs
[Fig. 4(a)] and a single fault at the output side of the SE
permits both inputs to be connected to the nonfaulty output
[Fig. 4(b)]. It may be noted from Figs. 3 and 4 that a fault at
an input (output) line is reflected as a fault at the corresponding output (input) line. Hence, simultaneous faults at an input
and an output line of the same SE are considered a multiple
fault. As the primary input and output lines of the MIN are
264
IEEE
2~ Inputs
m
t
2m
e
correspondingPE
outputs
*
Inputs
takes us to a
feedback path through the
node of the second partition. The second pass takes us to one
outputs
/
io
2 2g mInputs /*p
m
E4
op
j*
of the outputs of third partition and so on. In the worst case,
1) passes before we reach the Kth partition.
Iti will take (K
As this group contains all healthy SE's and the corresponding
R matrix contains all "1" elements, the next pass can take us
tto
-all the output nodes of the Kth partition. Now, the feedback path through
takes us back to the first partition and
outputs
*
,;
NO. MARCH 1985
TRANSACTIONS ON COMPUTERS, VOL. c-34,3,
access to all 2' PE's
inputs of the first
3
partition is possible.
The
a next pass provides access to all 2' outputs of the
second partition. If this process is continued, a total of
(K -1 + K) = (2K-1) passes is required to access any
Q.E.D.
one of the output nodes.
MIN.
Fig. 19. Optimum design of an
Lemma 4: The maximum number of tolerable control line
faults, under the conditions given in Theorem 3, is
assumed to be fault free, one input can be connected to at m (2n--2m-1).
2 ninput-2' output MIN, the
least one output line. This can also be proved using the
For a given
adjacency matrices for each stage and by using the resultant number of SE's in one stage = 2 so the total number of
The number of partitions =
one-pass reachability matrix.
Q.E.D. SE's = m
According to
Lemma 3: A special case of Lemma 2 arises when the number of SE's in one partition =
partition
is assumed to
control lines of all the switches are stuck-at-zero or -one; then the statement in Theorem 3, only one
partitions
may be
other
the graph model for a partitioned network will contain 2m be fault free while control lines in all
unconnected subgraphs, with each one directed from one faulty. Therefore, the maximum number of tolerable control
Q.E.D.
line faults = r (2n primary input to only one of the primary outputs.
of
tolerable
link
line
Proof: From Fig. 3(b) and (c), whenever the control Lemma The maximum number
in
Theorem
3
is
line of an SE is faulty, there is a one-to-one connection. This faults under the conditions given
means only one input is connected to one and only one of the (m 1)
output MIN,
Proof: For a given
outputs, and hence the adjacency matrix for each stage will
between the
connections
colhave only one nonzero element for each row and each
there are
1) intermediate
"
"
Hence,
there
is a total
umn. Hence, the overall R-matrix will also have only one
stages and 2" link lines for each stage.
the
primary
inputs
(except
in
intermediate links
entry each row and each column. This would lead to an of (m
of
1)2'
interoverall one-to-one connection, with 2m unconnected sub- and outputs). Each partition will consist
assumed
to
be
fault
is
for
Q.E.D. mediate links. As only partition
graphs each group.
allowed
in
all
other
is
SE
is
The optimality of the design in terms of DFA capability
free and a single link failure per
demonstrated by the following theorem.
partitions, the total number of tolerable link faults =
- 1)
=
- 1)
Q. D.
isimplementedby
Theorem 3: Ifa2ninput-2'output
in
our
design
is
fairly
to
and
tolerable
the
the
of
Since number faults
design procedures A)
(m < n) according
mr-stages
network,
we
could
claim
the
DFA
then
is
for
faults
in
ensured
close
to
the
number
of
SE's
B),
multiple single
capability
SE's constituting one partition of 2m that our methodology provides a close to optimal solution. As
provided thatmr
inputs and 2m outputs are assumed fault free. The upper an example, the graph model of the MIN shown in Fig. 18
bound for the number of passes required to provide the DFA which contains several single faults is provided in Fig. 20.
is (2`.i) where K =
The reachability matrix in the first pass is given in Fig. 21.
Proof: The graph models for possible single faults have Under the random request loading and close-to-finish arbithe computer simulation mentioned earlier probeen given in Figs. 3(b) and (c) and 4(a) and (b). The con- tration
vides
the
imperformances of the MIN of Fig. 18 and is shown
nectivity consideration (and the adjacency matrix), is
in
22.
The average path lengths are computed for no
is
MIN
A typical m-stage
Fig.
portant for the DFA
fault
case
and
when a single fault is present at either the
to
be
said
shown in Fig. 19. Then the worst case fault could
control
line
of
either stage or at a link connecting the two
are
be present when the SE's of all the (K 1) partitions
The
let
the
resulting curves indicate that a single fault has a
stages.
faulty. For simplicity (and without losing generality)
is
The
us assume that the kth partition healthy.
reachability very marginal increase on the average time delay and could
and the be considered to be a very valuable simulation result to supfor
could
be
obtained
matrix R
each partition
would
R-matrix for the first (K 1) partitions
satisfy port our claim that our design is good and close to optimal
It has not been possible to
the
last
2
1
is
to
Lemma while Lemma
partition. from a fault-tolerance
applicable
others, as, to the best of
to
our
methodology
one
in
the
first
As interpreted earlier,
compare design
(K 1) partitions,
such technique in the
exist
any
our
there
does
not
of
one
to
connected
to
at
least
allow
be
knowledge,
any input
pass would
to
literature.
input
while
the
Kth
allow
any
partition would
the outputs;
be connected to any one of its outputs in one pass.
Corollary 6: The restriction imposed by Theorem 3 is not
Let us assume that we started access from one of the inputs a necessary condition for the DFA property.
of the first partition. Under the assumed faults, the first pass
Proof: Theorem 3 is sufficient for ensuring DFA, but
will allow access to at least one of its output nodes and the not necessary. The faults may be such that the R-matrix ele-
t
2 Inputs *
2m
,v/,**
outputs
m-stage
Proof:
* 2.
5:
MIN
2m-1).
m
* (2Q
(m
1
mr-stage
n-,
2"- and the
*m 2m'.
2"- ).
m-stage 2n-input-2n
- 1)2n
(m
(2n 2m) (m
1/2(m
2m`
2f-.
[30],
capability.
viewpoint>
(2n- 2m-1)
E.
*_~ ~ C
265
AGRAWAL AND LEU: MULTISTAGE INTERCONNECTION NETWORKS
2
F
G
d
->
e 6
f
,+
C'
K
h
J CI
i
~
L
~~~~~~~~
M
I-
,
-
B.-S---A
N
1
i
1
m
P
14
lh
n
166
p
s-a-x
SE
e-a-x
1
1
7
L
10
Lb
16
load
Fig. 22. The effect of the single faults that occur in 2-stage 16-input
16-output network.
w
A
a
D
b
B
Fig. 20. A graph model of Fig. 18.
B
C
a
A
10
0
b
0
1
0
c
O 0
1
d
0
e
0
0 0
f
0
0
0
g
0 0
h
0
i
L
M
N
O
00
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
00
0
0
0
0
0
0
0
0
0
00
0 0
0
0
0
0
1
0
0
0
11
0
0
0
0
0
0
0
1
0
0
11
0
0
0
0
0
0
0
0
1
0
0
0
0
E
F
G
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
o
(o o
j
0
0
0
0
0
0
0
k
0
0
0
0
0
0
0
1
0
m
1
n
0
0
0
0
0
1
0
0
0
0
IIJ
00
1
1
0
0
0
0
1
00
1
1
0
0
0
0
0
10
0
0
1
1
1
001
0
0
1
1
1
1
0
1
1
1
0
1
1
1
1
0
0
1
0
0
0
0
0
00
00
c
d
p
K
0
D
0
e
f
g
(a)
b
1
1
E
d
F
0
0
0
1
0
0
0
0
0
00
0
0
0
1
0
0
e
1
0
0
0
0
00
0
0
0
0
1
0
f
1
0
0
0
0
00
0
0
0
0
0
0
0 0
p
00 0
0
0
0
0
00
D
c
1
0
2
B
-
0
SE
stage
link e-a-x
~~~~1
~ 1
~
*
k
1
ostage 1
fau
--.~'.
jv
1
Fig. 21. R, the reachability matrix for Fig. 20.
g _
-
A
-- _
h
(b)
ments may contain arbitrary l's and the multiple pass (hence,
multiplication of the R matrix to itself) may lead to an
R' matrix with all "1" entries.
Q.E.D.
One such exception is illustrated in Fig. 23, which can be
said to possess a high degree of fault tolerance. Thus, our
design procedure is very useful in implementing a MIN with
the DFA capability in the presence of faults. Theorem 3 identifies the set of single faults at the SE's so that it is possible
to ascertain the DFA characteristic even without obtaining a
graph model and without performing a lot of connectivity and
reachability computation.
Fig. 23. (a) One-stage MIN with 4 faults. (b) Graph model for Fig. 23(a).
VII. CONCLUDING REMARKS
The fault model of an SE is used to model MIN's, and an
adjacency matrix and reachability matrices are employed to
provide a systematic procedure of testing the network's DFA
capability. The versatility of the fault model enables us to test
the network under multiple stuck type faults both at the control lines and the input-output lines of the SE's. In addition,
IEEE TRANSACTIONS ON COMPUTERS, VOL. c-34, NO. 3, MARCH 1985
266
the R-matrix in successive passes is also useful in computing
the average path length. The network design procedure enables the MIN to posses maximum fault tolerance, and hence
in turn optimizes the availability of the system. The selection
of connection pattern is seen to be a key issue in minimizing
the path lengths in both the SSIN's and MIN's which could
also be used as an index for the performance. If we consider
the fault tolerance as well as the minimization of the path
lengths simultaneously, then the optimization problem of the
MIN becomes extremely complex and we hope to present
additional results in the near future.
REFERENCES
[1] D. P. Agrawal and T. Y. Feng, "A study of communication processor
systems," Rome Air Devel. Center, Tech. Rep. RADC-TR-79-3 10, Dec.
1979.
[2] C. L. Wu and T. Y. Feng, "On a class of multistage interconnection
networks," IEEE Trans. Comput., vol. C-29, pp. 694-702, Aug. 1980.
[3] H. J. Siegel, "The theory underlying the partitioning of permutation networks," IEEE Trans. Comput., vol. C-29, pp. 791-801, Sept. 1980.
[4] D. K. Pradhan and K. L. Kodandapani, "A uniform representation of
single- and multi-stage interconnection networks used in SIMD machines," IEEE Trans. Comput., vol. C-29, pp. 777-791, Sept. 1980.
[5] D. P. Agrawal, "On graph theoretic approach to n- and (2n - I)-stage
interconnection networks," in Proc. 19th Annu. Allerton Conf. Commun.
Contr. Comput., Sept. 30-Oct. 2, 1981, pp. 559-568.
"Graph theoretic analysis and design of multistage interconnection
[6]
networks," IEEE Trans. Comput., vol. C-32, pp. 637-648, July 1983.
[7] L. N. Bhuyan and D. P. Agrawal, "Design and performance of a general
class of interconnection networks," in Proc. 1982 Int. Conf. Parallel
Processing, Aug. 24-27, 1982, pp. 2-9; also in IEEE Trans. Comput.,
vol. C-32, pp. 1081-1090, Dec. 1983.
[8] D. P. Agrawal and S.C. Kim, "On non-equivalent multistage interconnection networks," in Proc. 10th Int. Conf. Parallel Processing,
Aug. 25-28, 1981, pp. 234-237.
[9] M. A. Abidi and D. P. Agrawal, "On conflict-free permutations in multistage interconnection network," J. Digital Syst., vol. V, no. 2,
pp. 115-134, Summer 1980.
, "Two single pass permutations in multistage interconnection net[10]
works," in Proc. 1980 Conf. Inform. Sci. Syst., Mar. 26-28, 1980,
pp. 516-522.
[11] D. A. Pauda, D. J. Kuck, and D. H. Lawrie, "High-speed multiprocessors and compilation techniques," IEEE Trans. Comput.,
vol. C-29, pp. 763-776, Sept. 1980.
[12] C. L. Wu and T. Y. Feng, "The reverse-exchange interconnection network," IEEE Trans. Comput., vol. C-29, pp. 801-811, Sept. 1980.
[13] J. E. Wirsching and T. Kishi, "Minimization of path lengths in single
stage connection networks," in Proc. 3rd Int. Conf. Distrib. Comput.
Syst., Oct. 18-22, 1982, pp. 563-571.
[14] C. L. Wu, T. Feng, and M. Lin, "Star: A local network for real-time
management of imagery data," IEEE Trans. Comput., vol. C-31,
pp. 923-933, Oct. 1982.
[15] D. C. Operferman and N.T. Tsao-Wu, "On a class of rearrangeable
switching networks, Part Il: Enumeration studies and fault diagnosis,"
Bell Syst. Tech. J., pp. 1601-1618, May/June 1971.
[16] J. P. Shen and J. P. Hayes, "Fault tolerance of a class of connecting
networks," in Proc. 7th Symp. Comput. Arch., La Baule, France,
May 6-8, 1980, pp. 61-71.
[17] J. P. Shen, "Fault tolerance analysis of several interconnection networks," in Proc. 1982 Int. Conf. Parallel Processing, Aug. 24-27,
1982, pp. 102-112.
[18] J. J. Narraway and K. M. So, "Fault diagnosis in inter-processor switching networks," in Proc. Int. Conf. Circ. Comput., Oct. 1-3, 1980,
pp. 750-753.
[19] C. L. Wu and T. Y. Feng, "Fault-diagnosis for a class of multistage
interconnection networks," in Proc. 1979 Int. Conf. Parallel Processing,
Aug. 21-24, 1979, pp. 269-278.
[20] D. P. Siewioriek et al., "A case study of C*mmp, Cm*, and C*vmp:
Part I-Experiences with fault tolerance in multiprocessor systems,"
Proc. IEEE, vol. 66, pp. 1178-1200, Oct. 1978.
[21] D. P. Agrawal, "Automated testing of computer networks," in Proc. 1980
nt. Conf. Circ. Comput., Oct. 1-3, 1980, pp. 717-720.
[22] D. K. Lawrie, "Access and alignment of data in an array processor,"
IEEE Trans. Comput., vol. C-24, pp. 1145-1155, Dec. 1975.
[23] K. M. Falavarianai and D. K. Pradhan, "Fault-diagnosis of parallel processor interconnection networks," in Proc. 1981 Fault Tolerant Comput.
Symp., June 1981.
[24] S. Sowrirajan and S. M. Reddy, "A design for fault-tolerant full connection networks," 1980 Conf. Inform. Sci. Syst., pp. 536-540.
[25] D. P. Agrawal, "Testing and fault-tolerance of multistage interconnection
networks," IEEE Computer, vol. 15, pp. 41-53, Apr. 1982.
[26] D. P. Agrawal and D. Kaur, "Fault tolerant capabilities of redundant
multistage interconnection networks," in Proc. Real-time Syst. Symp.,
Arlington, VA, Dec. 6-8, 1983, pp. 119-127.
[27] L. R. Goke and G. J. Lipovski, "Banyan networks for partitioning of the
multiprocessor systems, " in Proc. I st Annu. Symp. Comput. Arch., Dec.
1973, pp. 21-28.
[28] G. M. Masson, G. C. Gingher, and S. Nakamura, "A sampler of circuit
switching networks," IEEE Computer, vol. 12, pp. 32-48, June 1979.
[29] F. Harary, Graph Theory. Reading, MA: Addison-Wesley, 1972.
[30] P. Y. Chen, P. C. Yew, and D. Lawrie, "Performance of packet switching
in buffered single-stage shuffle-exchange networks," in Proc. 3rd Int.
Conf. Distrib. Comput. Syst., Oct. 18-22, 1982, pp. 622-627.
Dharma P. Agrawal (M'74-SM'79) was born in
Balod, India, on April 12, 1945. He received the
B.E. degree in electrical engineering from the
Ravishankar University, Raipur, India, in 1966,
the M.E. (hons.) degree in electronics and communication engineering from the University of
Roorkee, Roorkee, India, in 1968, and the D. Sc.
Tech. degree from the Federal Institute of Technology, Lausanne, Switzerland, in 1975.
He has been a Member of the Faculty in the M.N.
E
+
X
Regional Engineering College, Alahabad, India, the
University of Roorkee, the Federal Institute of Technology, Southern Methodist University, Dallas, TX, and Wayne State University, Detroit, MI.
Currently, he is with the North Carolina State University, Raleigh, as a
Professor in the Department of Electrical and Computer Engineering. His
research interests include parallel/distributed processing, computer architecture, fault tolerance, and information retrieval.
Dr. Agrawal has served as a Referee for various reputed journals and international conferences. He was a Member of Program Committees for the
COMPCON Fall of 1979, the Sixth IEEE Symposium on Computer Arithmetic, and Seventh Symposium on Computer Arithmetic. During the years
1980-1983 he served as a Member and the Secretary of the IEEE Computer
Society Publications Board, and has been awarded the Society's "Certificate of
Appreciation" for his services. Currently, he is the Chairman of the Rules of
Practice Committee of the Publications Board. He was the Treasurer of the
IEEE-CS Technical Committee on Computer Architecture and as the Program
Chairman for the Thirteenth International Symposium on Computer Architecture held in June 1984. He has been a Co-Guest Editor of the IEEE Transactions on Computers Special Issue on Computer Arithmetic and is an Editor
of the new Journal on Parallel and Distributed Computing published by
Academic Press. He is also a Distinguished Visitor of the IEEE Computer
Society. He is listed in Who's Who in the Midwest, the 1981 Outstanding
Young Men of America, and in the Directory of World Researchers 1980's
subjects published by the International Technical Information Institute, Tokyo,
Japan. He is a member of the ACM, SIAM, and Sigma Xi.
Ja-Song Leu (S'84) was born in Yun-Lin, Taiwan,
on October 15, 1957. He received the B E. degree in
EECS in 1980 from Chung-Yuan College, Taiwan,
d . 11i
-55u. >
the M.S. degree in computer studies from North
Carolina State University, Raleigh, in 1983, and
is now a Research Assistant working towards
the Ph.D. degree in the Department of Electrical
and Computer Engineering, North Carolina State
University. His current interests include parallel/distributed processing and computer communication.