Lab Manual, Digital Logic Design
EXPERIMENT # 10
Objective: IMPLEMENTATION OF FULL ADDER WITH 2, 2X4 DECODERS USING
74139 IC
Apparatus: 74139, 7400 IC’s, Bread Board, LEDs and connecting wires
Decoder :
n  2n.
n = No. of input lines.
2n = No. of outputs of a Decoder.
Decoder is a circuit that convert binary information from n-input lines to max of 2n output
lines e.g. if we have 2 inputs i.e. x,y then there will be 4 output of a Decoder and size of
Decoder will be 2x4.
x
2X4
DECODER
y
d0
d1
d2
d3
output lines
data input lines
Block Diagram of 2X4 Decoder.
E
Truth Table of 2X4 Decoder
x
0
0
1
1
y
0
1
0
1
E
1
1
1
1
d0
1
0
0
0
d1
0
1
0
0
d2
0
0
1
0
d3
0
0
0
1
Boolean Functions for 2 x 4 Decoder
do = E x′ y′
d1 = E x′y
d2 = E x y′
d3 = E x y
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Lab Manual, Digital Logic Design
Implementation
x
y
y'
x'
d0
=
x' y'
(To LED)
d1 = x' y
(To LED)
d2= x y'
(To LED)
d3= x y
(To LED)
E
Now we implement Half Adder with 2x4 Decoder.
Truth Table of Half Adder
i/p’s
x
0
0
1
1
o/p’s
y
0
1
0
1
SHA
0
1
1
0
CHA
0
0
0
1
Truth Table of 2X4 Decoder
i/p’s
x
y
0
0
0
1
1
0
1
1
o/p’s
d0
1
0
0
0
d1
0
1
0
0
d2
0
0
1
0
d3
0
0
0
1
By comparing Truth Tables of half Adder and 2 X 4 Decoder.
We can see that
SHA = d1 + d2
CHA= d3
Electronic System Lab, SED, UET Taxila
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Lab Manual, Digital Logic Design
Block Diagram of Half Adder with Truth Table of 2X4 Decoder
do
open
x
d1
2X4
DECODER
SHA
d2
y
d3 = CHA
E
Note:
By connecting an OR gate with output Pin 1 & 2 of 2X4 Decoder. Half Adder can be implemented with 2X4
decoder. Similarly by connecting two Half Adders, we can form a Full Adder by using 2, 2X4 Decoder IC’s.
Truth Table of Full Adder
i/p’s
y
x
0
0
0
0
1
1
1
1
o/p’s
0
0
1
1
0
0
1
1
z
SHA
CHA
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
Block Diagram of Full Adder with 2, 2X4 Decoders.
Using the concept of implementation of Half Adder with 2X4 Decoder, we can implement Full Adder
with 2, 2 X 4 Decoders.
do
do
open
x
open
d1
d1
2X4
DECODER
SHA=x+y
d2
y
2X4
DECODER
SFA=x+y+z
d2
Z
d3 =CFA
d3
CFA
=CHA
E
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Lab Manual, Digital Logic Design
Pin Configuration of 74LS139
+5 V
x
2
E
y
3
open
4
6
SHA=x+y
7
8
d3
GND
15
SHA = x+y
14
13
d0
d1
12
d2
10
d3
9
z
open
Data o/p
lines
Data i/p
lines
data
o/p lines
5
d0
d1
d2
16
Data i/p
lines
VCC
74LS139
1
E
11
SFA=x+y+z
(Cx+y+z)'
CFA
(Cx+y)'
Pin Configuration of 74LS139 (2, 2X4 DECODER)
Electronic System Lab, SED, UET Taxila
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