First-Pass-Silicon Radio
Technology for B3G Wireless
Terminals
Mohammed Ismail
Firstpass Technologies
[email protected]
Analog VLSI Lab.
Topics
•Wireless systems and cellular chipset evolution
•Multi-band radio architectures and IPs
•DC offset modeling and compensation in multi band Zero-IF receivers
•A multi-band WLAN/WiMAX Radio Architecture
•Will your first silicon spin be your last?
Radios for 3G
and 4G Wireless
Abstract
As we move from third generation ( 3G ) to 4G wireless and as we strive to
meet the demands for higher data rates and short distance wireless
applications, a debate has ensued on whether cellular and WLAN/WMAN are
seen as complementary or competing technologies. In either case, wireless
services beyond 3G (B3G) are moving to all-IP, always-best connected,
convergent wireless solutions requiring access to different wireless
infrastructures from the same wireless device, be it a cell phone, a laptop or a
PDA for a multitude of services including voice, data and multimedia
applications. For future handheld wireless devices, this requires low power, low
cost multi-standard multi-band chipsets, the radio part of which will be
increasingly complex with stringent demands on power consumption and cost as
the two main differentiators.
We will present radio design IPs at the system, architectural and block levels for
emerging always-best-connected wireless applications and with focus on smart
power, first-pass-silicon radio transceiver design in deep sub-micron CMOS. We
will highlight both the challenges and the opportunities for innovation in this
area.
2G - 3G - 4G
4G
All-IP
migration
SIP protocal
Backward compatible
VoIP, VoWLAN
Future proof
UMTS/WLAN
Competing or complementary?
convergence
Always
Best
Connected
WiMax
WiMax (Worldwide Interoperability Microwave Access)
Broadband Wireless Access in Metropolitan Area
NEC, Motorola partner on Wi-Fi/cellular connectivity
By Patrick Mannion, EE Times
Aug 5, 2003 (12:46 PM)
URL: http://www.commsdesign.com/story/OEG20030805S0037
MANHASSET, N.Y. — NEC America Inc. (Irving, TX) and Motorola Inc. (Arlington Heights, IL) have announced
their intent to collaborate on an enterprise communications solution that converges a wireless LAN voice over
Internet protocol (VoIP) network with cellular phone systems. Motorola's components include a dual system WiFi/cellular phone and a mobility manager that controls the hand-off between a local (WLAN) and cellular
networks and dispatch functions. The Wi-Fi/cellphone is still under construction, according to Nicholas Labun,
vice president and general manager of Motorola's seamless mobility solutions group. It will combine
802.11a/b/g WLAN technology from TI with Motorola's GSM/CDMA cellular expertise, with unspecified hand-off
functionality included.
According to Labun, the client device will be managed by the Motorola mobility manager that is integrated into
NEC's enterprise equipment and will use the session initiation protocol (SIP).
When it roams outside the WLAN network, the enterprise IP-PBX will initiate the transfer to the wide-area
cellular network via a call directly to the cellular provider or via a land-line connection. The mobility manager
will then make the switch from a VoIP call to a regular cellular network call.
The companies expect user efficiencies to come from increased accessibility to the business network and
greater mobility through seamless wireless access within or outside the enterprise network.
The announcement comes six months after Motorola announced a similar partnership with Avaya Inc. to also
enable seamless roaming between enterprise Wi-Fi networks via Avaya's IP-PBX equipment and cellular
networks. That deal also included Proxim Corp. as a WLAN infrastructure provider.
The new deal with NEC is similar in many respects in that it integrates Motorola's core seamless mobility
components with NEC's WLAN infrastructure and NEAX family of enterprise communication platforms.
Financial details of the agreement are not being disclosed. General availability for the solution is targeted for
the second half of 2004.
“WANDA,” for Wireless Any-Network Digital Assistant
4G Wireless
- Short Distance
- Unregulated bands
- Proliferating
WAN
WLAN
WPAN
Micro cell
Cellular - km wide
WLAN Pico cell:
- 802.11 a/b/g
- 100 m radius
WPAN Pico cell:
- Bluetooth & 802.15.3
- 10 m radius
4G Wireless
•
WLAN experiencing tremendous growth in the public, home, retail and enterprise
market segments
– P-WLAN Hotspot users to surpass 75m by 2008 (Gartner)
– WLAN to reach 50m homes by 2006 (BCWS) and 80% of US businesses by 2008
(InfoTech)
– Driven by major chip vendors, OEMs, consumers and service providers
•
Broadband access becoming the norm
– Surpass 290m subscribers globally by 2008 (ABI)
•
VoIP to replace circuit-switched telphony
– Service providers (globally) accelerating their deployments of high quality SIP-based
VoIP service and enterprise segment on the verge of mass adoption
– ”The most significant paradigm shift in the entire history of modern communications” Michael Powell, chairman of the US FCC
Wireless Standards Snapshot I
Wireless Standards Snapshot II
Wireless
Standards
Mobile
Frequency
Range (MHz)
Multiple
Access
Method
Duplex
Method
Number of
Channels
Channel
Spacing
Modulation
Scheme
User Data
Rate
Chip Rate
AMPS
824~849 (Tx)
869~894 (Rx)
FDMA
FDD
416
30 kHz
FM
N/A
N/A
GSM-900
890~915 (Tx)
935~960 (Rx)
TDMA
FDD
124 (8 users
per channel)
200 kHz
GMSK
9.6 kbps
270.833 kbps
E-GSM
880~915 (Tx)
925~960 (Rx)
TDMA
FDD
174
200 kHz
GMSK
9.6 kbps
270.833 kbps
DCS-1800
1710~1785 (Tx)
1805~1850 (Rx)
TDMA
FDD
374
200 kHz
GMSK
9.6 kbps
270.833 kbps
PCS-1900
1850~1910 (Tx)
1930~1990 (Rx)
TDMA
FDD
299
200 kHz
GMSK
9.6 kbps
270.833 kbps
IS-95A
824~849 (Tx)
869~894 (Rx)
CDMA
FDD
20 (768 users
per channel)
1.25 MHz
QPSK/OQPSK
14.4 kbps
1.2288 Mbps
GPRS
824~849 (Tx)
869~894 (Rx);
890~915 (Tx)
935~960 (Rx);
880~915 (Tx)
925~960 (Rx)
TDMA
FDD
124
200 kHz
GMSK
115 kbps
270.833 kbps
EDGE
876~915 (Tx)
921~960 (Rx);
1710~1785 (Tx)
1805~1850 (Rx);
1850~1910 (Tx)
1930~1990 (Rx)
TDMA
FDD
124
200 kHz
8-PSK
384 kbps
270.833 kbps
WCDMA
1920~1980 (Tx)
2110~2170 (Rx)
DSCDMA
FDD
12
5 MHz
QPSK
2M bps
3.84 Mbps
CDMA2000
/1xEV-DO
824~849 (Tx)
869~894 (Rx)
CDMA
FDD
20
1.25 MHz
QPSK / 8PSK /
16QAM
2.458 Mbps
1.2288M bps
Short-Range
Wireless Standards
Frequency
Range
Multiple
Access
Modulation
Data Rate
2.4GHz DSSS
2.4GHz
DSSS
DBPSK
DQPSK
1Mbps
2Mbps
2.4GHz FHSS
2.4GHz
FHSS
2GFSK
4GFSK
1Mbps
2Mbps
2.4GHz DSSS
High Data Rate
2.4GHz
DSSS
CCK
5.5Mbps
11Mbps
5GHz OFDM
5.250GHz
5.775GHz
OFDM
BPSK/QPSK
16/64 QAM
6,9,12,18
24,36,48,54
2.4GHz
5GHz
OFDM
QAM
Above
100Mbps
2.4GHz
FHSS
2GFSK
8-DPSK
1Mbps
3Mbps
Standards
IEEE
802.11
WLAN
Standards
IEEE 802.11n
MIMO
Wireless Chipset Technology
Drivers
higher performance/price ratios
Hand-set Evolution
Hand-set Evolution
Hand-set Evolution
Hand-set Evolution
Hand-set Evolution
Hand-set Evolution
Technology choices
CMOS Technology
• Compatible with baseband circuits
• Low cost due to high volumes
• More aggressive process scaling
• Rapidly improving fT
Smaller transistors and faster CMOS
200
FT ≈ 1 / LG
F
T
150
≈
1
FT = gm / 2 π CIN
/L
G
Ta
FT (GHz)
125
7.0
6.0
5
2O
2
SiO
100
(
D
VD
75
x)
a
m
∝
T OX
∝ LG
4.0
3.0
50
2
FT ≈ 1 / LG
25
0
0.01
5.0
2.0
1.0
0.10
0.20
0.30
0.40
0.50
0.60
Effective Gate Length (um)
Ft is no problem in CMOS
0.0
0.70
Maximum Supply Voltage (V)
175
8.0
CMOS Vs Bipolar
CMOS
• Symmetric behaviour
• Better Linearity (higher
signal swing)
• Higher ft at submicron
feature size
• Better scaling properties
• Low static power (no DC
gate current)
Bipolar
• Higher gm for same bias
• High ft
• Low thermal and 1/f noise,
but produces input current
noise
• Lower DC offset
• No body effect
• Lower overdrive (VCEsat)
CMOS
Reverse Interconnect Scaling
• Top metal layers – larger pitches – thicker lines : for power handling and
reduce losses
• Interconnect dielectric thickness is twice the metal thickness
• Hence top metal layers are far from the silicon substrate thus minimizing
substrate losses
CMOS Reverse Interconnect Scaling
• Distance between top metal layer and silicon substrate currently about
1.5um per metal layer
• 10 metal layer technology by the end of the decade
* ”Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design”, B.Kleveland,
C.H.Diaz etal., JSSC, Oct 2001
Optimized CMOS RF
Performance
Noise
Architecture
-Reduced
complexity
Block
-High speed
design
Transistor
-Leverage
CMOS
performance
ft > 75GHz
Architecture
-Set design
goals based on
application
Block
-Noise shaping
(sigma-delta,
chopping, etc)
Transistor
-Noise
optimized
transistors
Power
Architecture
-Reduced complexity
-Power management
Block
-Innovative biasing
-Rail-to-rail designs
-Folded cascode
-AB CMOS biasing for
OTAs and amplifiers
-use fully differential
unity gain buffers
-DC current re-use
Transistor
- operate transistors
in linear region
Area
Architecture
-Hardware
share
-Maximize
digital
Block
-Multi-Layer
passives
-Hand optimized
layout
Transistor
-Optimized
layout
Process &
temperature
Architecture
-Maximize
digital
Block
-Self
regulating
biasing
Transistor
-Interdigitized
layout
-statistical
modeling
(Monte Carlo)
Wireless System Example
Radio/Baseband/MAC
The Bluetooth SIG
Bluetooth was introduced in 1998
by Ericsson, IBM, Intel, Nokia and
Toshiba.
Currently, more than 2000 adopters
Bluetooth enabled devices have started
to appear on the market (2001)
Visit www.bluetooth.com
Bluetooth in 3G
Bluetooth Technology
• Radio interface, operating in the
2.45 GHz "free" ISM band.
• Transmitting power less than 1 mW, typical operating range up to
10 meters (30 ft)
• Up to 730 kbit/s user data rates, both circuit and packet switched
connection
• Very cost effective design! Integration into computer and phone
chipsets is foreseen
• The initial creator group consists of these companies
The technology
•
•
•
•
•
•
•
•
•
•
Short range wireless technology
Range up to 100 meters
Operate at the unlicensed 2.4 ISM band
Form small ad hoc networks called piconets
– One master and 7 active slaves
1 Mb/s rate
Robust and reliable transmission using frequency hop spectrum
Support link level security including authentication and encryption
Plug-and-play service discovery
Supports legacy applications
Enable cheap single chip implementation at low power
Bluetooth usage scenarios
• Cable replacement
Protocol architecture
Audio
SDP
IP
BNE RFCOMM
Co
ntr
ol
Applications
L2CAP
Link Manager
Baseband
RF
• Bluetooth core consists of Link Manager, Baseband and
RF
• L2CAP, SDP, RFCOMM, BNE constitute the host stack
Bluetooth radio
1Mhz
. . .
79
12 3
83.5 Mhz
•
•
frequency hopping spread spectrum
– 2.402 GHz + k MHz, k=0, …, 78
– 1,600 hops per second
GFSK modulation
– 1 Mb/s symbol rate
transmit power
– 0 dbm (up to 20dbm with power control)
BNE RFCOMM
L2CAP
Link Manager
Baseband
RF
tro
IP
Co
n
•
Audio
SDP
l
Applications
Baseband
RF
tro
Co
n
Audio
• Form Piconets and Scatternets
• Use paging and inquiry procedures to synchronize
transmission hop frequency and clock of the
devices
• Implement channel access control based on Time
Division Duplex (TDD)
• Support data and voice links
Applications
IP
• Provide flow and error control
SDP
BNE RFCOMM
• Voice coding including the error
L2CAP
resistant voice coding scheme CVSD
Link Manager
(Continuous Variable Slope Delta)
l
Baseband
Link Manager
Establish links between devices
Piconet management
Security support including authentication, encryption and key
management
Link commands configuration and information
BNE RFCOMM
L2CAP
Link Manager
Baseband
RF
tro
IP
Co
n
Audio
SDP
l
Applications
L2CAP
Link Layer and Connection Adaptation Protocol (L2CAP)
Adapt upper layers protocols over the Baseband
Set up both connectionless and connection-oriented logical channels
Provide quality of service as well as packet segmentation and
reassembly
BNE RFCOMM
L2CAP
Link Manager
Baseband
RF
tro
IP
Co
n
Audio
SDP
l
Applications
Other protocols
RFCOMM
Emulate serial lines used by many legacy applications (e.g. dial-
up networking, LAN access)
Provide reliable and in sequence delivery of byte stream
Support multiple concurrent connections to one or more BT
devices
SDP (Service Discovery Protocol)
Bluetooth Network Encapsulation (BNE)
Encapsulate Ethernet over
the transport of IP
BNE RFCOMM
L2CAP
Link Manager
Baseband
Bluetooth for
RF
tro
IP
Co
n
SDP
Audio
attributes
supports service browsing
l
Applications
class
or
searches for services by service
Profiles
Main tool for interoperability between BT devices for a specific
usage model (application and devices)
Define the set of procedures (from different protocols) and the
messages required
Specify the order in which the procedures are combined
Define the roles of involved devices
Four general profiles have been specified
Generic Access profile
Serial Port Profile
Service Discovery Application Profile
Generic Object Exchange Profile
A number of application profiles has been specified e.g. LAN
Access, Dial-up Networking, File Transfer, Headset.
The profile tree
Dial-up networking
File Transfer
Cordless Telephony
Headset
Intercom
LAN Access
Fax
Networking Profiles
Telephony Profiles
Synchronization
Object Push
Object Exchange
Profiles
Generic Object
Exchange
Serial Port
Generic access
Transport
Profiles
Service discovery
application
Generic Bluetooth Access Profiles
Bluetooth HW
Bluetooth radio
Ericsson Bipolar radio
•
•
•
One fully tested unit-easy to use
Radio IC, filters and baluns are matched together
Ideal for embedded applications and applications requiring a flexible
form factor
Smallest size
• RF IC flipchip mounted-No package
• Filter,impedance matched baluns and switch integrated into
LTCC substrate
Lowest height
• Self shielding design!
Output power/receiver sensitivity
• Class 2 ("10m"), -70dBm at BER 0.1%
Modules
Ericsson Bluetooth™ Module
• Radio, Baseband and Flash memory
• Firmware: Supports all Bluetooth protocol layers up
to HCI
• UART and USB interfaces for high speed data
transfer rates
• PCM and USB interfaces for voice
• Low energy consumption
• Point to multi-point operation
• Built-in shield
• FCC and ETSI type approved
Bluetooth radio and baseband architectures
Radio Architectures
Super Heterodyne Receivers
‰
‰
‰
‰
Discrete IR and IF filters not amenable for Integration
Channel selection done at IF
Low dynamic range baseband circuits
Multi-Standard programmability in IF stage is difficult to achieve
Integrated Receivers
‰
‰
‰
‰
‰
Eliminates the need for discrete IR and IF filters
Signal + Blockers are translated to baseband
Channel selection done at baseband
High dynamic range baseband circuits required
Multi-standard programmability in baseband circuits
Direct Conversion Receiver
‰ Digital servo loop implementation using DSP (for offset cancellation)
‰ Baseband Filter programmability for multi-standard support
‰ Digitally programmable variable gain amplifiers
WCDMA/GSM/DECT
Multi-standard Receiver
Antenna
DCS1800
Band Filter
DCS1800
LNA
I Mixer
DC Offset
Cancellation
Channel/Antialiasing Filter
VGA
Multi-standard
ADC
Duplexer
Transmitter
Signal
DECT
Band Filter
WCDMA
Band Filter
GSM
DECT
LNA
WCDMA
LNA
WCDMA
DAC
Multi-band
Frequency Synth.
DAC
90 o
DECT
Baseband
Signal
Multi-standard
ADC
Q Mixer
DC Offset Channel/AntiCancellation aliasing Filter
Processor
VGA
‰ Zero-IF receiver architecture
‰ Multiple narrow-band LNAs are used to get the high gain
and low noise figure with low power.
‰ I/Q Mixers, low-pass analog filters, analog-to-digital
converters are shared for all the standards
‰ Advanced Offset cancellation algorithm is needed to solve
the DC offset problem
WCDMA/GSM/DECT
Multi-standard Receiver
Standardswitching Signal
I
DCS1800
1710~1785MHz
DECT
TDD and
Band Switch
W CDMA
From
Transmitter
1880~1897MHz
90 o
M ulti-band
Frequency
Synthesizer
Q
1900~1920MHz
‰ Single-pole-four-throw switch controlled by Standard-switching
Signal. (MURATA Filter and Switch)
‰ Only one LNA of the three works to save power controlled by the
Standard-switching signal
‰ Two I/Q mixers are shared by all.
FSK low-IF Receiver
‰ Bluetooth, HomeRF, IEEE 802.11b(FHSS)
‰ Image Rejection by Hartley Method
‰ Quadrature Detector for Demodulator
A Radio Receiver Architecture:
3G
A Radio Receiver Architecture:
WLAN
A Radio Receiver Architecture:
Low-IF/Zero-IF
Subsampling Receiver
‰ First downconversion to High-IF => no IR problems
‰ Sub-sampled at rate fs, where fIF = (n + ¼fs). Signal
subsamples and centres at fs/4.
‰ I/Q separation and mixing done easily in discrete domain.
‰ Sampling jitter noise is multiplied due to sub-sampling.
‰ IF filters must be high-Q if used for narrow-channel.
IF Filter
Signal
Power
ωfs/4
ωfs
ω2fs
ω3fs
ω
ωHigh-IF
ωRF
A Radio Receiver Architecture:
Subsampling
Adaptive Frequency Hopping
AFH
2.4
2 .4 2
2 .4 3 7
2 .4 4
2.46
F req u en cy (G H z)
2 .4 8
2 .4
2 .42
2 .4 37 2 .4 4
2 .4 6
F re q u e n cy (G H z)
‰ Employed in the next generation of Bluetooth
‰ Free of Interferers in the Bluetooth and Wi-Fi Channels
‰ Concurrent Reception without degrading QoS
2.48
Concurrent Receiver Architecture
with AFH
DSP
Wi- Fi Digital
Baseband
0/
90
T/R
2
Bluetooth
Digital
Baseband
800 MHz
0/
90
AFH
Control
PPF
ADC
LO1=1600 MHz
WLAN
PLL
LO2= 2400 MHz
Bluetooth
PLL
fref
Features of the Concurrent
Architecture
‰ LNA shared between the signal paths
‰ Two separate PLLs to generate LO signals for Wi-Fi and Bluetooth
receivers
‰ Two VCO outputs separated at least 800 MHz to avoid interaction
between LOs
‰ Signal separation by the channel select filter
GSM, WCDMA, Wi-Fi Standards
Review
GSM 900
Tx band: 890M-915MHz
Rx band: 935-960MHz
Duplex: FDD
Multiple Access: TDMA
Modulation: GMSK BT=0.3
Chip rate: 270.833 kbps
Channel Spacing: 200 kHz
GSM 900 - continued
CNR: 9dB
Sensitivity: -102 dBm
Intermodulation Test: -99dBm signal, -49dBm at 800k 1.6MHz
Adjacent Channel Test:
-82dBm signal, -73dBm 1st adj channel, -41dBm 2nd adj channel
Spurious Response Test: -99dBm signal, -31dBm @>6MHz
In-band & out-of-band blocker test:
WCDMA
Tx band: 1920M-1980MHz
Rx band: 2110-2170MHz
Duplex: FDD
Multiple Access: CDMA
Modulation: QPSK, RRC filter (rolloff=0.22)
Chip rate: 3.84M bps
Channel Spacing: 5M Hz
WCDMA - continued
CNR: 7dB
Sensitivity: -117 dBm
Intermodulation Test: -114dBm signal, -46dBm at 10, 20MHz
Adjacent Channel Test:
-103dBm signal, -52dBm 1st adj channel
Spurious Response Test: -114dBm signal, -44dBm @>15MHz
In-band & out-of-band blocker test:
WLAN 802.11b
Tx & Rx band: 2.4-2.4835 GHz
Duplex: TDD
Multiple Access: CSMA/CA
Modulation: DBPSK, DQPSK, CCK
Chip rate: 11M bps
Channel Spacing: 25M Hz, 5MHz raster
WLAN 802.11b - continued
CNR: 14dB (for 11M bps rate)
Sensitivity: -76 dBm
Intermodulation Test: -73dBm signal, -35dBm at 25, 50MHz
Adjacent Channel Test:
-61dBm signal, -35dBm 1st adj channel
Spurious Response Test: -73dBm signal, -35dBm @>25MHz
In-band & out-of-band blocker test:
Tri-Standard Receiver Architecture
and Specifications
• Receiver Architectures
• Frequency Synthesizer Architectures
• Receiver Tests
primary parameters for whole receiver
• Excel Sheet
primary parameters for each blocks
Tri-Standard Transceiver Architecture
Tri-Standard TX/RX Architecture
BB filter
LO2
DAC_I1
GSM 900
Duplex Filter
PGC
I
VCO
PA
GSM TX
0o
PFD
Filter
40 MHz
Q
+
Antenna
LO3
90o
BB filter
DAC_Q1
GSM RX
Balun
90o
LNA
LO2
DAC_I 2
Duplex Filter
DAC_I 1
PGC
PGC
RF Filter
IF Filter
modulator
DAC_Q 1
Q
+
LO2
DAC_Q 2
BB filter
DAC_Q 2
Data_Q
DAC_Q 3
DSP
PPF/LPF
DC notch
T/R Switch
LO1
90o
WCDMA RX
Data_I
DAC_I 3
0o
PA
RF Filter
DAC_I 2
I
WCDMA TX
System Select
Switch
mode
select
BB filter
WCDMA
VGA
Sigma Delta
ADC
Balun
90o
LNA
or
LO2
802.11 b
Sigma Delta
ADC
off-chip component
BB filter
not shared PLL
DAC_I 3
PGC
I
shared PLL
RF Filter
0o
PA
90o
+
Q
LO2
BB filter
DAC_Q 3
Tri-standard frequency synthesizer
Prescalar
(N1=7)
Program Counter
(P1=5)
(N1+1)/N1
P1
S1
Swallow Counter
(S1=3)
M1=38
LO3
40M Hz
/4
/5
M1
WCDMA
WLAN
10MHz
-
To WCDMA Tx LO1
PFD
LPF
CP
VCO
GSM
8MHz
-
LPF
CP
PFD
VCO
GSM/WCDMA/WI-Fi
Mode Select
N
16
16
16
16
P
29
29
26
30
k
S
1~13
3~16
6~18
2~12
2nd order
Sigma Delta Modulator
k
1/10 ~ 9/10
1/20 ~ 19/20
0
0.4
fout2
/2
/2
LO1
WCDMA/
WLAN
LO2
/2
M/(M+1)
fref
GSM Tx 8MHz
GSM Rx 8MHz
WCDMA 10MHz
Wi-Fi
10MHz
fout1= 380 MHz
M=NP+S
465 ~ 477
467 ~ 480
422 ~ 434
482 ~ 492
b(t)
Prescalar
(N=16)
Program Counter
(5 bit)
(N+1)/N
P
S
Swallow Counter
(5 bit)
GSM
Receiver Tests
• Sensitivity Test
=> NF
• Intermodulation Test => IIP3, selectivity, PN
• Spurious Response Test => IIP2, selectivity, PN
•Adjacent Channel Test => selectivity, PN
• Inband & out-of-band Blocker Test => selectivity,
ADC DR
Receiver Specs:
NF
GSM-900
9.8 dB
IIP3
IIP2
Phase Noise
IIP3 (800k, 1600kHz)=-15.5dBm
IIP2 (Δf=600k~1.6MHz)=28dBm
IIP2 (Δf=1.6M~3M)=48dBm,
IIP2 (Δf=>3M)=68dBm,
IIP2 (out-of-band)=114dBm
PN (Δf=100kHz) = -84dBc/Hz,
PN (Δf=300kHz) = -116dBc/Hz,
PN (Δf=500kHz) = -138dBc/Hz,
PN (Δf=1.5MHz) = -148dBc/Hz,
PN (Δf=2.9MHz) = -158dBc/Hz,
PN (out-of-band) = -181dBc/Hz
PN (Δf=3MHz) = -109dBc/Hz,
PN (Δf=8MHz) = -129dBc/Hz,
PN (Δf=13MHz) = -138dBc/Hz,
PN (2095MHz) = -138dBc/Hz,
PN (2185MHz) = -138dBc/Hz,
PN (2050MHz) = -152dBc/Hz,
PN (2230MHz) = -152dBc/Hz,
PN (2025MHz) = -167dBc/Hz,
PN (2255MHz) = -167dBc/Hz
33dB @ Δf=5MHz,
58dB @ Δf=10MHz
PN (Δf=14MHz) = -145dBc/Hz,
PN (Δf=39MHz) = -160dBC/Hz,
PN (out-of-band) = -170dBc/Hz
60dB @ Δf=25MHz,
73dB @ Δf=50MHz,
83dB @ out-of-band
WCDMA
9 dB
IIP3 (10M, 20M)=-17dBm
IIP2 (Δf=10MHz) = -10dBm,
IIP2 (Δf=15MHz) = 14dBm,
IIP2 (2050MHz~2095MHz) = 14dBm,
IIP2 (2185MHz~2230MHz) = 14dBm,
IIP2 (2025MHz~2050MHz) = 42dBm,
IIP2 (2230MHz~2255MHz) = 42dBm,
IIP2 (< 2025MHz, > 2255MHz)=72dBm
Wi-Fi
10.4dB
IIP3 (25M, 50MHz) = -5dBm
IIP2 (Δf=25MHz) = 23dBm,
IIP2 (Δf=50MHz) = 53dBm,
IIP2 (out-of-band) = 73dBm
Selectivity
21dB @ Δf=200kHz,
53dB @ Δf=400kHz,
71dB @ Δf=600kHz,
81dB @ Δf=1.6MHz,
91dB @ Δf=3MHz,
114dB @ out-of-banc
Block Level Specs:
A ssu m e L oss fo r O ff-C hip C om p on en ts:
A nten na:
G a in (d B )
S e le ctiv ity ( d B )
W I-F i
10
5
N F (d B )
1 .5d B
L P F /P P F
VGA
ADC
0
0~40
0
30
55
15
25
0
Δf = 25M H z
Δf = 50M H z
C o m b in e d
*
R e q u ire d
45
80
> 60
> 73
3
15
15
15
20
20
8 .7
< 1 0.4
IIP 3 (d B m )
(2 5 M , 5 0 M H z)
-5
12
30
30
20
20
-4 .5
>-5
IIP 2 (d B m )
Δf = 25M H z
Δf = 50M H z
60
70
90
90
90
90
5 7 .5
5 7 .7
>23
>53
10
5
0
0
14~40
0
G a in (d B )
S e le ctiv ity (d B )
W CDMA
1.5 dB , D up lexer: 1.5 dB , B alu n:
LNA
M ix e r
D C n o tc h
Δf = 5M H z
Δf = 10M H z
IIP 2 (d B m )
GSM
IIP 2 (d B m )
*
> 33
*
> 58
<9
15
15
(1 0 M , 2 0 M H z )
-5
12
30
30
20
20
-4 .5
>-1 7
Δf = 10M H z
Δf = 15M H z
60
70
90
90
90
90
5 7 .5
5 7 .7
>-1 0
>14
10
10
0
0
0~40
0
30
45
60
90
1 10
15
25
25
40
50
45
70
85
130
160
>
>
>
>
>
Δ f = 2 0 0 kH z
Δ f = 4 0 0 kH z
Δ f = 6 0 0 kH z
Δ f = 1 .6 M H z
Δf = 3M H z
N F (d B )
IIP 3 (d B m )
25
3
G a in (d B )
S e le ctiv ity (d B )
*
45
15
N F (d B )
IIP 3 (d B m )
25
(8 0 0 k, 1 .6 M H z)
Δ f = 6 0 0 kH z
Δ f = 1 .6 M H z
Δf = 3M H z
10
20
20
55
8 .7
21
53
71
81
91
3
15
25
25
30
30
9 .2
< 9 .8
-5
10
30
15
20
20
80
80
90
90
90
90
-1 1 .8
68
68
6 8 .7
> -1 5 .5
> 28
> 48
> 68
* E xtra a tte n u a tio n s a re n e e d ed in th e d ig ita l filter to m e e t th e se le c tiv ity re q u ire m e n t.
RX Signal Levels: GSM
Sys switch
-90.0
-58.0
-43.0
-33.0
-23.0
0.0
-102
-15
-121.0
RF Filter
-91.5
-59.5
-44.5
-34.5
-24.5
-1.5
-103.5
-16.5
-121.0
BALUN
-93.0
-61.0
-46.0
-36.0
-26.0
-26.5
-105
-18
-121.0
LNA
-94.5
-62.5
-47.5
-37.5
-27.5
-28.0
-106.5
-19.5
-121.0
Mixer
-74.5
-42.5
-27.5
-17.5
-7.5
-8.0
-86.5
-9.5
-98.0
DC notch
-64.5
-32.5
-17.5
-7.5
2.5
2.0
-76.5
0.5
-87.4
PPF
-64.5
-32.5
-17.5
-7.5
2.5
2.0
-76.5
0.5
-86.8
GSM Signal Levels @ input of the block
0.0
200kHz blocker
-20.0
400kHz blocker
600kHz blocker
-40.0
1.6MHz blocker
-60.0
3MHz blocker
Levels (dBm)
200kHz blocker
400kHz blocker
600kHz blocker
1.6MHz blocker
3MHz blocker
out-of-band blocker
min signal
max signal
input noise floor
-80.0
out-of-band
blocker
min signal
-100.0
max signal
-120.0
input noise floor
-140.0
-160.0
-180.0
-200.0
Sys
switch
RF Filter
BALUN
LNA
Mixer
DC notch
Blocks
PPF
VGA
ADC
VGA
-82.1
-72.3
-71.9
-100.4
-126.5
-145.9
-76.5
0.5
-86.3
ADC
-49.2
-48.2
-53.7
-97.6
-134.1
-165.3
-36.5
0.5
-46.3
RX Signal Levels: WCDMA
m in s ig n a l
m a x s ig n a l
5 M H z o ffs e t b lo c k e r
1 0 M H z o ffs e t b lo c k e r
1 5 M H z o ffs e t b lo c k e r
2 1 8 5 M H z b lo c k e r
2 2 3 0 M H z b lo c k e r
2 2 5 5 M H z b lo c k e r
in p u t n o is e flo o r
S y s s w itc h R F F ilte r
-1 1 7
-1 1 8 .5
-2 5
-2 6 .5
-6 3
-6 4 .5
-5 6
-5 7 .5
-4 4
-4 5 .5
-4 4
-4 5 .5
-3 0
-3 1 .5
-1 5
-1 6 .5
-1 0 7 .0 1
-1 0 7 .0 1
BALUN
-1 2 0
-2 8
-6 6
-5 9
-4 7
-4 7
-4 3
-3 3 .5
-1 0 7 .0 1
LNA
-1 2 1 .5
-2 9 .5
-6 7 .5
-6 0 .5
-4 8 .5
-4 8 .5
-4 4 .5
-3 5
-1 0 7 .0 1
(b ) fo r W C D M A M o d e
M ix e r
-1 0 1 .5
-1 9 .5
-4 7 .5
-4 0 .5
-2 8 .5
-2 8 .5
-2 4 .5
-1 5
-8 4 .0 1
D C n o tc h
-9 6 .5
-1 4 .5
-4 2 .5
-3 5 .5
-2 3 .5
-2 3 .5
-1 9 .5
-1 0
-7 8 .3 9
LPF
-9 6 .5
-1 4 .5
-4 2 .5
-3 5 .5
-2 3 .5
-2 3 .5
-1 9 .5
-1 0
-7 8 .2 1
VGA
-9 6 .5 0
-1 4 .5 0
-6 6 .5 8
-8 3 .6 6
-8 5 .7 5
-1 3 3 .9 2
-1 4 2 .0 2
-1 0 .0 0
-7 8 .0 4
ADC
-5 6 .5 0
-0 .5 0
-2 4 .6 2
-5 3 .7 5
-6 2 .8 8
-1 3 5 .1 3
-1 4 1 .1 8
-1 0 2 .0 2
-3 7 .8 7
RX Signal Levels: Wi-Fi
Sys switch RF Filter
min signal
-76
-77.5
max signal
-10
-11.5
25MHz offset blocker
-35
-36.5
50MHz offset blocker
-20
-21.5
out of band blocker
-10
-11.5
input noise floor
-100.99
-100.99
BALUN
-79
-13
-38
-23
-13
-100.99
LNA
-80.5
-14.5
-39.5
-24.5
-14.5
-100.99
(c) for WiFi Mode
Mixer
-60.5
-4.5
-19.5
-4.5
5.5
-77.99
DC notch
-55.5
0.5
-14.5
0.5
10.5
-72.37
LPF
-55.5
0.5
-14.5
0.5
10.5
-72.19
VGA
-55.5
0.5
-46.34
-55.42
-63.85
-72.02
ADC
-15.5
0.5
-46.34
-55.42
-63.85
-31.85
ADC DR Requirement:
ADC full Scale
headroom
6~10dB
Max Interferer
at ADC
Standards
Channel signal level
at ADC
ADC DR
Channel noise level
at ADC
10~20dB
ADC noise
Channel signal level
at antenna
Channel gain
GSM
WCDMA
WLAN
Channel
Bandwidth
200 kHz
3.84 MHz
22 MHz
DR requirements in the
Triple-standard receiver
70 dB
60 dB
52 dB
IIP3
requirement
20 dBm
CMOS Radio Challenges : Circuits
‰ Good RF characterization and modeling is needed scalable
models, passives, varactors
‰ Process technology with better substrate isolation
‰ Good modeling of substrate coupling effects, fully incorporated in
the design process
‰ Better design kits for RF design
CMOS Radio Challenges : System I
‰ Adopt system partitioning and mixed-signal strategy that lend
themselves naturally to deep-submicron CMOS
‰ Maximize digital content
‰ Requires high speed ADCs/DACs with good DR
‰ Incorporate antenna and front-end passives (RF filters, Balun,
switches) very early in the design process
‰ Adopt pragmatic SOC and SOP (System On Package) strategies
CMOS Radio Challenges : System II
‰ Good package models, fully incorporated in the design
porcess
‰ Mapping strategy for system to block specifications that is
amenable to CMOS design capability
‰ Complete understanding of the wireless system standards to
optimize the system and avoid unnecessary over design
‰ Test verification, qualification and certification
Low Power RF CMOS
Radio Design
Architecture :
-System architectures geared towards full integration
-Orders of magnitude power saving with the right architecture for the
application
Strategy:
- Power management
- power-efficient radio frequency planning
- Avoid driving 50-Ohm loads
- No power hungry driving buffers, and matching network
- Optimum system partitioning
-Maximize digital content
-Optimize interface to DSP, single chip solutions
- Power efficient transmitters
- Bring the PA on chip ,saves power of PA buffers
- Adopt a system design exploiting a nonlinear PA
- Chip-package and package-board co-design
Low Power RF CMOS
Radio Design
Block and Circuit :
Digital solutions to analog problems
Few folds of power savings with the right design
Strategy:
Optimize and avoid over-design
Exploit merged LNA/Mixer design and current mode Mixer/Baseband interface
Bias current reuse
Adaptive class AB biasing
Exploit MOS symmetry and operation in triode region
Digitally programmable RX gain control,TX power control implemented in RF
Smart power Data converters ,power scales with speed and/or resolution
Digital self-calibration to relax analog/RF performance requirements
RF CMOS Circuit Design
LNA
• First stage in the receiver chain
• sensitivity of the system
• determines the overall NF of the system
• Input matching
•Provide enough gain to overcome the noise of subsequent
stages (Sensitivity)
• Add as little noise as possible
• Accomodate a large dynamic range without distortion
LNA
Ld
Lg
Cgs
Ls
Typical single ended CMOS LNA
LNA Design
Common Source
• Amplifying device must be large and biased at high current to
reduce noise
• Large input device => large input capacitance thereby attenuating
the input signal thus magnifyinging ’noise’.
• Hence NF is minimized by proper choice of transistor size and bias
current at the operating frequency of interest.
• Min. NF is achieved varies with bias current and device size
NFmin ≅ 1+2.3(ω/ωT)
optimum device width Wopt ≅ 1/(3ωLsCoxRs)
LNA Design
• Zin = (gm.Cgs /Ls) + s(Lg+Ls) + 1/(s.Cgs)
Input matched with proper choice of gm,Cgs, Ls and Lg
Power constraints and minimum noise figure determine the
transistor size and hence gm and Cgs.
Choose Ls to achieve 50 Ohm match
Design Lg to tune out the additional capacitance at the
operating frequency
• Gain depends on the parasitics of Q1 and load.
• Cascode device improves reverse isolation.
•Additional stage may be needed to drive a 50 Ohm load
(heterodyne architectures).
LNA
Common Gate
• Input matching is simpler
Zin = 1/ (gm+sCgs)
• Higher linearity.
Vbias
Vin
• Better reverse isolation.
• However, higher NF due to limitations on the choice of gm.
Mixer
• Frequency translation by multiplying two signals
• cos(ωct). cos(ωst) = cos(ωc+ ωs)t +
upconversion
cos(ωc- ωs)t
downconversion
• Is NOT Linear Time Invariant (LTI)
• LTI systems cannot produce spectral components that are not in the input
• To ’MIX’, system has to be Non-Linear or Time Variant
• Important properties
• Conversion Gain
• Noise Figure – SSB vs DSB
• Linearity
• Port Isolation
Mixer
• ’Nonlinearity’ based Mixers provide frequency translation through
indirect multiplication.
• Assuming the nonlinearity is characterized by,
Vout = Σ An (Vin)n
If
Vin = Vc cos(ωct) + Vs cos(ωst)
Second order nonlinearity would result in a cross modulation component,
Vout(cross) = A2 Vc Vs [cos(ωc- ωs)t + cos(ωc+ ωs)t ]
VS cos(wSt)
VC cos(wCt)
Mixer
• Gilbert multiplier based mixers
• Switching transistors => multiply by square wave
VIF
VLO
VRF
Basic Oscillator Theory
Oscillator Circuits
• RC Oscillators
- easy to realise
- low, medium frequency
- poor phase noise performance
• LC Oscillators
- high frequency
- good phase noise performance
- suited for RF wireless applications
Voltage Controlled Oscillators (VCO)
• Wireless applications require that oscillators be tunable by a
control signal
• Control signal is usually in the form of a voltage
ω
ω2
Vcont
VCO
ωo
ω1
V1
V2
Vcont
VCO Design Parameters
LC VCO Design
Multi Band VCO
•
Multi-band operation is accomplished by tuning LC VCO with two control lines,
one for continuous tuning and the other for digital band selection. The
continuous tuning is used for PLL control and channel select. The digital tuning
is used for RF band selection using MOSFET varactors.
Examples:
1. A synthesizer for 900MHz/1800MHz GSM transceiver using wide-band IF
double conversion architecture with a fixed IF of 300MHz. A multi-band VCO
can be designed to operate in the bands of 1200MHz and 1500MHz. Fig. (a)
2. The VCO can be shared between 1800MHz frequency band (GSM, PCS,
WCDMA) and the GPS band 1600MHz. Fig. (b)
VCO band 1 VCO band 2
300MHz
300MHz
200MHz
f
IF 300MHz
900MHz
GSM band
1200MHz
1500MHz
(a)
f
1800MHz
1600MHz
1800MHz
GSM band
GPS
GSM/PCS/CDMA
(b)
A Dual-Mode Frequency Synthesizer
for 3G
A fully integrated dual mode frequency synthesizer for GSM and WCDMA with
maximum hardware sharing:
A Dual-Mode Frequency Synthesizer
for 3G (cont’)
Shared components
Non-shared
components
VCO
Integer frequency
divider
PFD, CP,
loop filter
Crystal
oscillator
GSM
15801630MHz
Divided by
246-254
Loop filter
ω3dB ~
320kHz
80MHz
WCDMA
17851845MHz
Divided by
357-369
/2 output divider,
/32 input divider,
2nd ΔΣ modulator
/25 input divider
Frequency divider:
• Integer frequency divider for GSM
• Fractional frequency divider for WCDMA
Dual band VCO:
• NMOS accumulation mode varactor for band-to-band switching
• PN junction varactor for in-band tuning
Shared components:
•PFD, CP, integer frequency divider, loop filter, VCO, reference signal, 70% of total die area
Performance Specifications of
Frequency synthesizers
• Frequency range
• Frequency resolution
• Lock time
• Spectral purity
phase noise
harmonics
spur
Broadband Synthesizer
General role
of a
frequency
synthesizer
for wireless
applications
Example of a
Wireless
Transceiver
Front-End
Frequency Synthesizer
Frequency
synthesizer
implemented
as a
phase-locked
loop (PLL)
Frequency generation scheme
Challenges
due to
incompatible
specifications
in the design
of PLLs
Spur level
Phase
noise
Locking
time
Power
consumption
Challenges
addressed in
this work
Area
Goal
Specs
Frequency
range
Frequency generation scheme II
By running the VCO at high frequencies and
using fixed dividers before the output, we can
theoretically lower the phase noise floor by a
maximum of
30log(n)
where n is the division ratio
This is mainly due to:
• The reduced VCO tank parallel resistance at higher
frequencies
• The division factor
Frequency generation scheme III
Proposed scheme:
VCO
with switchable
capacitors and
inductors
Advantages:
• Low phase noise
• Wide frequency range
• Small area due to the smaller inductors at high frequencies
Standards chosen
Standard
Start
Freq.
Original
(MHz)
End
Freq.
Original
(MHz)
Start
Freq.
×2
(MHz)
End
Freq.
×2
(MHz)
Start
Freq.
×4
(MHz)
End
Freq.
×4
(MHz)
DCS1800
1710
1880
3420
3760
6840
7520
WCDMA II
1850
1990
3700
3980
7400
7960
WCDMA III
1710
1880
3420
3760
6840
7520
DECT
1881.792
1897.344
3763.584
3794.688
7527.168
7589.376
IEEE802.11b/g
2412
2472
4824
4944
9648
9888
IEEE802.11a
5150
5825
10300
11650
20600
23300
Bluetooth
2402
2480
4804
4960
9608
9920
Implementation of the VCO
•
•
•
•
Vtune
•
Vcap
L1
Vind
L1
•
L2
L2
PMOS transistors to reduce 1/f noise
L1: L=320pH and Q=16
L2: L=280pH and Q=24
The RF switch acts as a filter and its loss is
less than 1dB when it is ON.
Frequency ranges:
– When only L1 is selected, the frequency
range is 6.8GHz to 8GHz
– When all the inductors are selected, the
frequency range is 4.8GHz to 6GHz
The resistors are used for DC biasing of the
source/drain terminals of the MOS switch
devices.
Implementation of the frequency
divider
•
•
•
One divider core
Input frequency range is 4.5GHz to
8GHz
Differential prescaler implementation
designed to divide by 2 and by 4 and
to generate quadrature signals at the
same time.
The design is not fully-differential
which allows the circuit to operate
with a wide frequency range and
makes it less sensitive to variations
in the input voltage.
Simulation results of the combination
VCO-dividers
tp
Inductor switch
ON - OFF
Oscillator startup
VCO @ 5.3 GHz
tr
VCO @ 7.4 GHz
tset
tf
tset
Switching the inductors:
• Control signal has a period tp of
5ns and a rise time tr and a fall
time tf of 0.5ns.
• Steep rise or fall flanks of the
switch do not influence much the
performance of the VCO due to
the parallel-serial placement of
the switch over the inductors.
• A settling time (tset) of 1.1ns is
observed, which is due to the
loop-back of the VCO signal.
• The output amplitudes differ due
to the unequal losses at 7.4GHz
and 5.3GHz.
Layout of the complete design
1.5mm
1.6mm
•
•
2
1
3
•
0.18µm CMOS
Careful floor planning was made. For
example, the layout of the dividers
was done in a symmetrical manner so
as to avoid I/Q imbalances.
Blocks:
1. VCO
2. buffers for 50Ω matching with ESD
protection and for driving the
divider input load
3. dividers by 2 and 4 with 50Ω
buffers and ESD protection
Analog Baseband Chains
Goals/Motivation
• Develop baseband chains for 3G Integrated Wireless
receivers
– Tailored for Integrated Cellular,cordless and Indoor applications
– Based on regular modules for short design time
• Investigate and propose new CMOS circuits and
techniques suitable for integrated receivers
– Low Power Consumption
– Digitally Programmable
– Simple and Robust Filter/VGA/OTA circuit structures
Digitally Programmable CMOS Filter/VGA
for wireless base stations
Specifications
• Signal of Interest
: 12MHz - 23MHz
• Pass Band of Filter
: 12MHz - 23MHz (-0.5dB corner points)
• Pass Band Ripple
: < 0.5dB
• Stop Band
: 0MHz - 5MHz and after 40MHz
• Stop Band Attenuation
: > 25dB
• Programmable Gain
: -10 dB to 30 dB in steps of 1 dB
• Linearity (IMD)
: > 53 dBc
• Signal to Noise Ratio
: > 57 dB (noise integrated over 5MHz Bandwidth)
Proposed Filter/VGA Chain
*LPF: Low pass filter
*HPF: High pass filter
2nd order
LPF
6dB step
Vin+
1st order
HPF
3dB step
2nd order
LPF
6dB step
+6 dB
(-12~0) dB
Vin+6 dB
1dB step
Vout+
Vout-
(-4~0) dB
attenuator
(-12~0) dB
attenuator
2nd order
LPF
+6 dB
+6 dB
2nd order
HPF
0 dB
(-12~0) dB
attenuator
6dB step
(-12~0) dB
attenuator
attenuator
2nd order
LPF
2nd order
HPF
+6 dB
• 6 dB gain buffers in 5 filter stages provide fixed 30 dB gain.
• Use filter stages with voltage gain to eliminate the need for VGA stages.
• 5 digitally programmable attenuators attenuate 30 dB gain in 1 dB steps of gain
Vin+
C1
R
R
Vin+
+
+
C2
Vout+
+
Buffer
R
R
_
Vout+
Buffer
_
_
C2
+
_
Vout-
Vout-
Vin-
C1
Vin-
Use the buffer circuit to implement fully
differential Sallen-Key filter sections.
Use resistive chain to attenuate the gain
In 1/3/6 dB steps.
Filter tuning is achieved by 4 bit binary
weighted capacitor array.
Programmable gain variation: -10 – 30 dB
5 bit digital control
The frequency response of
VGA/Filter chain
Multi-Standard Receiver
VGA
RF
Filter
ADC
LNA
LO
RF
Filter
Bandwidth control
LNA
Gain Control
LO
RF
Filter
LNA
LO
RF
Filter
VGA
LNA
ADC
LO
DSP controls
DSP
DC offset
control
•DC Offset
•Gain of VGA
•Bandwidth of LPF
How to make Multi-Standard Receiver digitally programmable in CMOS?
1) R-2R ladders
2) Digitally Controlled Current Follower by applying CDN.
3) Digitally Controlled Filter by applying R-2R ladders and
DCCF
R-2R ladders
I
b1
b3
b2
b4
bn
R
I
V
2R
Ir
Ir/2
Ir/4
Ir/2
2R
2R
Ir/8
2R
R
R
R
R
Ir
2R
2R
Ir/4
R-2R
β
Ir/8
•Digital control word is applied through MOS switches and the resistors are
implemented by poly layers in CMOS process.
•The total resistance of the ladder is controlled by closing or opening the switches to
realize binary-weighted currents with a resistance ratio of 2.
Current Division Network (CDN)
Iin
Iin/(2n)
Iin/4
Iin/2
Vdd
d1
d1
d2
d2
dn
dn
Io
(Virtual ground)
•Digital control word is applied through MOS Switches and the current flowing is controlled
•Due to the geometrical symmetry of MOS device, The linear current inter relationships
in the resistive network are maintained in the MOS implementation.
Digitally Controlled Current Follower
α
VDD
M13
M9
M10
M3
Ibp
M7
M8
Ix
M1
X
DCCF
Z
Izp
VDD
M2
CDN
M11 Vb
M5
Mc
M12
X
Vc
Z
M6
M4
Isb
VSS
•The DCCF is a current follower with programmable gain that can be controlled digitally
•Use a CDN to provide precise gain characteristics by precise digital trimming.
Digitally Programmable
Fully Differential Filter
Vcm
α1
C1
R
2
R1
R
Rin
R2R
Vi
x DCCF z
R3
R2R
1x
CMFB
Rin
R2R
x DCCF z
α1
α2
x DCCF z
C2
R2
R2R
1x
CMFB
R3
R2R
1x
C1
R
2
R
R1
x DCCF z
α2
Vo
R2
R2R
1x
C2
Vcm
•The filter is used for channel selection in a multi-standard wireless receiver
•Cuff-off frequency and DC gain are controlled digitally
The die photo of
6th order digitally programmable filter
Measured AC response: PDC and IS-54
Measured AC response: GSM
Measured AC response: WCDMA
Summary of Multi-Standard Channel
Select Filter Performance
Filter
6th-order Butterworth
Technology
0.5 um CMOS
Chip area
1.25 mm2
Supply voltage
2.7 V
Current consumption
2.25 mA
Frequency tuning range
5kHz-5MHz
Gain
18 dB
Statistical gain variation(25 chips)
0.44 dB
IIP3(Inband)
28.3/25.6/23.7/21.9 dBm
PDC(IS-95)/GSM/IS-95/WCDMA
IIP3(stopband)
61/59.5/56/51.4 dBm
PDC(IS-95)/GSM/IS-95/WCDMA
Input referred noise
30/45/69/85 uV
PDC(IS-95)/GSM/IS-95/WCDMA
Stopband rejection
80/80/76/70 dB
PDC(IS-95)/GSM/IS-95/WCDMA
SFDR
92/89/84/80 dB
PDC(IS-95)/GSM/IS-95/WCDMA
Passband ripple
0.2 dB
PSRR (passband)
40.3 dB
Compact TDD Wireless Radio
Transceiver
Motivation
• Silicon estate!
– Baseband circuitry processing I/Q signals for both
RX and TX paths could occupy up to 50% of the
total die area
– Especially for a multistandard transceiver in a
single chip and for a sensor node in a sensor
network
Sample Die Photo
R. Ahola et al, “A Single-Chip CMOS Transceiver for 802.11a/b/g Wireless
LANs”, IEEE J. Solid-State Circuits, vol.39, no.12, pp2250-2258, Dec.2004
Direct Conversion Transceiver
DC Offset Cancellation
I
LPF
fRF
VGA
ADC
f
Q
LPF
LNA
Frequency
VGA
DC Offset Cancellation
0
Synthesizer
T/R
Switch
PA
ADC
f
I
VGA
LPF
DAC
VGA
LPF
DAC
Q
Idea
• Design one programmable baseband chain
• Share one baseband chain with receiver and
transmitter
– Time-Division Duplexing (TDD) systems only
Compact TDD Wireless
Transceiver
I
ADC
DC Offset Cancellation
Q
LNA
LPF
VGA
LPF
VGA
ADC
Frequency
Synthesizer
PA
I
DAC
DC Offset Cancellation
Q
DAC
Compact TDD Wireless Transceiver:
Receive Mode
I
ADC
DC Offset Cancellation
Q
LNA
LPF
VGA
LPF
VGA
Frequency
Synthesizer
DC Offset Cancellation
ADC
Compact TDD Wireless Transceiver:
Transmit Mode
DC Offset Cancellation
LPF
VGA
LPF
VGA
Frequency
Synthesizer
PA
I
DAC
DC Offset Cancellation
Q
DAC
Design Issues
• TDD systems only
• Dynamic behavior due to switches
– Settling time
• DC feedback loop
• Automatic Gain Control (AGC) loop
– Synchronization with RF T/R switches
DC Offset Cancellation in
Direct Conversion
Multistandard Wireless Receivers
Possible WiMAX/Super 3G Radio
• DC offset corrupts the signal and may saturate the analog
baseband stages
Generation of DC Offsets in DCR
• Transistor mismatches in the signal path
• Second-order intermodulation (IM2) of the
components such as LNAs, mixers, and
filters…
• Self-mixing of LO signal leaking into LNA
input and mixer RF input
• Self-mixing of LO signal leaking into, radiated
from, and reflected back to antenna
• Self-mixing of strong in-band interferers
leaking into mixer LO input
DC Offsets Generated by Three Self-Mixing
Mechanisms
LNA
LNA
LO Leakage
LO Leakage
Self-mixing due to LO leakage
Self-mixing due to LO leakage radiated
LNA
Interferer Leakage
Self-mixing due to interferer leakage
Modeling of DC Offsets
• Goal: Identifying static (time-invariant) and
dynamic (time-varying) DC offsets generated
by three self-mixing mechanisms:
– Self-mixing due to LO leakage (2 cases)
– Self-mixing due to interferer leakage
• Assumption: components (e.g. LNA, mixer,
filter) are ideal (No nonlinearities)
• I-branch only
Ideally…
Received signal:
u(t)
b(t): information signal
fc: carrier frequency
LNA
s(t)
A: LNA gain
y(t)
LPF
l(t)
LO signal:
Using complex envelop representation…
x(t)
Self-Mixing due to LO Leakage
LNA
LO Leakage
u(t)
s(t)
LNA
y(t)
l(t)
K2
K1
LPF
x(t)
Self-Mixing due to LO Leakage
u(t)
s(t)
LNA
y(t)
l(t)
K2
K1
Static DC offset
LPF
x(t)
Self-Mixing due to LO Leakage
Radiated
LNA
LO Leakage
u(t)
s(t)
LNA
y(t)
l(t)
Doppler Shift
K3
LPF
x(t)
Doppler Effect
fDS: Doppler shift
v: relative speed
fc: carrier frequency
c: speed of light
α: angle of arrival
Maximum Doppler shift (α = 0) when
Average human walking speed: 3.5 mph
Average vehicle driving speed: 60 mph
Self-Mixing due to LO Leakage
Radiated
u(t)
s(t)
LNA
y(t)
LPF
l(t)
Doppler Shift
K3
Dynamic DC offset
x(t)
Self-Mixing due to Interferer Leakage
LNA
Interferer Leakage
u(t)
s(t)
LNA
K4
y(t)
l(t)
LPF
x(t)
Self-Mixing due to Interferer Leakage
( fi: interferer frequency )
u(t)
s(t)
LNA
K4
y(t)
LPF
x(t)
l(t)
Dynamic DC offset
( fo= fi – fc )
Static DC offset
Static and dynamic DC offsets
Static DC offset
Dynamic DC offset
Dynamic DC offset
( fo= fi – fc )
Static DC offset
DC offsets in Frequency Domain
Static DC offset
Dynamic DC offset
at unknown frequency fo
Desired signal
0
fo
f
9To cancel static DC offset Æ High-pass filter
9To cancel dynamic DC offset Æ Tunable Notch filter
DC Offset Cancellation in Analog
Domain
I
BPF
Canceller
LPF
VGA
ADC
Canceller
LPF
VGA
ADC
LNA
90 o
Q
DC Offset Canceller in Analog
Domain
• AC Coupling
• High Pass Filter
• DC Feedback Loop
H(s)
A2
Transfer function:
A1
9 Good for static DC offset cancellation
9 Difficult to remove dynamic DC offset
DC Offset Cancellation in Digital
Domain
I
LPF
VGA
ADC
DAC
BPF
LNA
DSP
DAC
90 o
Q
LPF
VGA
ADC
DC Offset Canceller in Digital
Domain
• Measure DC offset in digital domain and subtract it
• For TDMA burst mode system:
– Measure DC offset using short known symbols in preamble
– Subtract the measured value during reception using DAC
• For TDMA burst mode QPSK system:
– Accumulate DC offset corrupted signals for a predetermined time
period to obtain the average of DC offset
– Subtract the average value using DAC
9
9
9
9
Good for dynamic DC offset cancellation
Still difficult to remove fast varying dynamic DC offset
Need DAC for subtracting
For specific systems only, e.g. TDMA systems
For Multistandard DCR…
• The most concern is losing information…
• The most important factor to consider
Æ Information is at/near DC?
• Modulation schemes!
– FSK: no information at DC
– PSK: considerable energy around DC
• But in wideband systems
Æ HPF won’t degrade the performance much even in PSK
• Most of WLAN and 3G standards use wideband systems
Wireless LAN Standards
3G Standards
DC Offset Cancellation for Multistandard
DCR
• Static DC offset cancellation
– Should be done in analog domain
– Tunable HPF or DC feedback loop
– To avoid significant degradation, cutoff frequency of HPF
should be about 0.1% of data rate [1]
• Dynamic DC offset cancellation
– Should be done in digital domain
– Should be working for most of systems
ÆAdaptive filtering technique! (adaptive noise canceller)
[1] B. Razavi, “Design Considerations for Direct-Conversion Receivers”, IEEE Transactions on
Circuits and Systems II, vol. 44, no. 6, June 1997
Multistandard DCR with DC Offset
Cancellation I
Using tunable high-pass filters for static DC offset cancellation
Static DC Offset
Canceller
I
HPF
LPF
VGA
ADC
Control
LNA
Signals
Dynamic
DC Offset
Canceller
DSP
90 o
Q
HPF
Static DC Offset
Canceller
LPF
VGA
ADC
Dynamic
DC Offset
Canceller
Multistandard DCR with DC Offset
Cancellation II
Using tunable DC feedback loops for static DC offset cancellation
Static DC Offset
Canceller
DC
Feedback
I
LPF
VGA
ADC
Control
LNA
Signals
Dynamic
DC Offset
Canceller
DSP
90 o
Q
LPF
DC
Feedback
Static DC Offset
Canceller
VGA
ADC
Dynamic
DC Offset
Canceller
Tunable DC Feedback Loop as
Static DC offset canceller
Gm
R
Vin
Transfer function:
C
A
Vout
Frequency Response for Two Standards
Bode Diagram
60
Blutooth
802.11b
55
Magnitude (dB)
50
45
40
35
30
1
10
2
10
3
10
4
10
Frequency (rad/sec)
5
10
6
10
7
10
Adaptive Noise Canceller (ANC) as
Dynamic DC offset canceller
• To track/cancel the dynamic DC offset in real-time,
ANC would be the best choice!
– ANC need both primary signal and reference signal
Primary signal:
d(n)
e(n)
d(n) = s(n) + n1(n)
e(n) = d(n) - y(n)
≈ s(n)
w(n)
Reference signal:
u(n) = n2(n)
u(n)
Adaptive
y(n)
Filter
By adapting w(n), y(n) ≈ n1(n)
signal (s(n)) and noises (n1,2(n)) are uncorrelated
noises (n1(n) and n2(n)) are correlated
Dynamic DC offsets
9 Dynamic DC offset Æ sinusoid at fo and fDS
Dynamic DC offset
Æ Will be cancelled by static DC offset canceller as fDS is very low
Dynamic DC offset
( fo= fi – fc )
Æ Will be cancelled by dynamic DC offset canceller
ANC as Dynamic DC offset canceller
9 ANC without external reference source
(= Adaptive linear forward predictor)
s(n): broadband signal containing information
o(n): sinusoidal dynamic DC offset at frequency fo
s(n) + o(n)
d(n)
e(n)
e(n) = d(n) - y(n)
≈ s(n)
w(n)
Delay
(Δ)
u(n) = s(n - Δ) + o(n - Δ)
u(n)
Adaptive
y(n)
By adapting w(n), y(n) ≈ o(n)
Filter
Adaptive Noise Canceller
s(n) and s(n - Δ) are uncorrelated because s(n) is a broadband signal
o(n) and o(n - Δ) are correlated because o(n) is a sinusoid
How to Adapt the FIR Filter w(n)
• Least Mean Square (LMS)
– Better tracking
w(n+1) = w(n) + μ u(n) e*(n)
– Normalized LMS (NLMS)
w(n+1) = w(n) + μNLMS u(n) e*(n)
μNLMS = 1/(μ-1 + ||u(n)||2)
• Recursive Least Square (RLS)
– Better convergence
Simulation Setup
• Desired signal: 1 Mbps BPSK signal
• Dynamic DC offset: 1 MHz and magnitude
bigger than signal by 30dB
• Adaptive filter length: 9
• Delay: 5
• Adaptation using NLMS algorithm:
w(n+1) = w(n) + μNLMS u(n) e*(n)
μNLMS = 1/(μ-1 + ||u(n)||2), μ = 0.001
1000-Symbol with Ideal Channel
AFP input signal d(n) corrupted by offset
corrected signal and desired signal
40
20
e
s
15
30
10
20
5
10
0
0
−5
−10
−10
−20
−15
−30
−40
−20
0
2000
4000
6000
8000
10000
12000
−25
0
DC offset corrupted input d(n)
(
2000
4000
6000
8000
10000
12000
: DC offset canceller output e(n)
: when no DC offset applied)
1000-Symbol with Ideal Channel
(raw data − demodulated data)2
(raw data − demodulated data)2
2
2
1.5
1.5
1
1
0.5
0.5
0
0
−0.5
−0.5
−1
100
200
300
400
500
600
700
800
900
Squared error of demodulated data
without cancellation
1000
−1
100
200
300
400
500
600
700
800
900
Squared error of demodulated data
with cancellation
1000
BER Performance with AWGN
Channel
BER − BPSK
0
10
Without dynamic DC offset canceller
−1
10
With dynamic DC offset canceller
−2
BER
10
Theory without DC offset
−3
10
−4
10
−5
theory w/o offset
offset with cancellation
offset w/o cancellation
10
−6
10
0
1
2
3
4
5
Eb/N0 [dB]
6
7
8
9
10
–
–
–
–
–
–
–
Rx
Tx/Rx
Rx
Tx
Tx
Band Select
(5GHz / 2.4GHz)
Bandwidth Select
Rx
Tx
DSP/Modem
–
Fully integrated 802.11a, 802.11g and
802.11b WLAN radio transceiver
Multi standard programmable
bandwidth
Front end configurable for all
frequency bands
Minimum external components
• Integrated VCO, LNA and filters
Manufactured in 0.18µm CMOS
48 QFN/MLF packaging, 7x7mm
footprint
Analog I/Q interface
Lowest power consumption
Partners for complete chip-set
Digitally
Programmable
Analog Baseband
–
Configurable RF
TripleTraCTM 802.11 a/b/g
WLAN Radio Transceiver
Multi-standard WLAN chipset
PA
RF
5.8GHz
5.2GHz
5.8GHz
5.2GHz
PA
RF
Modem
2.4GHz
DSSS
2.4GHz
PA
partner
Modem
OFDM
Analog
Base-band
TripleTraCTM
802.11
MAC
MAC,Modem
partner
Frequency Plan for Multi-band Operation
RF Spectrum
2400
2485
5150
5350
5470
5725
5825
f (MHz)
Local Oscillator ( LO1)
3840
4160
4320
f (MHz)
IF
1310
1565
f (MHz)
Local Oscillator (LO2)
0
f (MHz)
0
f (MHz)
Baseband
5GHz/2.4GHz Multi-Band Transceiver
Without Image Rejection
5GHz LNA
RX RF Mixer
RX IF Mixers
LPF
I
2GHz LNA
Q
LPF
LO1
LO1
5G Preamp
LO2
LO2
TX IF Mixers
TX RF 5G Mixer
I
LPF
Q
2G Preamp
LPF
TX RF 2G Mixer
3.3mm
Die photo of multi-standard
WLAN radio
3.6mm
•
•
•
Die area ~12mm2
48-pin QFN pkg
0.18µm 1P6M
CMOS
Radio test results
RX2 2437MHZ
RX5 5240MHZ
Radio test results
Radio test results
Radio test results
Phase Noise at PA output
Radio test results
Measured Performance
Summary
ScannerIC™
•
Highly-integrated single-chip Discovery/Mobility device that enables users to
detect 802.11b/g Access Points (AP) and find an optimum location for connectivity
– Monitors beacon frames and extracts SSID
– Measures the signal quality of the WLAN medium, and the network condition including
available bandwidth and channel access delays
– Enables seamless AP hand-off
•
Implements the 802.11b receiver chain and baseband, as well as a small portion
of the standard MAC
–
–
–
–
–
Only external receiver components required are a balun and a bandpass filter
Pin Count: 20
Low Power Consumption: <150 mW
High Sensitivity: -82dBm
0.18um CMOS Process
HWD
MURATS™
•
•
Single-chip MUlti Radio Access Technology Scanner targeting next
generation multi-standard communication appliances
– GSM, WCDMA and WLAN scanning and radio measurement
solution
– Supports fast and seamless handover/roaming between
heterogeneous radio technologies
– “Always Best Connected” - ensuring that users are always
connected to the best RAT (Radio Access Technology) through
cell/channel selection or reselection
Implements the receive chain only operating on low rate broadcast
channels
– Several complex functions not needed including power control,
security, channel demultiplexing, variable spreading, channel
synthesizer
– High block sharing including micro-controller, equalizer, channel
decoder, CRC check, ADC, analog RF blocks
– Other RATs added in the future making the device a universal
scanner
SWIP™
•
•
Single-chip WLAN Internet Phone targeting the high volume
residential/SOHO market
–
VoIP based on SIP standardized by IETF in RFC 2543/3261 & TIA/TR41. Supports SIP
voice and instant messaging. Implements the emerging 802.11e QoS standard
–
Optimized to support the basic rates of 802.11 WLANs, particularly 1-2 Mbit/s
Contains all the blocks required to build a low-cost VoIP/WLAN
handset:
–
Low power CPU core, voice codec, embedded memory, various user interface blocks
and 802.11 PHY (including PA)
–
Pin Count: 96
–
Low power consumption: <300mW
–
High sensitivity: -82dBm
–
20dBm transmit power
–
0.18um CMOS Process
–
Supports several low power mode operations
SWIP Hardware
Architecture
SWAP™
•
Single-chip WLAN Application Platform optimized for low power, small
form factor and low cost
•
Targeting highly-portable multimedia and IP telephony appliances
•
Same hardware as SWIP™, but excludes the voice codec & the VoIP
engine
–
802.11 MAC, Baseband, RF Front-end and PA
–
Supports WLAN basic rates of 1-2 Mbit/s via UART interface
–
Pin Count: 56
–
Low power consumption: <250mW
–
High sensitivity: -82dBm
–
20dBm transmit power
–
0.18um CMOS Process
–
Supports several low power mode operations
–
Underlying design is 11 Mbits/s capable
Over-Design and Yield Loss in RFICs
Parasitic Effects
Capacitive/Electromagne
tic on-chip Coupling
Random Process
Variations
Substrate Noise
Coupling
Element Mismatches
Inaccurate Models
Loading &
Interconnects
Degrade Performance
Decrease in Yield
Over-design, Non-optimal
Power Solutions
Is only one silicon spin important?
• YES!
• Three reasons
– NRE costs
– Mask set costs
– Time to market
NRE Costs
• NRE stands for nonrecurring engineering
• It is the cost of paying the design team’s salaries and
overhead for the project duration
• Typical design cycle
Specification
2-4 weeks
1
r
o
f
Test onths
m
9
1-3
months
6
Fabrication
8 weeks
Design
3-6 months
!
e
l
c
y
c
n
g
i
s
e
d
Layout
2-4 months
Mask Set Costs
Mask Set Cost
$3,000,000
$2,500,000
$2,000,000
$1,500,000
$1,000,000
$500,000
$0
0.35
0.25
0.18
0.13
0.09
Feature Size (um)
Source: http://www.m2000.fr/products.htm
0.065
Total Cost Per Spin
• The cost for a team of 10 people for 9 months is
over $500,000
• For a common 0.18 process, the cost of a single
mask set is $250,000
• So the dollar cost for the first spin is over
$750,000.
• Additional spins take less time and cost less, but
can still cost more than $400,000
• However, they can have an impact on the
business
Time for Extra Spins
• Even if the dollar cost for the extra spin is not great,
the time cost can be the biggest expense
• If the error is small and can be fixed in 1 month, it still
takes the 8 weeks to fabricate the new chip
• Then the new chip has to be tested again, which is
another month slip
• So in the best case, a respin costs about 4 extra
months
• This 4 months is time missed in the market, and time
the engineers are not working on the next product
Proposed Methodology
Developing a new methodology in
designing radio systems based on:
Calibration
‰Monitoring block
performance
off chip passives
‰ Developing self calibration)
‰ Global control of parameters
Digital Band Select
Digital Data Rate &
Channel Select
DSP
Rx
Digitally Programmable
Analog Baseband
‰ Developing self awareness
Rx
Frequency
Synthesizer
‰ Study of the effect of each block
non-ideality on the specific system
parameter (sensitivity analysis).
Configurable RF
‰ Study of the key system
parameters (BER, EVM,…)
Proposed Methodology
Adaptive DSP, Digital Auto-Calibration
Circuit
Control
Parameters
Analog / RF
Block
A/D
Block/Sub-System
Adaptive
DSP Algorithm
System
Master Control
¾ Initialization
¾Schedule Supervision and correction
Shared Resources
¾ A/D and D/A
Our Vision for a First-Pass Multi-Mode
Receiver
Calibration
Digital Band Select
Digitally
Programmable
Analog Baseband
off chip passives
Frequency
Synthesizer
Rx
Rx
Configurable RF
“Smarts”
Digital Data Rate &
Channel Select
for
First Pass
DSP
GSM,
WCDAM,
WLAN
WiMAX,….
AGC,
I/Q balance,
DC Offset,….
Why Digital Calibration?
•
Demo a First-Time-Right
radio
Robust
– A mature design methodology
•
DSP
FPGA
– Enables use of sophisticated signal
processing algorithms
–
•
Can be part of a digital baseband in a
wireless chipset
Mature
– Significantly more mature design
methodology compared to RF/Analog
•
scalable and Flexible
•
Minimum risk, 1st time-right.
Chip under test
Multi-standard radio receiver (WiMAX/WLAN,
OFDM UWB)
implemented on TSMC0.13 um technology.
Focus on RF RX System Parameters
Conclusion I
• Design Techniques achieving maximum hardware share at
minimum power consumption (configurable radio, programmable
analog baseband)
• Improvement in technology, characterization, packaging techniques
are needed
• Migration to future wireless standards for higher data rates and
multimedia applications
• Eventual convergence of LAN, WAN, PAN infrastructures for
seamless wireless communication
•Need for higher levels of integration, available only in CMOS
technologies
• Technology scaling favors multi GHz RFCMOS
• New challenges, careful system partitioning, good mixed signal
strategy, maximize digital content
Conclusions II
• As we migrate to high data rates beyond 3G,
radio design will become more complex
• CMOS has adequate performance to meet
the challenge
• Innovations in frequency planning and radio
architecture design will make it happen
• Low power design must be incorporated at all
levels, architecture, block and circuit
Thank You!