Overview
 Last lecture
 Ripple and Carry-Lookahead Adders
 Today
 ALU
 An Introduction to Hardware Description Languages (HDL)
CSE 370 – Winter 2002 - Hardware Description Languages - 1
Carry-lookahead implementation (cont’d)
 Carry-lookahead logic generates individual carries
 sums computed much more quickly in parallel
 however, cost of carry logic increases with more stages
Cin
Cin
A0
B0
S0 @2
C1 @2
A0
B0
C1 @3
A1
B1
S1 @3
C2 @4
A1
B1
A3
B3
S1 @4
C2 @3
A2
B2
S2 @5
C3 @6
A2
B2
S0 @2
S2 @4
C3 @3
S3 @7
Cout @8
A3
B3
S3 @4
C4 @3
C4 @3
CSE 370 – Winter 2002 - Hardware Description Languages - 2
Gi = Ai Bi
Pi = Ai xor Bi
Gi, Pi, available at time 1
Cin
A0
B0
S0 @2
GiPi + GjPj available at
time 3
G0 + P0 C0
A1
B1
S1 @4
G1 + P1 G0 + P1 P0 C0
G2 + P2 G1 + P2 P1 G0
+ P2 P1 P0 C0
GiPi available at time 2
GP0 available at time 2
GG0 available at time 3
A2
B2
S2 @4
A3
B3
S3 @4
GP0= P3 P2 P1 P0
GG0= G3 + P3 G2 + P3 P2 G1 +
P3 P2 P1 G0+ P3 P2 P1 P0 C0
CSE 370 – Winter 2002 - Hardware Description Languages - 3
Carry-lookahead adder
with cascaded carry-lookahead logic
 Carry-lookahead adder
 4 four-bit adders with internal carry lookahead
 second level carry lookahead unit extends lookahead to 16 bits
4
4
A[15-12]B[15-12]
C12
4-bit Adder
P
G
4
S[15-12]
@8
@2
P3
C16 C4
@4
4
4
@3
G3
A[11-8] B[11-8]
C8
4-bit Adder
P
G
4
S[11-8]
@8
@2
@5
C3
P2
4
4
@3
G2
A[7-4]
B[7-4]
C4
4-bit Adder
P
G
4
S[7-4]
@7
@5
C2
@2
P1
4
4
A[3-0]
B[3-0]
C0
4-bit Adder
@0
P
G
4
S[3-0]
@4
@4
@3
G1
C1
@2
P0
@3
G0
C0
Lookahead Carry Unit
P3-0 G3-0
@3 @5
CSE 370 – Winter 2002 - Hardware Description Languages - 4
C0
@0
Carry-select adder
 Redundant hardware to make carry calculation go faster
 compute two high-order sums in parallel while waiting for carry-in
 one assuming carry-in is 0 and another assuming carry-in is 1
 select correct result once carry-in is finally computed
five
2:1 mux
C8
4-bit adder
[7:4]
1
C8
4-bit adder
[7:4]
0
1 0 1 0
C8
S7
10
S6
1 0 1 0
S5
S4
adder
high
adder
low
C4
C0
4-Bit Adder
[3:0]
S3
S2
S1
CSE 370 – Winter 2002 - Hardware Description Languages - 5
S0
Arithmetic Logic Unit
 Inputs: n-bit words
 A = An-1An-2… A0;
B = Bn-1Bn-2… B0; Carry-in C0
 Output: n+1-bit word + some signals (overflow, zero, etc.)
 F = FnFn-1…F0 where Fn is in fact carry-out
 Control inputs. For example:
 M = 0 “logic” (i.e., bit wise) operations
 M = 1 “arithmetic” (with carry) operations
 Other control bits Sm,Sm-1,…,S0 for selecting particular “opcodes”
CSE 370 – Winter 2002 - Hardware Description Languages - 6
ALU specification (1-bit slice)
M = 0, logical bitwise operations
S1 S0
Function
0 0
Fi = Ai
0 1
Fi = not Ai
1 0
Fi = Ai xor Bi
1 1
Fi = Ai xnor Bi
Comment
input Ai transferred to output
complement of Ai transferred to output
compute XOR of Ai, Bi
compute XNOR of Ai, Bi
M = 1, C0
0
0
1
1
= 0, arithmetic operations
0
F=A
1
F = not A
0
F = A plus B
1
F = (not A) plus B
input A passed to output
complement of A passed to output
sum of A and B
sum of B and complement of A
M = 1, C0
0
0
1
1
= 1, arithmetic operations
0
F = A plus 1
1
F = (not A) plus 1
0
F = A plus B plus 1
1
F = (not A) plus B plus 1
increment A
twos complement of A
increment sum of A and B
B minus A
logical and arithmetic operations
not all operations appear useful, but "fall out" of internal logic
CSE 370 – Winter 2002 - Hardware Description Languages - 7
Arithmetic logic unit design (cont’d)
 Sample ALU – truth table
M
0
1
1
S1
0
S0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Ci
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
Ai
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
0
1
1
0
0
1
1
Bi
X
X
X
X
0
1
0
1
0
1
0
1
X
X
X
X
0
1
0
1
0
1
0
1
X
X
X
X
0
1
0
1
0
1
0
1
Fi
0
1
1
0
0
1
1
0
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
1
0
0
1
1
0
0
1
0
1
1
0
CSE 370 – Winter 2002 - Hardware Description Languages - 8
Ci+1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
1
0
1
0
0
0
1
1
0
0
1
1
1
1
1
0
1
Arithmetic logic unit design (cont’d)
 Sample ALU – multi-level discrete gate logic implementation (via a CAD tool)
\S1
\Bi
[35]
M
S1
Bi
[33]
S0
Ai
[30]
Ci
[33]
Co
[30]
[33]
M
Ci
[30]
M
Ci
\Co
Ci
[30]
[33]
\Co
[30]
[35]
\Co
\[30]
\[35]
12 gates
CSE 370 – Winter 2002 - Hardware Description Languages - 9
Fi
Arithmetic logic unit design (cont’d)
 Sample ALU – clever multi-level implementation (see Katz for details)
S1
Bi
S0
Ai
X1
A1
A2
X2
A3
first-level gates
use S0 to complement Ai
S0 = 0
causes gate X1 to pass Ai
S0 = 1
causes gate X1 to pass Ai'
use S1 to block Bi
S1 = 0
causes gate A1 to make Bi go forward as 0
(don't want Bi for operations with just A)
S1 = 1
causes gate A1 to pass Bi
use M to block Ci
M=0
causes gate A2 to make Ci go forward as 0
(don't want Ci for logical operations)
M=1
causes gate A2 to pass Ci
other gates
for M=0 (logical operations, Ci is ignored)
Fi = S1 Bi xor (S0 xor Ai)
= S1'S0' ( Ai ) + S1'S0 ( Ai' ) +
S1 S0' ( Ai Bi' + Ai' Bi ) + S1 S0 ( Ai' Bi' + Ai Bi )
for M=1 (arithmetic operations)
Fi = S1 Bi xor ( ( S0 xor Ai ) xor Ci ) =
Ci+1 = Ci (S0 xor Ai) + S1 Bi ( (S0 xor Ai) xor Ci ) =
A4
X3
O1
Ci
M
just a full adder with inputs S0 xor Ai, S1 Bi, and Ci
Ci+1
Fi
CSE 370 – Winter 2002 - Hardware Description Languages 10
Summary for examples of combinational logic
 Combinational logic design process
 formalize problem: encodings, truth-table, equations
 choose implementation technology (ROM, PAL, PLA, discrete gates)
 implement by following the design procedure for that technology
 Binary number representation
 positive numbers the same
 difference is in how negative numbers are represented
 2s complement easiest to handle: one representation for zero, slightly
complicated complementation, simple addition
 Circuits for binary addition
 basic half-adder and full-adder
 carry lookahead logic
 carry-select
 ALU Design
 specification, implementation
CSE 370 – Winter 2002 - Hardware Description Languages 11
Hardware description languages (HDL)
 Describe hardware at varying levels of abstraction (HDLs are HLLs)
 chip densities increase hence design complexity increases
 Structural description
 textual replacement for schematic (because of increase in complexity)
 hierarchical composition of modules from primitives
 Behavioral/functional description
 describe what module does, not how
 synthesis generates circuit for module
 Simulation semantics
CSE 370 – Winter 2002 - Hardware Description Languages 12
HDLs
 Abel (circa 1983) - developed by Data-I/O
 targeted to programmable logic devices (PLAs, PALs etc.)
 not good for much more than state machines
 ISP (circa 1977) - research project at CMU
 simulation, but no synthesis
 Verilog (circa 1985) - developed by Gateway (now part of Cadence)
 similar to Pascal and C
 delays is only interaction with simulator
 fairly efficient and easy to write
 IEEE standard
 VHDL (circa 1987) - DoD sponsored standard
 “V” is for “VHSIC” (very high speed integrated circuit)
 similar to Ada (emphasis on re-use and maintainability)
 simulation semantics visible
 very general but verbose
 IEEE standard
CSE 370 – Winter 2002 - Hardware Description Languages 13
Verilog
 Supports structural and behavioral descriptions
 Structural
 explicit structure of the circuit
 e.g., each logic gate instantiated and connected to others
 Behavioral
 program describes input/output behavior of circuit
 many structural implementations could have same behavior
 e.g., different implementation of one Boolean function
 We’ll only be using behavioral Verilog
 rely on schematic for structural constructs
CSE 370 – Winter 2002 - Hardware Description Languages 14
Verilog capabilities (overview)
 Hierarchical design using instantation of modules
 A module, like a procedure in a C-like language, has a name, input/output
ports, and a body
 A module is not called like a procedure. It is instantiated.
 Inputs are monitored. Upon change, the output is changed.
 Can be done continuously, or under some conditions
 Output can be instantaneous, or after some delay
 The module stays around for the lifetime of the program
CSE 370 – Winter 2002 - Hardware Description Languages 15
Structural model
module xor_gate (out, a, b);
input
a, b;
output
out;
wire
abar, bbar, t1, t2;
inverter
inverter
and_gate
and_gate
or_gate
invA (abar, a);
invB (bbar, b);
and1 (t1, a, bbar);
and2 (t2, b, abar);
or1 (out, t1, t2);
endmodule
CSE 370 – Winter 2002 - Hardware Description Languages 16
Simple behavioral model
 Continuous assignment; Input continuously monitored; Can be used for
combinational circuits
Required key word
Name
module and_gate
input
output
reg
Port list
(out, in1, in2);
in1, in2;
out;
out;
assign #2 out = in1 & in2;
endmodule
delay from input change
to output change
CSE 370 – Winter 2002 - Hardware Description Languages 17
Simple behavioral model
 always block; “infinite-loop”-like assignment; output changes every time
input changes
module and_gate
input
output
reg
(out, in1, in2);
in1, in2;
out;
out;
simulation register keeps track of
value of signal
always @(in1 or in2) begin
#2 out = in1 & in2;
end
endmodule
specifies when block is executed
ie. triggered by which signals
CSE 370 – Winter 2002 - Hardware Description Languages 18
Module Hierarchy (Basic idea)
 Connect modules together to form larger modules
 Example:
 Build an AND gate by 2 NAND gates in series
module NAND2 (in1, in2, out);
module AND2(in1,in2,out);
input in1, in2;
input in1,in2;
output out;
output out;
assign out = ~(in1 & in2);
wire w1; // to connect the 2 NAND's
endmodule
NAND2 nand1(in1,in2,w1);
NAND2 nand2(w1,w1,out);
endmodule
CSE 370 – Winter 2002 - Hardware Description Languages 19
Driving a simulation
module stimulus (a, b);
output
a, b;
reg [1:0]
cnt;
2-bit vector
initial block executed
initial begin
only once at start
cnt = 0;
of simulation (in contrast
repeat (4) begin
with “always”)
#10 cnt = cnt + 1;
$display ("@ time=%d, a=%b, b=%b, cnt=%b",
$time, a, b, cnt); end
print to a console
#10 $finish;
end
assign a = cnt[1];
assign b = cnt[0];
endmodule
directive to stop
simulation
CSE 370 – Winter 2002 - Hardware Description Languages 20
Complete Simulation
 Instantiate stimulus component and device to test in a schematic
CSE 370 – Winter 2002 - Hardware Description Languages 21
Comparator Example
module Compare1 (A, B, Equal, Alarger, Blarger);
input
A, B;
output
Equal, Alarger, Blarger;
assign #5 Equal = (A & B) | (~A & ~B);
assign #3 Alarger = (A & ~B);
assign #3 Blarger = (~A & B);
endmodule
CSE 370 – Winter 2002 - Hardware Description Languages 22
More Complex Behavioral Model
module life
input
output
reg
reg [7:0]
reg [3:0]
reg [3:0]
(n0, n1, n2, n3, n4, n5, n6, n7, self, out);
n0, n1, n2, n3, n4, n5, n6, n7, self;
out;
out;
neighbors;
count;
i;
assign neighbors = {n7, n6, n5, n4, n3, n2, n1, n0};
always @(neighbors or self) begin
count = 0;
for (i = 0; i < 8; i = i+1) count = count + neighbors[i];
out = (count == 3);
out = out | ((self == 1) & (count == 2));
end
endmodule
CSE 370 – Winter 2002 - Hardware Description Languages 23
Hardware Description Languages vs.
Programming Languages
 Program structure
 instantiation of multiple components of the same type
 specify interconnections between modules via schematic
 hierarchy of modules (only leaves can be HDL in DesignWorks)
 Assignment
 continuous assignment (logic always computes)
 propagation delay (computation takes time)
 timing of signals is important (when does computation have its effect)
 Data structures
 size explicitly spelled out - no dynamic structures
 no pointers
 Parallelism
 hardware is naturally parallel (must support multiple threads)
 assignments can occur in parallel (not just sequentially)
CSE 370 – Winter 2002 - Hardware Description Languages 24
Hardware Description Languages and
Combinational Logic
 Modules - specification of inputs, outputs, bidirectional, and internal signals
 Continuous assignment - a gate's output is a function of its inputs at all
times (doesn't need to wait to be "called")
 Propagation delay- concept of time and delay in input affecting gate output
 Composition - connecting modules together with wires
 Hierarchy - modules encapsulate functional blocks
 Specification of don't care conditions
CSE 370 – Winter 2002 - Hardware Description Languages 25