ABCN Pad ring
V8.0
Final ABC130 pads distribution
30/04/13
F. Anghinolfi/K. Swientek
1
ABC130 – Pad ring and Fiducials
3146.16 um
1
2
6.8mm x 7.9mm (x,y)
y
7602.18 um
x
4 off fiducials added
Fiducials are 95µm x 95µm
(Ball bond pad)
4
3
F. Anghinolfi/K. Swientek
3150 um
30/04/13
200
200
200
250
200
250
250
padDisable_RegA
padDisable_RegD
padShuntCtrl
PIO_INP_RAW_PULLD
OWN
DGNFETProt
GNDD
LONERTHREE_padP
LONERTHREE_padN
GNDD
COM_LZERO_PadP
COM_LZERO_PadN
GNDD
CLK_PadP
CLK_PadN
GNDD
BC_padP
PIO_INP_RAW_PULLD
OWN
SIOGND
PIO_REC160
SIOGND
PIO_REC160
SIOGND
PIO_REC160
SIOGND
PIO_REC160
To FE
200
250
250
200
250
250
200
BC_padN
ABC130 “BOTTOM SIDE”
To BE
Chip edge
40x40 um MA
423.03
3387.82
530.82 um
3
ABC130 “RIGHT SIDE” (but represented horizontal to
match the paper or.)
Chip edge
Follow up on next slide --
14+377 = 391 um
30/04/13
PIO_INP
PIO_INP
111
PIO_INP
PIO_INP
111
111
4
PIO_INP
PIO_INP_PD
1 2 3
padID (5)
111
padTerm
0
111
111
111
200
PIO_REC160
FastCLK_PadP
FastCLK_PadN
GNDD
SIOGND
111
111
200
PIO_TRCVR160
DataL
DataLB
DVSS
SIODVSS
111
200
PIO_TRCVR160
XoffL
XoffLB
To “Bottom” side
Abut left pad of next slide
1710 um
F. Anghinolfi/K. Swientek
4
ABC130 “RIGHT SIDE” (but represented horizontal to
match the paper or.)
Follow up on next slide --
Special Unit
DVSSBR
DVSS
SIODVSS
VDDD
SIODVDD
DVDD
SIOVDD
GNDD
SIOGND
111
VDDD
SIODVDD
DVDD
SIOVDD
111
111
SIOGND
GNDD
Digital Power/Ground (6 pads) Left Group
Distance from last supply here, DVSS to DVSSA
in the next slide is 162 um
Abut left pad of next slide
7*111 = 777 um
30/04/13
F. Anghinolfi/K. Swientek
5
ABC130 “RIGHT SIDE” (but represented horizontal to
match the paper or.)
Follow up on next slide --
DVSSA
GNDIT
VDDA
GNDA
AVDD
GNDIT
VDDA
GNDA
AVDD
GNDIT
VDDA
GNDA
AVDD
GNDIT
VDDA
GNDA
AVDD
DVSSA
SIOGND
SIOVDD
SIOGND
SIODVDD
SIOGND
SIOVDD
SIOGND
SIODVDD
SIOGND
SIOVDD
SIOGND
SIODVDD
SIOGND
SIOVDD
SIOGND
SIODVDD
SIODVSS
Abut left pad of next slide
111
111
162
SIODVSS
Analog Power/Ground (16 pads)
17*111+162 = 2049
30/04/13
F. Anghinolfi/K. Swientek
6
30/04/13
8*111+126= 1014 um
F. Anghinolfi/K. Swientek
1577 um
200
111
111
200
111
111
200
111
111
DVDD
GNDD
VDDD
DVDD
GNDD
VDDD
DVDD
SIODVDD
SIOGND
SIOVDD
SIODVDD
SIOGND
SIOVDD
SIODVDD
PIO_TRCVR160
SIOGND
PIO_TRCVR160
SIODVSS
PIO_DRV160
SIODVSS
PIO_DRV160
VDDD
SIOVDD
XOFFRB
XOFFR
GNDD
DATRB
DATR
DVSS
DataoutFC2_PadP
DataoutFC2_PadN
DVSS
DataoutFC1_PadP
DataoutFC1_PadN
GNDD
SIOGND
Digital Power/Ground (9 pads) Right group
200
111
111
111
126
ABC130 “RIGHT SIDE”
(but represented horizontal to match the paper or.)
Chip edge
To “Top” side
368+14
=382 um
7
423.03
1233.82
30/04/13
F. Anghinolfi/K. Swientek
319
111
306
111
ANA
ANA
PIO_ANA
SIOVDD
SIOGND
PIO_INP_PD
SIOGND
PIO_INP_PD
SIOGND
SIOBPU08_B_o
utput
SIOGND
PIO_INP_PD
AMUXOUT
TESTRES
TESTCOM
VDDD
GNDD
GNDD
ScanEnable
Scan_in_CLK
GNDD
Scan_out_CLK
GNDD
Scan_in_BC
GNDD
Scan_out_BC
SIOBPU08_B_o
utput
SIOGND
VDDD
SIODVDD
PIO_INP_PD
GNDD
abcup_pad
RSTB_pad
PIO_INP
SIOGND
VDDD
SIOVDD
Chip edge
111
228.14
3387.82
111
111
111
111
111
111
111
111
111
111
111
111
GNDD
SIOGND
40x40 um MA
111
ABC130 “TOP SIDE”
Analogue Pads
Attached to the
Analogue FE block
Power rails break
2290
8
ABC130 – Placement on reticle
ABC130
6.8mm x 7.9mm (x,y)
20.4
TDCpix
6.8
2.8
ABC130
0.2 (arbitrary)
1.8
7.9
20.4
<=21
12.03
7.9
6.8
0.2 (arbitrary)
<=20
6.665
TDCpix_demo
19.03
20130412
2 ABC130 per reticle, 60 “good” reticles
per wafer
ABC130 – Pads list
//top edge signals
RSTB_pad
N.C.
Scan_Enable
SDI_CLK
SDO_CLK
SDI_BC
SDO_BC
padTESTCOM
TESTRES
AMUXOUT
//Power pads
4x GNDIT
4x GNDA
4x AVDD
4x VDDA
DVSSA
5x GNDD
5x DVDD
5x VDDD
DVSS
40
Static
MHz
MHz
MHz
MHz
Analogue
Analogue
Analogue
I
I
I
I
O
I
O
O
I
O
CMOS Pull-up
CMOS Pull-Down
CMOS Pull-Down
CMOS Pull-Down
CMOS 8mA
CMOS Pull-Down
CMOS 8mA
Analogue
Analogue
Analogue
Power
Power
Power
Power
Analogue Ground
0V Analogue Ground to FE branch
Analogue Ground
0V Analogue Ground
Ext. Analogue Power Ext. Power for Analogue
Reg. Analogue PowerRegulated Power for Analogue
ESD Return
0V Ground specific to ESD return
Digital Ground
0V Digital Ground
Ext. Digital Power
Ext. Power for Digital
Reg. Digital Power Regulated Power for Digital
ESD Return
0V Ground specific to ESD return
6.8mm x 7.9mm (x,y)
Power
Power
Power
Power
External Hard Reset signal
Reserved
Enable Scan Path chains
Input for CLK Scan Path chain
Output of CLK Scan Path chain
Input for BC Scan Path chain
Output of BC Scan Path chain
Discriminator bias "spy" point
Reference resistance
Analogue "spy" output
1
0
0
0
X
0
X
X
R
X
0V
0V
1.5V
1.2V
0V
0V
1.5V
1.2V
0V
Ashley’s Old
rather old
4 slides
30/04/13
F. Anghinolfi/K. Swientek
11
ABC130 Bottom Edge – Left Side
VSS (spare) pad omitted - but assume
this GND serves the function?
GND Pad
6mm x 7.9mm (x,y)
BC
FE_GND
RLCK
L0_COM
R3_L1
A: REG_A
B: REG_D
C: ShuntCtrl
A
B
C
y
Gnd pad, placed 250µm from
LVDS pads (between centres)
Pads placed on 125µm pitch
x
LVDS Rx placed on
200µm pitch
250µm
250µm
200µm
200µm
250µm
250µm
700µm
Unless indicated ALL bond pads are 95µm x 190µm
3650µm
450µm
200µm
ABC130 Bottom Edge – Bottom left corner
Remaining Pad assignment as prescribed by Francis
6mm x 7.9mm (x,y)
Pads step and repeat at 125µm pitch
Chip IDx
125µm
Chip IDx
125µm
TERM
150µm
200µm
FC_CLK
y
125µm
125µm
x
200µm
DataL
125µm
125µm
XoffL
200µm
300µm
Fiducial 3
ABC130 Bottom Edge – Top right corner
Fiducial 2
275µm
6mm x 7.9mm (x,y)
XoffR
200µm
125µm
125µm
DataR
200µm
125µm
125µm
y
FC2
200µm
125µm
125µm
x
FC1
G
P
G
P
Remaining PAD assignment as prescribed by Francis
200µm
150µm
125µm
125µm
125µm
Pads step and repeat at 125µm pitch
ABC130 – Fiducial Detail
3875µm
1
120µm
2
6mm x 7.9mm (x,y)
y
7660µm
x
4 off fiducials added
Fiducials are 95µm x 95µm
(Ball bond pad)
4
3
120µm