University of Portland
School of Engineering
5000 N. Willamette Blvd.
Portland, OR 97203-5798
Phone 503 943 7314
Fax 503 943 7316
Final Report
Project Lamprey: A CMOS Traffic
Light and Intersection Control Circuit
Contributors:
Khalfan Al-Mehairi
Tram Nguyen
Michael Rybel
Carldez Thomas
Approvals
Name
√
Dr. Lillevik
Date
4/23/04
Insert checkmark (√) next to name when approved.
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Revision History
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Rev.
Date.
0.9
4/14/04 .
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4/18/04
4/23/04
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Author
K. Al-Mehairi
T. Nguyen
M. Rybel
C. Thomas
M. Rybel
M.Rybel
Reason for Changes
Initial Draft
Implemented Advisors Changes
No Changes from 0.95
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Acknowledgements
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. would like to thank our advisors Sigurd Lillevik, Ph.D. and Zia Yamayee,
Project Lamprey
. advising us on our project. We would like to thank Mr. Mike Uhl of the Intel
Ph.D., P.E. for
Corporation for
. his continued support of our project. Also, we would like to thank Peter M.
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Osterberg, Ph.D. for his support of the MOSIS program and Wayne Lu, Ph.D. for his
technical support. Most of all, though, we are grateful to our families for their continued
support and belief in our abilities.
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Table of Contents
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Summary.......................................................................................................................
1
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Introduction ..................................................................................................................
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Background .................................................................................................................. 3
Methodology ................................................................................................................ 4
State Machine Design .............................................................................................................................4
Schematics Capture................................................................................................................................4
Place and Route File ...............................................................................................................................5
CPLD Macro Model.................................................................................................................................5
Three-Dimensional Intersection Model ..................................................................................................5
Results .......................................................................................................................... 6
Technical..................................................................................................................................................6
Block Diagram ..................................................................................................................................6
L1 and L2 Sensors ....................................................................................................................7
Pedestrian Sensors...................................................................................................................7
MOSIS Chip ..............................................................................................................................7
Traffic Lights ..............................................................................................................................7
Pedestrian Lights ......................................................................................................................7
State Machine ..................................................................................................................................7
Output Traces...................................................................................................................................8
Default Pattern ....................................................................................................................... 10
Pedestrian Pattern ................................................................................................................. 11
L1 or L2 Pattern...................................................................................................................... 12
L1 and L2 Pattern................................................................................................................... 13
Three-Dimensional Physical Model ............................................................................................. 14
Process ................................................................................................................................................. 15
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Original Schedule .......................................................................................................................... 15
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Schedule Overview ....................................................................................................................... 15
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Critical Path ...................................................................................................................................
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Assumptions .................................................................................................................................. 16
Milestones...................................................................................................................................... 17
Risks .............................................................................................................................................. 18
Resource Requirements ............................................................................................................... 18
Contingency Plan .......................................................................................................................... 19
CCB Request ................................................................................................................................ 19
Conclusions ...............................................................................................................20
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List of Figures.
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. block diagram..................................................................................................6
Figure 3. Traffic light system
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Figure 5. Controller state diagram.
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Figure 8. Output trace for the default pattern. ............................................................................................ 10
Figure 9. Output trace for the pedestrian pattern....................................................................................... 11
Figure 10. Output trace for the left turn pattern.......................................................................................... 12
Figure 11. Output trace for both the L1 and L2 patterns. .......................................................................... 13
Figure 12. Traffic intersection 3D physical model. ..................................................................................... 14
Figure 13. Project Lamprey schedule. ....................................................................................................... 15
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List of Tables .
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Table 1. Signal names and. functionality. ......................................................................................................9
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Table 2. Project Lamprey milestone
table.................................................................................................. 17
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Table 3. Project Lamprey risk analysis....................................................................................................... 18
Table 4. Project Lamprey budget. .............................................................................................................. 18
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Summary
This document is the final report which summarizes our senior design project. This report
outlines the entire process that has been applied to accomplish Project Lamprey. Project
Lamprey is a CMOS Traffic Light and Intersection Control Circuit, which is implemented on
a MOSIS (Metal Oxide Semiconductor Information Systems) chip.
The specific type of intersection that project Lamprey implements is as follows: A street
running North to South has through traffic lanes and two left turn lanes one for the
Northbound street and one for the Southbound street. Bisecting this “busy street” from
East to West is a less traveled street which only implements through traffic lanes.
This report begins with a background section that provides the reader with a basic working
knowledge of the history of traffic lights. The first traffic lights were mechanical devices
implemented on the tramways of England. The first electric traffic lights were installed in
Cleveland, Ohio in 1914. Today traffic lights are used in every major city in the USA.
Project Lamprey was implemented by sequential logic because it was determined that the
hardware portion would need to have a memory of past events such as which lights have
been green, which lights have been yellow, etc. Once the type of logic was determined, a
sequential logic state machine was designed to meet the functional requirements of the
intersection that project Lamprey set out.
The result of this sequential logic design is a Finite State Machine (FSM) that contains
sixteen states. These sixteen states control a complicated traffic pattern on the
intersection. Each state controls the specific traffic lights for the through traffic and left turn
lanes on the north to south street as well as the through traffic signals on the east to west
street.
Once the state machine was designed, it could be taken to a schematic capture program
and literally built inside the software where it could be thoroughly tested and its
functionality verified. After schematic capture, a place and route file was created to send
to the silicon fabrication plant to implement our design on and integrated circuit.
While the fabrication was taking place, a macro model using the Verilog hardware
description language and a complex programmable logic device was designed and built to
implement the same design as the silicon integrated circuit. This was a piece of hardware
that could be tested while the silicon integrated circuit was being fabricated.
In addition to the electronic portion of this project, a 3-dimensional model was built to
display the results of project Lamprey in a meaningful way. Light emitting diodes were
used as the traffic lights and a miniature intersection was set up to observe the way that
the final hardware behaved.
The project was a success and all of milestones set about in the project plan were met
without difficulty. It should be noted that all of the aspects of project Lamprey that were
done in software are available at the following website.
http://lewis.up.edu/egr/srdesign04/lamprey/
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Introduction
The purpose of the Final Report is to outline and explain the CMOS Traffic Light and
Intersection Control Circuit. This document contains useful information for the people who
want to understand project Lamprey for implementation purposes or to improve the control
of the traffic light and intersecting circuit.
It presents background information, which can be useful to build fundamental concepts of
the project. Not only will this report help the reader to understand the sequence that has
been followed, but also it provides hints and guidelines to build the project through a
technical discussion in the methodology chapter. The Results chapter in this report is the
crucial part, which contains two important sections. Those two sections review the major
components of the design process. The Technical section educates the reader about the
architecture and the implementation of project Lamprey’s design. Furthermore, the
Process section describes the difference between the original plan and the actual plan that
had been followed to complete the project effectively. Finally, the last chapter of this
document is the Conclusions, which explain the key-points of the final report, and provides
any further suggestions that can expand the project in the future.
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Background
In 1868, the first known traffic light was installed for pedestrians who had to walk across
main streets or along tramways in England. This traffic signal was a gas lamp, consisting
of two glasses: a red glass and a green glass. When it was safe for the pedestrians to
walk across the tramway, a mechanical arm would raise the green glass over the gas
lamp, which would make the light from the lamp appear green. Conversely, when it wasn’t
safe to cross the red glass would be raised. It was invented by the signal engineer of the
English railway J.P. Knight and was placed in front of the House of Commons. However,
only one was ever installed because it exploded only a few months later and killed the
attendant officer.
Electric traffic lights were installed for the first time in 1914 by the American Traffic Signal
Company under the direction of Safety Director Alfred A. Benesch in Cleveland, Ohio at
Euclid Ave. and 105th Street. It had two long cross arms, red and green lights, and
buzzers. Two long buzzes signaled Euclid Avenue traffic to proceed, one long buzz meant
it was 105th Street's turn to proceed.
Today, traffic lights are present in every major city in the United States. We count on
traffic signals to safely and efficiently move traffic through busy intersections. Nowadays,
we take these devices for granted, but without them we would need to hire full time traffic
directors and traffic accidents would be far greater then they are today.
The design of a traffic light and intersection controller is an interesting, not to mention
challenging, undertaking. Most modern traffic lights are designed using digital systems
implementations that have multiple redundant features. Also, modern traffic intersections
are tied together in order to predict and maintain even traffic flow. However, these issues
will not be addressed in this project.
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Methodology
The following section describes the methodology used by project lamprey to produce the
traffic light and intersection control circuit.
State Machine Design
The first step in any digital design process is to determine what kind of logic you will be
using. There are basically two types that are available, combinational and sequential. A
combinational logic circuit’s outputs only depend on the current inputs to the circuit.
Sequential logic on the other hand has a memory of past events, its output depends on
the present input and possible previous inputs as well. To put it simply, sequential logic
has a memory of past events.
Project lamprey must have memory of what lights have been green what lights have been
yellow and so on. It is then simple to design this controller around sequential logic; more
specifically, a finite state machine. A state machine follows a sequence of events based
on certain conditions. In project Lamprey’s case, there is one state where certain lights on
the intersection are red and then the next state turns the lights to green, while on the
adjacent street the lights turn from green to yellow to red. Each of these light changes are
controlled by a state in the state machine.
In order to design our state machine, it was first necessary to construct a state table.
However, the problem was that a state machine of this complexity is not easily designed
by hand, so computer aided design is needed in order to produce the state machine. The
most that could be done by hand is develop a state diagram.
Once a state diagram was finalized, we then used computer aided design to produce the
equations that tell the state machine how it is to move from one state to the next (state
equations). In this particular case, the Hardware description language of ABEL was used
to produce the state equations, which could then be taken to the next step. It should be
noted to the reader that the ABEL program is not included here, however a software copy
is available on the project Lamprey website
Schematics Capture
Using the state equations that are generated by ABEL, a schematic layout of the controller
was created on a schematics capture program called B2Logic. Once the schematics were
generated, test vectors were sent into the schematics and outputs monitored in order to
test the controller. Exhaustive testing was employed to ensure a wide range of scenarios
were covered. This type of testing ensures that the state machine reacted as expected
and function correctly. The B2Logic software gives the ability to test a design and reacts
as the actual hardware when the controller is implemented in silicon. A copy of the
B2Logic schematics that were created for project Lamprey are available on the Lamprey
website.
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Place and Route File
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When the schematics
all of test vectors that were run in the schematics capture
.place andpassed
software, a .
route file was generated manually. This process was time
consuming and very difficult, so it was important to make sure the schematics were
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working flawlessly. Once this is ensured, the process of creating a place and route file
was started.
First, each gate on the schematics was given a name and then its inputs and outputs were
given names as well. These names usually correspond to what the gate was named. For
instance, if a gate was named U1 and it had two outputs and one input, then they were
simply named U1_P1, U1_P2, U1_P3. Following a logical nomenclature system like this
made the place and route file easier to check when it was finished.
Once all of the gates in the schematic were labeled, the place and route file was started,
usually in a simple text editor. The gates were called using the library that the IC foundry
provides; in this case, the MOSIS foundry was used. Below is a sample from the place
and route file that was generated for project Lamprey. Also, the place and route file
appears on the Lamprey website.
Once the place and route file was written, it was checked. Here, the person who wrote the
file inserted a number of known errors into the file. Then, the person who wrote the file
gave it to someone else and that person checked it. If that person finds the same errors
that were inserted into the file, then it was assumed that the file is accurate. The place
and route file was then sent to the IC foundry for fabrication.
CPLD Macro Model
While the IC was fabricated (it took about a month and a half), a macro model was built.
This model was implemented using discrete logic in the 7400 series logic family. This
family of logic includes basic logic gates and a few MSI functions such as multiplexers and
encoders. However, project lamprey decided to blaze a trail by implementing the macro
model on one chip just like the final product would be on one silicon fabricated chip. This
was done by HDL (Hardware Description Language) rapid prototyping. The HDL of
choice was Verilog because it is a simple language to use and is very powerful as well. A
Verilog program was written to simulate, in software, the Lamprey controller. When it was
finished being tested, it was downloaded to a CPLD (Complex Programmable Logic
Device). While the other chip was being fabricated, the CPLD was used to debug the
design and work out any errors. Having done this, the team can then simply do a chip for
chip swap when the silicon fabrication of the other chip is finished.
Three-Dimensional Intersection Model
When the hardware design was finished, it was necessary to build a physical intersection
out of plywood and art materials so that the outputs of the circuits can be displayed in a
meaningful manner. This was done by creating a miniature of the intersection and using
LED’s to create the traffic lights. This made the project more interesting to look at and also
served to show how the project could be implemented in the real world.
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Results
The purpose of this chapter is to explain and discuss the results of the project. There are
two parts in this chapter: technical and process. In the technical sub-section, we will
explain each individual component of this design and how the design works based on the
top-level block diagram. The process sub-section will compare our project plan to the
actual activities.
Technical
Block Diagram
Figure 1 shows the block diagram that Project Lamprey implements.
Figure 1. Traffic light system block diagram.
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L1 and L2 Sensors
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These sensors were implemented by push buttons, which generate an active high signal
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when depressed by the user. It indicates there is/are car(s) on the left-turn lanes of the
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intersection.
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Pedestrian Sensors
Similar with the above L1 and L2 sensor, pedestrian sensors were also push buttons. It
generates an active high logic signal when pedestrian depress the button to across the
intersection to the other side of the street.
MOSIS Chip
This receives the active high signals from the push buttons and generates the correct
output signals, which are fed to the traffic lights. The MOSIS Chip includes 3 internal RS
latches and 3 different internal counters, named C1, C2, and C3. The latches hold the
signals from the push buttons until the state machine reaches the predefine state for that
input. All of the counters contain an input called EN, which enables the counter whenever
it enters its predefine state. Counter C1 is a 0-to-8 counter, which is used to keep the
green lights of the busy streets on. Counter C2 is a 0-to-5 counter, which provides the
delay time for the green lights of the semi-busy streets. The third counter C3 is a 0-to-3
counter that is used as the delay for all of the yellow lights of the state machine. At the
end of each count, the counter generates a binary 1 that indicates to the state machine
that it is time to switch states.
Traffic Lights
The traffic lights consist of ultra bright red, yellow, and green LEDs for the coming-through
traffic and left turn lanes. Each of the LEDs is, respectively, connected to the output
signals which come from the MOSIS chip.
Pedestrian Lights
These lights are similar to the traffic lights except the LEDs are red and white. Red lights
control the walk and white light don’t walk signals that are situated on either side of a
crosswalk.
State Machine
Figure 2 shows the state diagram for project Lamprey.
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Figure 2. Controller state diagram.
The inner circle contains the default pattern, which allows traffic to flow on the northbound
and southbound lanes. After a certain amount of time, the green lights on the north/south
lanes cycle from yellow to red. The state machine then allows the eastbound and
westbound lanes to flow through the intersection. Again, after a certain amount of time,
the lights change from green to red and the process repeats.
The previous default case keeps repeating its cycle unless one of the external push
buttons gets activated. The push buttons box controls the input. The first push button is an
asynchronous reset, which serves to put the state machine into state 0, which is a known
state. The next two push buttons simulate sensors within the road that indicates that a
vehicle is in either one of the two left turn lanes. The final pushbutton is a pedestrian cross
walk button. This button is used to activate the pedestrian cross walk signal.
The next loop is the L1 loop, which allows cars to turn left on one of the left turn lanes. This
state pattern is activated if the L1 pushbutton is turned on. Also, this state pattern allows
cars that are adjacent to the L1 lane to flow through the intersection. The third loop is the
L2 loop which is same as L1 state pattern, but in the opposite direction of the intersection.
The L1 and L2 pattern is activated when both the left turn push buttons are activated. This
pattern allows cars in both left turn lanes to make left turns. The final loop is the pedestrian
pattern. If the pedestrian pushbutton is triggered, then the lights on the north and
southbound lanes, which represent the busy street, change to red and the pedestrian
lights turn to white. This process allows pedestrians to cross the busy street.
Output Traces
This section describes some of the output traces generated by the B2Logic schematic
capture and simulator tool. In order to make the output traces easier to read, a table has
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been created (Table 1) that shows the names of the signals and their function. It should be
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noted that even though the traces show the state machine being clocked at 100 ns the
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actual device is clock at 1.0 s.
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. Table 1. Signal names and functionality.
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Signal Name
RS
Signal Type
Input from pushbutton
R1, Y1, G1
Output to LEDs
R2, Y2, G2
Output to LEDs
RA, YA, GA
Output to LEDs
RB, YB, GB
Output to LEDs
RC, YC, GC
Output to LEDs
WA, SA
Output to LEDs
WC, SC
Output to LEDs
L1, L2
Input from pushbutton
P
Input from pushbutton
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Signal Function
This signal is a reset signal. When the signal
goes high it returns the state machine to State 0.
These are the red, green and yellow lights for
the L1 left turn lane.
These are the red, green and yellow lights for
the L2 left turn lane.
These are the red, green and yellow lights for
the lane A which travels from south to north.
These are the red, green and yellow lights for
the lane A which travels from north to south.
These are the red, green and yellow lights for
the lane A which travels from west to east
These are the white and red lights which control
the crosswalk signal across lanes A, L1 and B,
L2.
These are the white and red lights which control
the crosswalk signal across lane C.
These are the pushbutton inputs to the system
that represent cars waiting to turn on lane L1
and L2
This is the pushbutton input to the system that
represents a pedestrian requesting to cross a
street.
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Default Pattern
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Figure 3. Output trace for the default pattern.
The state machine’s default pattern is shown in Figure 3. At time zero, the RS input
signal is asserted causing the state machine to resist to State 0. At 100 ns, the state
machine is at State 0 were GA, GB, and WA are all asserted high. This means that the
lights controlled by output signals GA, GB, and WA will all be on.
After about 9 clock cycles, the state machine goes into State 1 were YA and YB are
asserted. This occurs between 900 and 1000 ns. These signals stay high until 4 clock
cycles have passed. At this time, the output signals R1, R2, RA, RB, RC, SA, and SC
that controls the red and don’t walk lights are asserted and the present state is State 2.
One-clock cycle later, around 1300 ns, the state machine is in State 3 and GC is
asserted. The state machine remains in this state until 6 clock cycles have passed. After
which, it goes to State 4 were YC is the only signal that is asserted.
Since YC, YA, and YB all have the same associated delay, the state machine will again
change state after 4 clock cycles have passed. At this point, the time is a little past 2100
ns and the state machine is now in State 5, which is the last state for the default pattern.
This state is the same as State 2 where all of the outputs signal that controls red lights
and don’t walk lights are asserted, meaning that these lights are on. Once another clock
cycle has passed, this system will return to State 0 and repeat this process until one of
the three inputs are asserted.
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Pedestrian .Pattern
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Figure 4. Output trace for the pedestrian pattern.
Figure 4 shows the state machine’s pedestrian pattern. As before, the Input signal RS is
asserted to start the state machine at State 0. The state machine remains there until
approximately 900 ns. After which, the state machine enter State 2.
During this time, the input signal P is asserted. Since State 2 is the state where the system
checks the value of input P to determine its next state, it sees that input P is a binary 1.
This causes the state machine to go to State F were GC and WA are both asserted,
meaning the green light of Lane C and the Pedestrian light of WA are turned on.
Since this state uses a longer delay than its counter part State 3, the state machine
remains in this state until 9 clock cycles have passed. After which, the state machine then
proceeds to State 4 and, after following the same pattern as before, returns to State 0. For
the diagram above, the state machine enters State F at approximately 1300 ns and goes
to the next state at approximately 2100 ns.
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L1 or L2 Pattern
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Figure 5. Output trace for the left turn pattern.
Figure 5 shows the state machine’s L1 pattern. Since Patterns L1 and L2 behave exactly
the same, only the pattern L1 is shown. As usual, at time 0, the input signal RS is asserted
to reset the state machine to State 0. The state machine then follows the default pattern
(Figure 3) until it reaches State 5. This occurs between 0 and 2100 ns.
Once at State 5, the state machine checks the input signal L1 and L2 to see if any or both
of them are asserted. For this example, the state machine sees that the input signal L1 is
asserted. This causes the next state to be State 6 where G1 and GB are high. Similar to
before, the state machine remains in this state until 9 clock cycles, after which the state
machine goes to State 7. This occurs at approximately 2700 ns in the diagram.
While in State 7, the output signals Y1 and GA are asserted. Once four clock cycles have
passed, at approximately 3100 ns, the state machine proceeds to State 8 where GA is the
only output asserted. The state machine stays there for 1 clock cycle and then returns to
State 0 and the default pattern.
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L1 and L2 Pattern
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Figure 6. Output trace for both the L1 and L2 patterns.
The final pattern of the state machine is the L1 and L2 pattern shown in Figure 6. Once
again, at time zero, the RS input signal is asserted to start the state machine at State 0. It
then follows the same sequence as the default pattern (Figure 3) until it reaches State 5,
which is at approximately 2100 ns.
Once again, at State 5, the state machine checks the L1 and L2 inputs to see if any one of
them is asserted. For this case, both L1 and L2 are high. This means that upon the next
clock cycle the state machine will enter State C. At State C, both G1 and G2 are asserted.
After 9 clock cycles, about 2750 ns, the state machine will go to State D were both Y1 and
Y2 are asserted. It remains there until 4 clock cycles pass at which time it proceeds to
State E were all of the output signals to the red and don’t walk lights are asserted. The
state machine remains at State E for 1 clock cycle and then return to State 0 and the
default pattern.
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Three-Dimensional Physical
Model
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Figure 7. Traffic intersection 3D physical model.
Figure 7 shows a photo of the finished physical model for project Lamprey. It uses LEDs
to implement the traffic lights and model railroad scenery in order to convey a sense of
realism to the project.
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Process
Original Schedule
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Figure 7 below shows the original schedule of our project from start to finish.
Figure 8. Project Lamprey schedule.
Schedule Overview
Project Lamprey schedule required forty-nine tasks starting from August 26th, 2003 and
ending on April 21st, 2004, which covers fall and spring semesters. The schedule has
been designed to optimize, manage and organize Project Lamprey. It contains different
numbers of tasks and milestones, which will monitor designing, building and testing the
procedures of the project. Also, the Project Lamprey schedule has short and long tasks
depending on the time that necessary to be completed. The shortest tasks are the type
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that need only one day to complete, such as, “Approval Meetings”, “Monthly Program
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Reviews”, and “Check Ordering Parts Statue”. On the other hand, the schedule has fewer
. have been broken down to subtasks for more efficient achievements.
long tasks, which
For example,.“Build Lamprey Project Model” task will take fifty-six days to be completed,
. broken down to seven different tasks where the longest will take twelve
so it has been
days, and the. shortest will need five days to be prepared. This solid schedule has been
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set using MS Project.
Critical Path
Using MS Project, Project Lamprey schedule contains a critical path with two components.
These two components were always monitored carefully because if any type of delays
appears on them, the schedule of Project Lamprey would slip. The first critical component
is “B2 Logic Design and Test” which is located in fall semester schedule. The second
component, which is “ .tpr file Write and Test” path, is also located in the same semester
and comes after the previous task. Thus, Fall term was a critical semester for Project
Lamprey because it contained two important components. In the final analysis, the original
schedule was followed to the letter, and all milestones and tasks were completed exactly
as planned in the schedule.
Assumptions
In the beginning of our project, certain assumptions were identified as follows:

The complete design of our project can fit on the MOSIS Chip.

Making the model 3 x 3 ft will give it a great appearance while not
restricting its’ mobility.

We can get our macro model done faster by using a Xilinx CPLD
chip.

We will be able to build a realistic looking 3D model.

All of our parts will be received in a timely manner.
Although most of our assumptions went well, there were a few differences that were
noticed. First of all, our design turned out to be the biggest chip design this semester.
Therefore our design came really close to not fitting on the MOSIS chip.
We also had some difficulty with the model size. Because it was 3 x 3 ft we had problems
moving it out of the senior design lab. We ended up having to tilt it side ways to get it out.
Beside these two minor problems most of our assumptions proved true and we were able
to get things done on schedule.
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Milestones
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The planning of our milestones went very well, especially during the spring semester
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where some were finished early.
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Table 2. Project Lamprey milestone table.
Because we used a Xilinx CPLD chip for our macro model, we were able to get the macro
model (Milestone 7) done earlier than planned. The process went well for us because it
limited the amount of wire wrapping that had to be done. Also, since the functionality of the
macro model was done in the Verilog program, we were able to test it before we even
began wire wrapping.
Because we were able to get the macro model done early, we were also able to finish the
system model (Milestone 9) early as well. The only real delay we had in our milestones
table was our TOP approval meeting (Milestone 8). This delay was due mainly because of
scheduling difficulties between the group and our advisors. It did not impact the remaining
milestones.
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. the project risks and rates them as high, medium, or low.
Table 3 identifies
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Risks
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Number
Risk Factor
Description
1
Medium
tpr files is not complete in time.
2
High
MOSIS Chip doesn’t work.
3
Low
Xilinx CPLD doesn’t work
4
Medium
Not able to create a realistic model.
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The assessment of our risk factors went very well. We identified early on what our risks
were. This enabled us to focus on these risks to try to prevent any possible problems. We
also noticed that the size of our chip added another risk. Since our place and route file was
large compared to other place and route files, we had added room for error. But because
we were aware of this potential problem we were also able to prevent it.
Resource Requirements
Most of our resources went exactly as planned. Our estimation for the amount of time we
would spend on building the 3D model and the macro model were almost perfect.
However, we did go over budget and we ended up funding some of the project ourselves.
Our original budget was $205.33 (see Table 4 below). The reason we went over is
because we didn’t account for the high prices of the building and the amount it would cost
for the landscape and other parts of the model. Our total amount we went over budget
was about $24.5. This is what it cost us to purchase two of the model buildings for our
project. Everything else was covered in our budget.
Table 4. Project Lamprey budget.
Line
A
B
Category
1 Materials
Electronics
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.1
Model Materials
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2
Description
Number
Rate
Amount
Part Number
$
$
$
$
$
$
$
$
$
$
122-1175-ND
AE7338-ND
ED2023-ND
V1016-ND
K325-ND
MV8114-ND
MV8412-ND
MV8316-ND
67-1604-ND
SW404-ND
Subtotal
CPLD
CPLD Socket
CPLD Pin Grid Array
Vector Prototype Board
Wire Wrap Wire
LEDs RED
LEDs Green
LEDs Orange
LEDs White
Push Buttons
Plywood SCHOOL OF ENGINEERING
PVC PIPE
LandScape and Construction
Total
2
2
1
2
3
20
20
20
2
6
1
N/A
N/A
$
$
$
$
$
$
$
$
$
$
12.10
1.76
10.10
20.44
10.37
0.35
0.39
0.46
3.75
0.25
24.20
3.52
10.10
40.88
31.11
6.82
7.66
9.04
7.50
1.50
N/A CARLDEZ
$ 13.00
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N/A
$ 10.00
N/A
$40.00
$ 205.33
N/A
N/A
N/A
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Contingency Plan
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Since the biggest risk for our project was the MOSIS chip, most of our contingency plans
were built around the possibility that it might not work. Part of our goal was to make our
project flexible. To do this, we made sure that our MOSIS chip was designed so that you
could use internal reset latches that were connected inside of the chip or you could use
external latches. This plan was very useful and worked well for our group.
One problem that we did encounter was the fact that our internal RS latches were wired
backwards. This caused the latches to not function properly; however, because the chip
design was flexible in this regard we were able to use external latches. Because of this,
our chip still worked as planned.
Our other contingency plan was that if the chip did not work for some reason, we would
abandon it and use the xilinx CPLD instead. However, since our first contingency plan
worked we didn’t have to use this option and we were able to use our MOSIS chip as we
originally planned.
CCB Request
There was no need for any change request.
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Chapter
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Conclusions
Overall, the objectives for this project were accomplished. They include:

Design a traffic light and intersection control circuit using MOSIS
silicon fabrication.

Create a new type of macro-model so that discrete logic from the
7400 series logic would not have to be implemented. This was done
by using a CPLD macro model in order to do a chip for chip swap
when the silicon fabrication was completed.

Build a realistic physical intersection so that the output of the
integrated circuits could be conveyed in a meaningful manner. This
was also accomplished since project Lamprey created a very good
physical 3-dimensional intersection model that implemented LEDs to
act as the traffic lights.
In conclusion, this project was challenging yet it was not so difficult that solutions to those
difficulties were hard to come by. In the future, this project could be improved by
implementing pedestrian lights that flash realistically to convey that the traffic light for that
particular crosswalk will be changing to green soon. Also, making the physical model
smaller to facilitate better mobility would be something to consider. As far as the process
for project Lamprey, there wasn’t anything that could be done differently. (I’m not sure I
agree) All parts were received in a timely manner and designs and documentation were
completed on time.
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FINAL REPORT
PROJECT LAMPREY
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CONTACT: CARLDEZ THOMAS