A probabilistic approach to
clock cycle prediction
J. Dambre,
D. Stroobandt and J. Van Campenhout
TAU, December 2, 2002
"A probabilistic approach to clock cycle prediction"
Outline
• System-level interconnect prediction
• Prediction of minimal clock cycle
• New probabilistic approach
• Experimental results
• Main causes of errors
• Conclusions & future work
"A probabilistic approach to clock cycle prediction"
System-level interconnect prediction
Parameters
from
interconnect
topology
Predict
length distribution of
interconnections
in final implementation
Measured
or typical
values
Technology
and design
parameters
Real or
hypothetical
"A probabilistic approach to clock cycle prediction"
System-level interconnect prediction
Wire length distribution
Parameters
from
interconnect
topology
Probabilistic:
• wire length variability across multiple
layout runs
• assumed homogeneous: all point-topoint wires “drawn” independently from
same distribution
Not : accurate lengths of individual wires
for particular run!
"A probabilistic approach to clock cycle prediction"
Technology
and design
parameters
System-level interconnect prediction
Wire length distribution
Parameters
from
interconnect
topology
Interconnect lengths affect:
• routing requirements (cost!)
• power dissipation
• yield
• performance (clock cycle)
• etc. ...
"A probabilistic approach to clock cycle prediction"
Technology
and design
parameters
System-level interconnect prediction
Wire length distribution
Parameters
from
interconnect
topology
Assess/compare impact of, e.g.:
• new/future technological parameters
• physical design options (e.g. layout or
cell aspect ratio)
• optimization algorithms that change
circuit topology
without having to perform physical design!
"A probabilistic approach to clock cycle prediction"
Technology
and design
parameters
Outline
• System-level interconnect prediction
• Prediction of minimal clock cycle
• New probabilistic approach
• Experimental results
• Main causes of errors
• Conclusions & future work
"A probabilistic approach to clock cycle prediction"
Prediction of minimal clock cycle
Parameters
from
interconnect
topology
Wire length distribution
Distribution of
gate and wire delays
Distribution and expected value
of minimal clock cycle
"A probabilistic approach to clock cycle prediction"
Technology
and design
parameters
Previous work:
prediction of critical path delay in BACPAC
Wire length distribution
Distribution of
gate and wire delays
Distribution and expected value
of minimal clock cycle
(1)
Length of average and
global wire
Delays of average and
global “gate+wire”
addition
(max. logic depth)
Critical path delay
(1) Sylvester et al., SLIP 1999
"A probabilistic approach to clock cycle prediction"
Previous work:
prediction of critical path delay distribution
Wire length distribution
Distribution of
“gate+wire” delays
Distribution and expected value
of minimal clock cycle
(2)
Concept:
average delay  delay of
average wire
Monte Carlo sampling
(max. logic depth)
Distribution and expected
value
of critical path delay
(2) Iqbal et al., SLIP 2002
"A probabilistic approach to clock cycle prediction"
Prediction of minimal clock cycle?
Problem: minimal clock cycle relates to maximal
combinatorial delay !
Maximal logic depth does not model :
• equal logic depth, but different number of paths
• paths with less than maximal logic depth can also become
slowest
=> more important as interconnect represents ever
increasing fraction of total delay !
Need model that captures impact of parallellism
on extreme value !!
"A probabilistic approach to clock cycle prediction"
Outline
• System-level interconnect prediction
• Prediction of minimal clock cycle
• New probabilistic approach
• Experimental results
• Main causes of errors
• Conclusions & future work
"A probabilistic approach to clock cycle prediction"
Prediction of minimal clock cycle?
Distribution of gate and
wire delays
Parameters
from
interconnect
topology
Distribution and expected value
of minimal clock cycle ?
Available:
• “gate+wire” (= segment) delay
distribution
• topology of circuit graph
Assumption:
• homogeneous: all individual segment
delays “drawn” independently from
same distribution
"A probabilistic approach to clock cycle prediction"
Technology
and design
parameters
?
log(P(D))
log(P(D))
log(d)
?
log(d)
log(d)
log(P(D))
log(d)
log(P(d))
log(P(d))
Prediction of minimal clock cycle:
probabilistic principles
?
log(d)
Sum of independent variables?
convolution of distributions
(discrete or continuous)
P d1  d2     i  0 P d1  i .P d2    i 
"A probabilistic approach to clock cycle prediction"
Sum of independent variables:
P(delay = d)
path delay distribution as a function of logic depth
1.0E+00
depth 1
1.0E-01
depth 2
1.0E-02
1.0E-03
depth 4
1.0E-04
depth 6
1.0E-05
depth 8
1.0E-06
1
depth 10
10
100
1000
delay d (arbitrary units)
"A probabilistic approach to clock cycle prediction"
log(d)
log(P(d))
log(P(D))
?
log(d)
log(d)
log(d)
log(P(D))
log(d)
log(P(d))
log(P(d))
Prediction of minimal clock cycle:
probabilistic principles
Maximum of independent
variables?
use cumulative distributions
P maxd1, d2, , dm       im1P di   
"A probabilistic approach to clock cycle prediction"
Maximum of independent variables:
maximum path delay distribution for independent paths
(logic depth = 4)
P(max. delay = d)
1.0E+00
1.0E-02
1 path
1.0E-04
1.0E-06
2 paths
1.0E-08
8 paths
4 paths
1.0E-10
10 paths
6 paths
1.0E-12
1
10
100
1000
Maximal path delay d (arbitrary units)
"A probabilistic approach to clock cycle prediction"
Prediction of minimal clock cycle:
independent paths?
Segment delays might be approximately independent, but
paths in a circuit are generally not independent!
Basic concept of new approach:
uncoupling of dependencies!
Find interconnect topology with:
• same number of wire segments
• independent paths only
• approx. same clock cycle
distribution
"A probabilistic approach to clock cycle prediction"
Prediction of minimal clock cycle:
independent paths?
Definition:
wire criticality = maximal depth of any path through that
wire
depth
depth
53
depth64
Criticality
Segments
1
0
2
0
3
1
4
1
5
9
6
6
"A probabilistic approach to clock cycle prediction"
Prediction of minimal clock cycle:
independent paths?
Notion:
Sensitivity of clock cycle to individual wire delay strongest
on paths with depth = wire criticality
Approximations:
1. Ignore impact on clock
cycle through paths with
smaller depth
2. Assume that wires with
equal criticality have equal
impact on clock cycle
"A probabilistic approach to clock cycle prediction"
Prediction of minimal clock cycle:
independent path model
Equivalent topology:
• find wire criticalities (possible without enumeration of all paths !)
• for each depth i:
equivalent paths(i) = nets(crit = i) / i
Criticality
Segments
Eq. paths
1
0
0
0.33
2
0
0
0.25
3
1
0.33
1.80
4
1
0.25
1
5
9
1.8
6
6
1
"A probabilistic approach to clock cycle prediction"
Outline
• System-level interconnect prediction
• Prediction of minimal clock cycle
• New probabilistic approach
• Experimental results
• Main causes of errors
• Conclusions & future work
"A probabilistic approach to clock cycle prediction"
Prediction of minimal clock cycle
Distribution of segment
delays
Parameters
from
interconnect
topology
Distribution and expected value
of minimal clock cycle
"A probabilistic approach to clock cycle prediction"
Technology
and design
parameters
Experimental validation
Benchmark
circuits
100 placement runs each
Segment
delays
max. path delay
Measured
distribution of
maximal path
delays
68 benchmarks from LGSynth
series:
• sizes of 527 to 24819 blocks
• logic depths of 6 to 284
segment from ITRS
• Technology parameters
criticality
(ed. 2001, technology
node 2001)
distribution
• Delay models from
BACPAC
segment
(e.g. Sakurai, Chern, ...)
delay
distribution
1. traditional:
sum of
Predicted
average
distribution of
segment
delays
maximal path
2. new
delays
"A probabilistic approach to clock cycle prediction"
Experimental validation
Average maximal path delay (ns)
1.6
1.4
1.2
Experimental
Traditional estimation
New estimation
1
0.8
Correlation:
0.6
0.923 (traditional)
0.4
0.959 (new)
0.2
0
"A probabilistic approach to clock cycle prediction"
Experimental validation
Traditional estimation
New estimation
20
Average20%:
Within
10%:
relative
error:
• 21/68
10/68 (30.9%)
(14.7%)
-29.3% (traditional)
• 53/68
38/68 (77.9%)
(55.9%)
6.7% (new)
15
10
5
95
85
75
65
55
45
35
25
15
5
-5
-15
-25
-35
-45
-55
-65
-75
-85
0
-95
Number of benchmarks
25
Relative error (%)
"A probabilistic approach to clock cycle prediction"
Outline
• System-level interconnect prediction
• Prediction of minimal clock cycle
• New probabilistic approach
• Experimental results
• Main causes of errors
• Conclusions & future work
"A probabilistic approach to clock cycle prediction"
Validity of assumptions?
Both prediction strategies assume that
individual wire lengths are independent and
equally distributed random variables
They ignore that:
• some wires may almost always be long/short
(locally different distribution)
• there might be local correlations between wire
lengths (not independent)
"A probabilistic approach to clock cycle prediction"
Validity of assumptions?
Are deviations due to these assumptions or
to equivalent topology?
Monte Carlo experiment to meet assumptions:
• take measured segment delay distribution
• randomly assign delay from distribution to all
segments and find maximal path delay
• repeat 1000 times for each circuit
Only cause of remaining errors can be
equivalent topology!
"A probabilistic approach to clock cycle prediction"
Assumptions or equivalent topology?
Average maximal path delay (ns)
1.6
1.8
1.6
1.4
1.4
1.2
1.2
1
1
0.8
0.8
0.6
0.6
0.4
0.4
Experimental (Monte Carlo)
Experimental
Traditional
estimation
Traditional
estimation
New
estimation
New
estimation
Correlation:
0.977 (traditional, vs. 0.923)
0.996 (new, vs. 0.959)
0.2
0.2
0
"A probabilistic approach to clock cycle prediction"
Assumptions or equivalent topology?
Traditional estimation
New estimation
35
20
30
Within
Average
Within
10%:
20%:
relative
error:
• 2.9%
• 7.4%(vs.
(vs.14.7%)
30.9%)
-39.1 % (vs. –29.3 %)
• 63.2%
• 98.5%(vs.
(vs.55.9%)
77.3%)
-7.1 % (vs. 6.7 %)
25
15
20
10
15
10
5
5
95
85
75
65
55
45
35
25
15
5
-5
-15
-25
-35
-45
-55
-65
-75
-85
0
-95
Number of benchmarks
25
40
Relative error (%)
"A probabilistic approach to clock cycle prediction"
Remaining errors?
Rather systematical underestimation of
approximately 7%
Our equivalent path topology fully uncouples all
paths.
But there are alternatives:
• with same number of segments,
• also using criticalities,
• for which distributions can be calculated !
"A probabilistic approach to clock cycle prediction"
Remaining errors?
(a)
(b)
Example:
• measured average clock cycle using segment delay
distr. from one of the benchmark experiments
• result: clock cycle (a) 7.1 % below clock cycle (b)
Total uncoupling of paths seems too strong!
Can model be tuned to include this effect?
"A probabilistic approach to clock cycle prediction"
Outline
• System-level interconnect prediction
• Prediction of minimal clock cycle
• New probabilistic approach
• Experimental results
• Main causes of errors
• Conclusions & future work
"A probabilistic approach to clock cycle prediction"
Conclusions
• New probabilistic model for clock cycle
prediction:
• captures the essence of circuit parallellism
• based on equivalent graph topology with
independent paths
• Significantly improved accuracy reached within
same assumptions as existing work
• Experimentally verified that most of the
remaining errors are due to these assumptions
• They are OK for many circuits, but very bad
for some!
"A probabilistic approach to clock cycle prediction"
Future work
• More experiments to validate model sensitivity
to design options its and usefulness for
different applications
• Combine model with predicted wire length
distributions
• Try to find mathematical foundations for
equivalent topology
• Try to incorporate local effects and study
some alternative topologies
"A probabilistic approach to clock cycle prediction"
‘mm30a’: an example ...
Average wire length
Clearly shows
inhomogeneity,
with many of the
most critical
segments
systematically
having low delays
Benchmark mm30a
Criticality
"A probabilistic approach to clock cycle prediction"