Fixed-Point Numbers Positional representation: k whole and l fractional digits Value of a number: x = (xk–1xk–2 . . . x1x0 . x–1x–2 . . . x–l )r = Σ xi r i For example: 2.375 = (10.011)two = (1×21) + (0×20) + (0×2−1) + (1×2−2) + (1×2−3) Numbers in the range [0, rk – ulp] representable, where ulp = r –l Fixed-point arithmetic same as integer arithmetic Two’s complement properties (including sign change) hold here as well: (01.011)2’s-compl = (–0×21) + (1×20) + (0×2–1) + (1×2–2) + (1×2–3) = +1.375 (11.011)2’s-compl = (–1×21) + (1×20) + (0×2–1) + (1×2–2) + (1×2–3) = –0.625 EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 1/22 Radix Conversion for Fixed-Point Numbers Convert the whole and fractional parts separately. To convert the fractional part from an old radix r to a new radix R: • Perform arithmetic in the new radix R Evaluate a polynomial in r –1: (.011)two = 0 × 2–1 + 1 × 2–2 + 1 × 2–3 Simpler: View the fractional part as integer, convert, divide by r l (.011)two = (?)ten Multiply by 8 to make the number an integer: (011)two = (3)ten Thus, (.011)two = (3 / 8)ten = (.375)ten • Perform arithmetic in the old radix r Multiply the given fraction by R, use the whole part as the MSD and the fractional part to repeat the process (.72)ten = (?)two 0.72 × 2 = 1.44, so the answer begins with 0.1 0.44 × 2 = 0.88, so the answer begins with 0.10 EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 2/22 1 Floating-Point Numbers Useful for applications where very large and very small numbers are needed simultaneously • Fixed-point representation is not very good for dealing with very large and extremely small #s simultaneously x = (0000 0000 . 0000 1001)two Small number y = (1001 0000 . 0000 0000)two Large number • Neither y2 nor y / x is representable in the format above • Floating-point representation is like scientific notation: −20 000 000 = −2 × 10 7 0.000 000 007 = 7 × 10–9 Significand EE800-lec03_part1 (2010) Exponent base Exponent Also, 7E−9 The Arithmetic/Logic Unit 3/22 ANSI/IEEE Stand. Floating-Point Format (IEEE754) Revision (IEEE 754-2008) is available. Short (32-bit) format 8 bits, bias = 127, –126 to 127 23 bits for fractional part (plus hidden 1 in integer part) Sign Exponent 11 bits, bias = 1023, –1022 to 1023 Short exponent range is –127 to 128 but the two extreme values are reserved for special operands (similarly for the long format) Significand 52 bits for fractional part (plus hidden 1 in integer part) Long (64-bit) format Two ANSI/IEEE standard floating-point formats. EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 4/22 2 Short and Long IEEE 754 Formats: Features Some features of ANSI/IEEE standard floating-point formats Feature Word width in bits Significand in bits Significand range Exponent bits Exponent bias Zero (±0) Denormal Single/Short 32 23 + 1 hidden [1, 2 – 2–23] 8 127 e + bias = 0, f = 0 e + bias = 0, f ≠ 0 represents ±0.f × 2–126 e + bias = 255, f = 0 e + bias = 255, f ≠ 0 e + bias ∈ [1, 254] e ∈ [–126, 127] represents 1.f × 2e Double/Long 64 52 + 1 hidden [1, 2 – 2–52] 11 1023 e + bias = 0, f = 0 e + bias = 0, f ≠ 0 represents ±0.f × 2–1022 e + bias = 2047, f = 0 e + bias = 2047, f ≠ 0 e + bias ∈ [1, 2046] e ∈ [–1022, 1023] represents 1.f × 2e min 2–126 ≅ 1.2 × 10–38 2–1022 ≅ 2.2 × 10–308 max ≅ 2128 ≅ 3.4 × 1038 ≅ 21024 ≅ 1.8 × 10308 Infinity (±∞) Not-a-number (NaN) Ordinary number EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 5/22 Simple Adders Inputs Outputs x y c s 0 0 1 1 0 1 0 1 0 0 0 1 0 1 1 0 x c Inputs y HA s Outputs x y cin cout s 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1 x cout y FA s cin S = x ⊕ y ⊕ cin Cout = ycin + xy + xcin Binary half-adder (HA) and full-adder (FA). EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 6/22 3 Ripple-Carry Adder: Slow But Simple x31 y31 x1 c31 c32 FA cout . . . y1 c2 x0 y0 c0 c1 FA FA s1 s0 Critical path s31 cin Ripple-carry binary adder with 32-bit inputs and output. EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 7/22 Carry Propagation 0111 + 0001 1000 EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 8/22 4 •Carry Look-Ahead Adder •uses the concepts of generating and propagating carries •Ci+1=xiyi+ci(xi+yi), xiyi = gi, xi+yi=pi •Carry Bypass (=skip) Adder -Looks for cases in which carry out of a set of bits is identical to carry in EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 9/22 Design of Fast Adders •Carry Select Adder -Don’t know carry in: so do both -Use MUX to select the right sum •Carry Save Adder -produce the sum and carry bits separately and add them at the end -10011 + 00110 = (21+4) = 25, 01100+10011+00110 = (25+12) = 37 EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 10/22 5 Combined Addition/ Subtraction I. EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 11/22 Two’s-Complement Addition and Subtraction k / x c in Adder k / y k / k / x±y c out y or y′ Add′Sub Binary adder used as 2’s-complement adder/subtractor. EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 12/22 6 Combined Addition/ Subtraction II. EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 13/22 •Combined Addition/Subtraction II. - 4 FAs, 4 XORs, 1 extra control bit. Note: Combined Addition/Subtraction I. - 4 FAs, 8 ANDs, 4 ORs, 2 extra control bits EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 14/22 7 Magnitude Comparator EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 15/22 A3=B3 ? X3A2’B2 EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 16/22 8 Binary Multiplier EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 17/22 EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 18/22 9 Shift-Add Multiplication Multiplicand Multiplier x y Partial products bit-matrix y0 y 1 y2 y3 Product z x x x x 20 21 22 23 Multiplication of 4-bit numbers in dot notation. EE800-lec03_part1 (2010) The Arithmetic/Logic Unit Binary and Decimal Multiplication Position 7 6 5 4 3 2 1 0 ========================= 4 x2 1 0 1 0 y 0 0 1 1 ========================= (0) z 0 0 0 0 +y0x24 1 0 1 0 –––––––––––––––––––––––––– 2z (1) 0 1 0 1 0 z (1) 0 1 0 1 0 +y1x24 1 0 1 0 –––––––––––––––––––––––––– 2z (2) 0 1 1 1 1 0 z (2) 0 1 1 1 1 0 +y2x24 0 0 0 0 –––––––––––––––––––––––––– 2z (3) 0 0 1 1 1 1 0 z (3) 0 0 1 1 1 1 0 4 +y3x2 0 0 0 0 –––––––––––––––––––––––––– (4) 2z 0 0 0 1 1 1 1 0 z (4) 0 0 0 1 1 1 1 0 ========================= 19/22 Example Position 7 6 5 4 3 2 1 0 ========================= 4 x10 3 5 2 8 y 4 0 6 7 ========================= (0) z 0 0 0 0 +y0x104 2 4 6 9 6 –––––––––––––––––––––––––– 10z (1) 2 4 6 9 6 z (1) 0 2 4 6 9 6 +y1x104 2 1 1 6 8 –––––––––––––––––––––––––– 10z (2) 2 3 6 3 7 6 z (2) 2 3 6 3 7 6 +y2x104 0 0 0 0 0 –––––––––––––––––––––––––– 10z (3) 0 2 3 6 3 7 6 z (3) 0 2 3 6 3 7 6 4 +y3x10 1 4 1 1 2 –––––––––––––––––––––––––– 10z (4) 1 4 3 4 8 3 7 6 z (4) 1 4 3 4 8 3 7 6 ========================= Step-by-step multiplication examples for 4-digit unsigned numbers. EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 20/22 10 Example Two’s-Complement Multiplication Position 7 6 5 4 3 2 1 0 ========================= 4 x2 1 0 1 0 y 0 0 1 1 ========================= (0) z 0 0 0 0 0 +y0x24 1 1 0 1 0 –––––––––––––––––––––––––– (1) 2z 1 1 0 1 0 z (1) 1 1 1 0 1 0 4 +y1x2 1 1 0 1 0 –––––––––––––––––––––––––– (2) 2z 1 0 1 1 1 0 z (2) 1 1 0 1 1 1 0 +y2x24 0 0 0 0 0 –––––––––––––––––––––––––– 2z (3) 1 1 0 1 1 1 0 z (3) 1 1 1 0 1 1 1 0 +(–y3x24) 0 0 0 0 0 –––––––––––––––––––––––––– 2z (4) 1 1 1 0 1 1 1 0 z (4) 1 1 1 0 1 1 1 0 ========================= Position 7 6 5 4 3 2 1 0 ========================= 4 x2 1 0 1 0 y 1 0 1 1 ========================= (0) z 0 0 0 0 0 +y0x24 1 1 0 1 0 –––––––––––––––––––––––––– (1) 2z 1 1 0 1 0 z (1) 1 1 1 0 1 0 4 +y1x2 1 1 0 1 0 –––––––––––––––––––––––––– (2) 2z 1 0 1 1 1 0 z (2) 1 1 0 1 1 1 0 +y2x24 0 0 0 0 0 –––––––––––––––––––––––––– 2z (3) 1 1 0 1 1 1 0 z (3) 1 1 1 0 1 1 1 0 +(–y3x24) 0 0 1 1 0 –––––––––––––––––––––––––– 2z (4) 0 0 0 1 1 1 1 0 z (4) 0 0 0 1 1 1 1 0 ========================= Step-by-step multiplication examples for 2’s-complement numbers. EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 21/22 Hardware Multipliers Shift Multiplier y Doublewidth partial product z (j) Shift Multiplicand x 0 Mux 1 yj Enable Select c out Adder c in Add’Sub Hardware multiplier based on the shift-add algorithm. EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 22/22 11
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