Vol. 34, No. 6
Journal of Semiconductors
June 2013
Prevention of plasma-induced damage on thin gate oxides in BEOL sub-half micron
CMOS processing
He Qi(贺琪)Ž , Zhao Wenbin(赵文彬), Peng Li(彭力), and Yu Zongguang(于宗光)
China Electronic Technology Group Corporation No. 58 Institute, Wuxi 214035, China
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Abstract: A comparison is made of several plasma-induced damage (PID) measurement techniques. A novel PID
mechanism using high-density plasma (HDP) inter-metal dielectric (IMD) deposition is proposed. The results of a
design of experiment (DOE) on Ar pre-clean minimizing PID are presented. For HDP oxide deposition, the plasma
damage is minimal, assuring minimal exposure time of the metal line to the plasma using a maximal deposition
to sputter ratio. This process induces less PID than classic SOG processing. Ar pre-clean induces minimal plasma
damage using minimal process time, high ion energy and high plasma power. For metal etching, an HDP etch is
compared to a reactive ion etch, and the impact of the individual process steps are identified by specialized antenna
structures. The measurement results of charge pumping, breakdown voltage and gate oxide leakage correlate very
well. On metal etching, the reactive ion etching induces less plasma damage than HDP etching. For both reactors,
PID is induced only in the metal over-etch step.
Key words: plasma induced damage (PID); dielectric deposition; sputter ratio; antenna structure
DOI: 10.1088/1674-4926/34/6/066003
PACC: 7340L; 7340Q
1. Introduction
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The degradation of gate oxide MOS devices due to plasma
processing has become technologically important, and has
driven intense research since the device dimensions began to
approach the sub-half micron regimeŒ1; 2 and the gate oxide
thickness started to decreaseŒ3 .
This paper describes the identification and optimization of
all the main process steps responsible for plasma-induced damage (PID) in a sub-half micron CMOS process with five layers
of metal.
contacts varying from 1 up to 10.000. Cumulative structures,
including poly antennas, all metal layer contacts and vias, were
designed according to maximum A.R. design rules to measure
the impact of the full processing flow.
2. Antenna and test structures
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The test structures used were fabricated in the standard
flow of a 0.35 m twin well standard CMOS with up to five
layers of metal. All the structures were connected to a transistor with a 2 0.35 m2 gate area attached to metal antennas
of various designs, most of which are available in both NMOS
and PMOS. For the conductors (poly and metal), the antennas
were designed as plates and comb structures. To investigate
the classical and extended electron shadingŒ4 , comb structures
were designed with minimal (0.6 m) and maximum (5 m)
spacing between the lines. The timing of the electron shading
effects was extracted with the help of the transient (T)–fuse
schemeŒ5 . To investigate the impact of the size of the antenna
and to ensure that the nature of the damage was plasma, the antennas were designed with a ratio (A.R.) of 1.000 up to 100.000
compared to the gate area. All the antennas were protected from
the impact of charging from conductors on higher levels by a
double diode. Figure 1 is an example of a poly antenna for the
PID test structure [BL9MOD5].
To investigate the impact of the contact and via processing plate, antennas were designed on top of a range of vias or
3. Measurement
To evaluate the different measurement techniques, charge
pumping (CP), breakdown voltage (Vbd / and gate oxide leakage were compared as a function of A.R. for metal combs with
0.6 m spacing (Fig. 2). Due to the high plasma density, the
HDP etcher was found to induce significantly more PID than
the MDP etcher. This difference was used to compare and correlate the measurement methods.
All the techniques correlated very well. CP is capable of
measuring latent damage caused by antennas 10 times smaller
than those starting to cause leaking gate oxides.
Figure 3 is a mapping of Vbd that fits perfectly with the
gate oxide leakage (Ig / mapping. Since full wafer mapping is
required to reveal patterned PID, gate oxide leakage measurement was selected because of its reduced measurement time
and good resolution in revealing extrinsic gate oxide damage.
The plasma processes in the BEOL flow include highdensity plasma oxide deposition (HDP-CVD), PETEOS deposition, contact and via etching, Ar pre-sputter cleaning prior to
contact/via Ti–TiN glue layers, resist striping and metal etching, and finishing with oxide–nitride deposition and patterning
as the passivation layer. Below, some of the data is represented
with surprising results. All the results are presented as the percentage of gates with an oxide-leak current larger than 1 nA at
a gate voltage of 3.63 V.
† Corresponding author. Email: [email protected]
Received 29 November 2012, revised manuscript received 21 January 2013
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He Qi et al.
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Fig. 1. Layout of the poly antenna for the PID test structure.
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Fig. 2. CP current, Vbd and gate leakage as a function of A.R. for the
HDP and MDP.
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Fig. 4. Fused metal antennas measuring (a) the PID of the full metal
etch process, (b) the PID of the over etch only, and (c) the PID of the
main etch only.
Table 1. The comparison of four processes with varying pressure and
source power.
Parameter Proc.1
Proc.2
Proc.3
Proc.4
Full etch
19%
7.14%
10.71%
14.28%
Main etch 0
0
0
0
Over etch
21.43%
9.52%
10.72%
17.86%
Fig. 3. The results of gate oxide leakage and voltage breakdown measurements.
4. Metal etch
As already mentioned in this paper, the HDP metal etcher
induces significantly more PID than the MDP etcher. In order to identify the process step responsible for the PID during
metal etching in the HDP etcher, T-fused antennas were processed and measured. The fuses are made by designing a small
interruption in the metal line. This interruption is designed such
that the fuse is only opened at the end of the main etch step.
With this technique, the diode protection or the antenna can be
isolated from the gate and the end of the main etch step.
Three types of antennas were compared (Fig. 4): (a) measuring the PID of the full etch process, (b) with a fused diode
connected to the antenna, with only the impact of the over-etch
being measured, and (c) with a fuse in the antenna connection,
and only the impact of the main-etch measured.
Four processes with varying pressure and source power
were compared. The results, expressed as leaking gate oxides,
are represented in Table 1 below.
Over a wide range of processes, no PID is generated during the main-etch. Only the over-etch is responsible for the full
PID.
This technique provides important information on the pro-
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J. Semicond. 2013, 34(6)
Fig. 5. Plasma damage induced by HDP oxide deposition PID expressed as leaking gates with Ig > 1 nA (Mn: n as the metal level
of the comb antenna).
cess step responsible for the plasma damage in cases where an
etch process needs to be improved.
Fig. 6. Plasma damage induced by SOG and HDP oxide deposition
gap-fill processing PID expressed as leaking gates with Ig > 1 nA Ar
pre-clean processing.
5. HDP inter-metal dielectric oxide deposition
Fig. 7. Via resistance (/ as a function of ion energy and plasma density.
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In the 0.35 m technology, HDP oxide deposition was introduced to replace the SOG used in previous generations of
technology. HDP oxide deposition is combining PECVD oxide deposition (D) with Ar sputter etching (S). The ratio of
these two processes (D/S) determines the gap fill capability of
the process. In this high-density plasma environment, the PID
risk is very high. Previously, to prevent PID it was proposed
to deposit a thin layer without a sputter etch component (liner)
prior to HDP depositionŒ6 , or to use a multiple step depositionŒ7 . Using these techniques, considerable PID can still be
measured.
Four kinds of deposition were compared: high D/S with
liner, high D/S without liner, low D/S with liner and low-high
D/S multiple step with liner (Fig. 5). In all cases, the liner is a
50 nm oxide.
Both processes with high D/S showed low PID. Processes
with a low D/S step, with or without a liner, show high PID.
These experiments prove that it is not the liner that is preventing PID, but a D/S that is too low. When using a D/S that is
too low, the upper corners of the metal lines remain exposed
to the plasma during a large part of the process. Even when a
liner is deposited prior to HDP deposition, this liner may be
removed from the corners of the metal lines by sputter etching
during the process, allowing the exposed metal lines to pick up
charges from the plasma. This mechanism is clearly illustrated
by the cross-sections of metal lines covered with the partial deposited layer, and shows that during HDP deposition with low
D/S, the top corners of the metal structures remain open to the
impact of the plasma during a large part of the processing.
To evaluate the lower damage HDP deposition, it has been
compared with low damage SOG processing, and the results
are presented in Fig. 6. A huge antenna with an A.R. of 100.000
had to be used to measure the PID. The new HDP processing
proves to induce even less PID than the classic low damage
SOG process.
A matrix of plasma power and plasma density was processed. Time was adjusted to keep the oxide removal constant,
and plasma damage was measured as gate leakage on gates
connected to 10.000 vias. The results were modeled in a lin-
ear model giving a good fit.
The percentage of failing gates is decreasing mainly by increasing bias (ion energy) and less by increasing plasma power
(ion density) and/or decreasing process time. The combination
400 W ion energy with 300 W plasma density was found to be
the optimal combination for low plasma damage, good uniformity and low via resistivity (Fig. 7).
For a number of etch processes, it was reported that PID
was reduced by reducing the plasma density and increasing the
bias powerŒ8; 9 , while we see a decrease with increased plasma
density. For the references, the process times were kept constant. In this experiment, the process time could be reduced
significantly from 60 to 15 s due to the increased etch rate with
high plasma density. This demonstrates that for this process,
the process time has a larger impact on PID than the increased
PID due to the increase in plasma density.
6. Conclusions
The measurement results of charge pumping, breakdown
voltage and gate oxide leakage are shown to correlate very
well. For HDP oxide deposition, plasma damage is minimal,
assuring minimal exposure time of the metal line to the plasma
using a maximal deposition to sputter ratio. This process induces less PID than classic SOG processing. There is evidence
that the allowed antenna ratio is decreasing on higher metal layers. Ar pre-clean induces minimal plasma damage using minimal process time, high ion energy and high plasma power. On
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metal etching, MDP etching induces less PID than HDP etching, and PID is induced only in the metal over-etch step, so a
neighboring impact is not expected.
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