Chapter 4.
Field Effect Transistor
Golden Rule : JFET(잘 안씀)
ID
아날로그 회로
nMOS
enhancement
Saturation
(On)
Linear
(On)
nMOS
depletion
n-JFET
1. 화살표는, Gate의 forward
bias 방향
(또는 channel type) 표시
pMOS
depletion
2. VGS는 reverse bias,
Drain은 Gate의 반대전압
pMOS
3. IG ~ 0
enhancement
디지탈 회로
VGS> VT (On) : ~ RDS
VGS< VT (Off) : 끊어짐




1


 I

 2 DSS2 (V GS  VT )


VT


VGS
p-JFET
Off
(VGS<VT)
ID
VDS < VGS-VT
(Linear) : 가변저항
 I
DSS
ID  2
 VT
2

(V GS VT )V DS

VDS
VDS > VGS-VT
(Saturation) : 전류 소스
ID 
IDSS
(V GS VT )2
2
VT
Golden Rule : MOSFET(주로 디지탈 회로)
ID
아날로그 회로
nMOS
enhancement
Linear
(On)
nMOS
depletion
Saturation
(On)
n-JFET
VGS
1. 화살표는 Gate의 forward
bias 방향
(또는 channel type) 표시
2. VGS는 reverse bias,
D는 G와 같은 방향 전압
3. IG ~ 0
디지탈 회로
p-JFET
pMOS
depletion
pMOS
enhancement
ID
Off
(VGS<VT)
VDS


VDS < VGS-VT
VDS > VGS-VT




(Linear) : 가변저항
(Saturation) : 전류 소스
1
VGS> VT (On) : ~ RDS  

ID (ON )
 2
ID (ON )
(V GS VT )

2
2
ID (ON )
I

(
V

V
)

 I  2
D
GS
T
2


V

V
(V VT )V DS
GS (ON )
T

 D
2 GS
V GS (ON ) VT 


V

V


GS
(
ON
)
T


VGS< VT (Off) : 끊어짐
1. JFET
Junction Field Effect Transistors (JFET) 원리
Depletion 영역
(높은 저항)
n
p
n
p
n
p
n
p
Linear
Saturation
- 기호의 G 화살표가 forward bias 방향
- G 는 S에 대해서 reverse bias 걸어서 사용
- G에 걸린 reverse bias가 커지면, depletion
영역이 넓어져서, 전류가 줄어든다.
- S는 D에 대해서, ground (n-channel JFET)
또는 최고 전압(p-channel JFET)에 연결
Saturation 영역 발생 원인
-V
+V
Depletion 영역
(높은 저항)
Linear 영역 (작은 VDS)
0V
- drain-source 사이의 channel
에 흐르는 전류 ID는, channel에
걸리는 전압VDS 와 channel 저항
Rch 에 의해 결정 : ID = VDS/Rch
gate에 대한 상대적인 reverse bias가,
drain이 source보다 더 크기때문에,
drain 쪽 depletion 영역이 더 깊다.
-V
Saturation영역 (큰 VDS)
++V
0V
-
VDS 가 증가해서 VDS (sat)(=VGS-VT)에 이르면, drain 쪽에 depletion영역이 겹
쳐서 저항이 매우 높은 좁은 영역 형성
만일, VDS를 VDS (sat) 이상으로 올리더라도, 증가한 전압이 모두 이 영역에 걸리
고, channel에 걸리는 전압은 VDS (sat) 로 한정된다.
따라서, ID = VDS(sat)/Rch 로서 일정하게 된다.
Golden Rule : JFET(잘 안씀)
ID
아날로그 회로
nMOS
enhancement
Saturation
(On)
Linear
(On)
nMOS
depletion
n-JFET
VGS
1. 화살표는, Gate의 forward
bias 방향
(또는 channel type) 표시
2. VGS는 reverse bias,
Drain은 Gate의 반대전압
3. IG ~ 0
디지탈 회로

VGS> VT (On) : ~ RDS
VGS< VT (Off) : 끊어짐
p-JFET
Off
(VGS<VT)
ID
pMOS
depletion
pMOS
enhancement



1


 I

 2 DSS2 (V GS  VT )


VT


VDS < VGS-VT
(Linear) : 가변저항
 I
DSS
ID  2
 VT
2

(V GS VT )V DS

VDS
VDS > VGS-VT
(Saturation) : 전류 소스
ID 
IDSS
(V GS VT )2
2
VT
JFET 특성의 예
1.
2.
3.
4.
5.
BVGSS : Gate-Source breakdown
voltage, Gate에 이 전압 이상 걸어주면
breakdown이 생겨 망가짐.
IDSS : VGS=0일 때 saturation drain
current ID(sat) .
VGS(OFF), VP : pinch-off voltage,
threshold voltage(VT)의 절대값
Ciss = CGS+CGD
Crss = CGD
CGS : gate-source간 capacitance
CGD : gate-drain 간 capacitance
JFET 회로의 예 : Current source
1. VT < 0 for n-JFET
2. VGS=0 > VT
3. VDS가 높지 않으면(VDS < VGS-VT), 트랜지스터는 가
변저항으로 작동(VGS = 0)
 I
DSS
ID  2
 VT

2


I
(
V GS VT )V DS ~   2 DSS
VT




V DS



V
V  R loadID  V DS  R loadID    T ID
 2IDSS 
ID ~
V


V
R load    T 
 2IDSS 
4. (VDS > VGS-VT)이도록 V를 충분히 높이면,
전류 소스로 동작(VGS = 0)
ID 
IDSS
(V GS VT )2  IDSS
2
VT
2. MOSFET
MOSFET(n-channel, enhancement mode) 원리
VGS=0
(a) Gate 전압 VGS=0이면, drain source 간에 n-p-n 접합 구조이기 때문에 전류가 흐르지 못함.
(b) Gate에 약한 +전압이 걸리면, electron들이 gate 밑에 모여서 원래 있던 hole들을 죽여서
depletion영역 형성
(c) Gate에 강한 +전압이 걸리면, 아주 많은 electron들이 gate 밑에 모여서, 원래 있던 hole들을
죽이고도 남아서, 실질적으로 electron들이 더 많은 “실질적인 n-type 영역” 형성. 따라서,
source-drain간에 n-n-n접합구조처럼 되므로 전류가 흐름.
(n+, p+ 등 + 사인은 높은 doping level(많은 양의 불순물/carrier을 의미함)
Saturation 영역이 생기는 이유
Linear 영역 (작은 VDS)
- drain-source 사이의 channel
에 흐르는 전류 ID는, channel에
걸리는 전압VDS 와 channel 저항
Rch 에 의해 결정 : ID = VDS/Rch
Saturation영역 (큰 VDS)
-
VDS 가 증가해서 VDS (sat)(=VGS-VT)이상 올라가면, “drain 근처 gate 밑의 구간”의 전압이
높아져서, gate의 전압이 그 영역의 전압에 비해서 충분히 높지 않게 된다. 따라서, 이 영역
에는 free electron이 없이 depletion영역만 생겨서, 저항이 매우 높은 좁은 구간 형성
만일, VDS를 VDS (sat) 이상으로 올리더라도, 증가한 전압이 모두 이 영역에 걸리고, channel
에 걸리는 전압은 VDS (sat) 로 한정된다.
따라서, ID = VDS(sat)/Rch 로서 일정하게 된다.
Golden Rule : MOSFET(주로 디지탈 회로)
ID
아날로그 회로
nMOS
enhancement
Linear
(On)
nMOS
depletion
Saturation
(On)
n-JFET
VGS
1. 화살표는 Gate의 forward bias
방향 (또는 channel type) 표시
pMOS
depletion
2. VGS는 reverse bias,
D는 G와 같은 방향 전압
pMOS
enhancement
3. IG ~ 0
디지탈 회로
p-JFET
ID
Off
(VGS<VT)
VDS


VDS < VGS-VT
VDS > VGS-VT




(Linear) : 가변저항
(Saturation) : 전류 소스
1
VGS> VT (On) : ~ RDS  

ID (ON )
 2
ID (ON )
(V GS VT )

2
2
ID (ON )
I

(
V

V
)

 I  2
D
GS
T
2


V

V
(V VT )V DS
GS (ON )
T

 D
2 GS
V GS (ON ) VT 


V

V


GS
(
ON
)
T


VGS< VT (Off) : 끊어짐
MOSFET 특성의 예
1.
2.
3.
4.
5.
6.
7.
RDS(on) : VGS를 VGS(on)(>VGS(th))로 고정하고 VDS가 작을때 (VDS<VGS) 의 RDS
VGS(th) : threshold gate voltage VT
ID(on) : 트랜지스터가 켜졌을 때 drain current (이전 슬라이드의 식 참조)
Crss = CGD (gate-drain 간 capacitance)
BVDS : drain-source breakdown voltage
BVGS : gate-source breakdown voltage
IGSS : gate leakage current
Enhancement vs. Depletion Mode MOS FET
nMOSFET

0
Cut - off

V2 
 
I D    n (VGS  VT )VDS  DS  Ohmic
2  Linear
 


Saturation
I Dsat  n (VGS  VT ) 2
2

Z n C 0
where  n 
L
n+
n+
Enhancement mode n-MOS FET
n+
n
n+
1)
2)
pMOSFET

0
Cut - off

 
V2 
I SD    p (VSG  VT )VSD  SD  Ohmic
Linear
2 
 


I Dsat  p (VSG  VT ) 2
Saturation
2

Z p C 0
where  p 
L
Depleted without
voltage
Depletion mode n-MOS FET
p+
p+
Enhancement mode p-MOS FET
Source is connected to body.
Source has a lower potential
than the drain and gate.
1)
2)
Source is connected to body.
Source has a higher potential
than the drain and gate.
Symbols of MOSFET
*Broken lines for enhancement mode
Switches
S
D
G
FET on
(Linear)
FET off
D
G
MOSFET analog switch.
S
- 15V (VGS >VT) : Linear, R ~ 1/(VGS-VT))
- Ground (VGS<VT) : Cut off
다양한 Inverters
CMOS(Complementary MOSFET)회로 : CMOS Inverter
=5V
S
p-MOS
(Load)
D
D
S
n-MOS
(Driver)
1) If Vin = 5V (input high),
-> VGSn = 5V > |VTn|
VSGp = 0V < |VTp|
-> n-MOS: ON with a small R
(VDS ~ 0 < VGT-VT : Linear Region)
p-MOS: OFF with an infinite R
-> NO Current
-> Vout = 0 (output low)
2) If Vin = 0V (input low),
-> VGSn = 0V < |VTn|
VSGp = 5V > |VTp|
-> n-MOS: OFF with an infinite R
p-MOS: ON with a small R
(VSD ~ 0 < VSG-VT : Linear Region)
-> NO Current
-> Vout = 5V (output high)
No static power consumption for CMOS Circuits.
-> Integrated Circuits for Computer Processors.
CMOS Logic
Logic Circuit in CMOS Architecture
1.pMOS :
• First, take the inverse of ‘each’
variable
• ‘OR’ : parallel connection
• ‘AND’ : Serial Connection
2.nMOS :
• First, take the inverse of the
entire function.
• ‘OR’ : parallel connection
‘AND : serial connection
VDD
NAND
Gate
A
B
Z
Z
Z  A B
A
B
VDD
NOR
Gate
A
B
Z
Z  A B
A
B
Z
Note)
1. The logic functions are
implemented twice, once in
NMOS and once in PMOS
devices.
2. Zero static power dissipation.
3. All devices can be the same size
and circuit functions correctly.
4. The output of a logic circuit is
connected to the input of the
next logic circuit.
CMOS AND gate (NAND gate and Inverter)
X
X
1
0
O
1
O
A
B
Output
1
1
0
1
0
1
0
1
1
0
0
1
Simple Dynamic Random Access Memory (DRAM)
(Bit Line)
(Word
Line)
1) When CS is
charged/discharged, it
represents 1/0, respectively.
2) Read Cycle: M1 is on and the
value in CS is read using the
BL (bit line). During the read
cycle, small amount of
charge is transferred to CBL.
Thus, the DRAMs lose charge
each read cycle and they
often requires refresh cycle.
3) Write Cycle: The value on BL
is fixed by external circuits,
and M1 is on so that the
value on BL is transferred to
CS through M1.
4) Writing Speed:
f ~ (RM1Cs)-1
Logic to Microprocessors
Vin
Vout
Vin
Vout
Equivalent
Circuit
Vin
Vout
CL
capacitors
Logic to Microprocessors (Conti.)
When Vin is low, pMOS is on, nMOS is off, and Vout goes from low to high,
Vout
Rp
On
Off
Vout
Effectively RC Circuit
 L H ~ R pCL
CL
time
Vout
Vout
Rn
Effectively RC Circuit
 H L ~ RnCL
time
Speed of Microprocessors
Vin
Vout
Vin
Vout
 L H ~ R pC L ,
Maximum
f~
는 mobilty
 L H
 H L ~ R nC L
Computer Clock Frequency :
1
1
~
  H L
C L R p  R n 
Why Si dominates the computer industry?
1)
Si has high quality insulating oxide layer. Germanium oxide can be
dissolved in water.
2)
CMOS logic circuits does not have static power dissipation, which
dramatically minimizes the total power consumption.
3)
In CMOS logics, the maximum clock speed is determined by both hole and
electron mobility. Even though one can increase the clock speed by
increasing the width, it actually increases the size of circuits and load
capacitance, and eventually, slow down the overall speed.
f~


L H
1
1
~
  H L
C L R p  R n 
Ex.) pure Si: n = 1360 cm2/V-sec, p = 460 cm2/V-sec
pure GaAs: n = 8000 cm2/V-sec, p = 320 cm2/V-sec
(note) Larger hole mobility is one reason why silicon dominated
computer chip industry.
3. 트랜지스터 특성 비교
BJT vs. MOSFET
BJT: the original transistor, dominate analog circuit design
JFET, MOSFET 특성 비교
MOSFET dominates current microelectronics.
-As many as 35 process steps are required to produce a bipolar
transistors, but 9 manufacturing processes for MOSFET.
-Low wasted power
Transistors 비교 정리
Input
BJT
JFET
MOSFET
IB
VG
VG
장점
Output
단점
• base 전류가 많아 power 소모가
크다
IC
• 많은 전류를 흐를 수 있다.
• Input과 output의 신호의 polarity가
같아서 다음 단계 회로 연결이 용이.
• 주로 high power 회로에 많이 응용.
• VT값이 다른 트랜지스터에 비해 일정
IDS
•
•
•
•
많은 전류를 흐를 수 있다.
낮은 gate 전류
높은 input 저항
Constant current source 등에 응용
• 소자마다 VT값이 많이 다름
• Input와 output의 polarity가
달라서 다음 단계 회로 연결이
불편.
IDS
•
•
•
•
원칙적으로 gate 전류는 0.
gate power dissipation 이 없음.
input 저항 무한대
컴퓨터 논리 회로에 응용
• 소자마다 VT값이 많이 다름
• 흘릴 수 있는 전류 용량이
상대적으로 낮다.
4. Microfabrication
(참고자료, 학기말 시험에 안나옴.)
4.1 기본 공정
Basics Microfabrication
Processes
Diffusion Windows
Single Crystal
p-Si Substrate
Substrate
Etching
Epitaxial
Layer
Epitaxy
Oxide Layer
Oxidation
Diffusion or
Ion Implantation
Metallization
Epitaxial Deposition
Application: Growth of thin film (1-20um,
typically 2um) of n- or p-type Si on a
crystalline substrate.
Gas
Phase
Epitaxial
Film
Substrate
Features:
1. Results in single crystal layer.
2. Chemical reaction
(Silane) SiH4 + H2 ->Si + 3H2
(Silicon Tetrachloride)
SiCl4 + 2H2 -> Si + 4HCL
3. Epitaxial layer can be grown over
diffused region or other epitaxial layer.
4. Silicon grown over SiO2 is randomly
oriented and called polysilicon.
5. High temperatures (~1100C) cause
outdiffusion of previously diffused
impurities.
Oxidation Process
Applications:
1. Serves as a diffusion barrier and can be etched to allow selective
diffusions.
2. Protect device junctions from atmospheric contamination.
3. Serves as a low leakage insulator on which metal interconnect
can be run.
Features:
1. Occurs evenly across the wafer.
2. Chemical reaction
Si + O2 ->SiO2 or Si + 2H2O -> SiO2 + 2H2
3. Temperatures: 900oC – 1200oC
4. Occurs at Si-SiO2 interface so requires O2 to diffuse through a
growing SiO2 layer.
Growth rate ~ t (thin layers)
t1/2 (thick layers)
Diffusion
Common Dopants:
P-Si: Boron, Al, Ga, In
N-Si: P, As, Sb
Constant Source Diffusion
 x
N(x, t)  N 0 erfc 
 2 Dt
where N(x, t)  density



(atoms/cm 3 ), N 0  surface concentrat ion,
D  diffusion coefficien t of dopants, T  1100o - 1300o C, and Junction Depth  0.1um - 20um
Typical Constant Source Diffusion System
Limited Source Diffusion
 x
N(x, t)  N 0 erfc 
 2 Dt
where N(x, t)  density



(atoms/cm 3 ), N 0  surface concentrat ion,
D  diffusion coefficien t of dopants, T  1100o - 1300o C, and Junction Depth  0.1um - 20um
Metal Deposition I:
Vacuum Evaporation
Features:
1. High vacuum (10-5 -10-6 torr)
2. Materials: Au, Al, Si etc.
Metal Deposition II: Sputtering
Features:
1. Cathode is coated with target
metals.
2. High voltage (~5000V) is
applied between cathode and
anode.
3. Low pressure argon ions are
formed which accelerate
toward cathode, causing
metal to float away.
4. High melting temperature
materials: Fe etc.
Photolithography
Characteristics of Photoresist:
1. Sensitive to UV light.
2. Developed like photographic film.
3. Exposed and developed resist is impervious to HF acid used to
etch SiO2, but can be removed with an organic solvent.
4. Can be of negative or positive type.
Photolithography for Diffusion
Photoresist Layer
Mask
Developed PR Window
Etched SiO2 Window
Mask Exposure Methods
1.
2.
3.
Usually low resolution.
(>1 um linewidth)
Academic systems.
Cheap equipment.
1.
2.
3.
Best results
(<100nm linewidth)
Industrial systems.
Expensive equipment.
4.2 BJT
Biopolar Junction Transistor
N--type buried layer diffusions
Bipolar Transistor
Resistor
SiO2
n--type buried layer diffusions
Epitaxial Layer
Bipolar Junction Transistors (Conti.)
isolation diffusions
p-type base diffusion
Bipolar Junction Transistors (Conti.)
n--type emitter diffusion
contact window
Aluminum
Interconnection
Bipolar Junction Transistors (Conti.)
Ground
(emitter)
input
(base)
p-isolation
wall
interconnections
resistor RL
Emitter
Base
Collector
V+
Bipolar Junction Transistors (Conti.)
4.2 CMOS
CMOS Process
N
N+ substrate
nMOS Region
pMOS Region
N
N+ substrate
Active Area
Mask #1
CMOS Process (Conti.)
P+ implant
P-Well
Mask #2
N
N+ Substrate
P diffusion
P Well
N
N+ Substrate
CMOS Process (Conti.)
N+ implant
P Well
N
N+ Substrate
Thick oxide to prevent the
accidental gating effect.
P Well
N
N+ Substrate
Lateral
Channel Stop
Mask #2
(negative)
CMOS Process (Conti.)
P Well
N
N+ Substrate
P Well
N
N+ Substrate
CMOS Process (Conti.)
Poly-silicon
Mask #3
P Well
N
N+ Substrate
P Well
N
N+ Substrate
CMOS Process (Conti.)
P+ Implant
Mask 4
P Well
pMOS
N
pMOS: S/D
nMOS: body
contact
N+ Substrate
N+ Implant
Mask 4
(negative)
P Well
N
N+ Substrate
pMOS: body
contact
nMOS: S/D
CMOS Process (Conti.)
P Well
N
N+ Substrate
Contact
Mask #5
P Well
N
N+ Substrate
Metal Line
Mask #6
CMOS Process (Conti.)
via Mask #7
P Well
N
N+ Substrate
via Mask #8
P Well
N
N+ Substrate
4.3 Photomask Layout
Layout Example: Inverter
VDD
poly
silicon
pMOS
p-Well
G
GND
pMOS: p+ implant
nMOS: n+ implant
n-
From Layout to Mask
Mask 1 (Active Area)
Mask 3 (polysilicon)
Mask 2 (p-Well)
Mask 4 (S/D/body contact mask)
Mask 5 (Contact)
Mask 6 (Metal)
Design Rules
1.
Rules to design VLSI layouts without parasitic effects.
2.
The design rules are developed by process engineers and
provided to VLSI layout designers.
3.
Example: minimum gate length in poly silicon mask
IT 산업에서의 분업화
Device Modeling
(calculation cost)
VLSI Layout
(device size, design rules)

0

V2
 Z C 
I D   n 0 (VG  VT )VD  D 
2 
 L 

Z n C 0
(VG  VT ) 2
I Dsat 
L

Device Development
and Characterization
(on-off current, speed)
Computer
Chips
Process Development
(yield, cost, design rules)
Logic Design (speed, power)
Meter Check of JFET
anti-static foam
-usually no difference between the source and drain terminals.
-any meter reading of continuity through that channel will be
unpredictable due to a stored charge across the capacitance of the
gate-channel PN junction
-anti-static foam