General Introduction to
Electronics Group
Wei WEI
State Key Laboratory of Particle Detection
and Electronics
2017/7/31
ASIC research in IHEP
• ASIC Group in EPC, IHEP
– With 9 staff and 1 PhD student
 Most of them are PhD
– With 8 years research history in ASIC design
– Active in international collaborations
 ATLAS, LHASSO…
• Three Major Direction
– Micro Pattern Gas Detector Readout
 GEM, MicroMegas, …
– PMT Detector readout
 LHASSO, Juno, …
– Silicon Pixel Detector readout
 Sync-Radiation, ATLAS Pixel
• Other research
– ADC, Waveform Sampler
2
3
4
实测结果
线性放电级输出@55Fe with GEM
线性放电级输出
甄别器输出
刻度信号
• 芯片实测功能正常：
• 纯芯片噪声774e• TOT脉冲前沿jitter 200ps
• 和GEM探测器55Fe放射源初步联调结果
• 能够看到正常的放射源下模拟输出波形
• 联调系统等效输入端噪声＜1000e• 正进一步测试TOT甄别脉冲性能
5
PMT Readout: LHAASO-WFCTA
• 16 Channels
• Auto select High Gain &
Low Gain for wide
dynamic
• Self- peak holding
• Self-trigger or external
trigger：
• 16 trigger output/ 1
analog peak value output
(in serial)
ARCHGARD
0.05
0.00
-0.05
-0.10
res
-0.15
-0.20
-0.25
-0.30
0
50
100
150
250
300
E
Linear Fit of Data13_E
600
500
output(mV)
200
400
300
200
100
0
0
1pe
50
100
150
200
250
300
input(mV) 1pe~0.8mV
2-350pe（ 3%）
4
res
2
output(mV)
0
0
500
1000
1500
2000
2500
3000
0
500
1000
1500
2000
2500
3000
400
350
300
250
200
150
100
50
0
300p.e.（RC=50ns）
input (mV) 1pe~0.8mV
10-3750pe
（18%,200pe~50%）
PMT Related Design for JUNO Experiment
• In design of a 1Gsps Waveform Sampling ASIC, based on
a switched-capacitor S/H array, and a distributed on-chip
Wilkinson ADC
• 8+1 Channels with 256 storage cell/chn
• Will be taped out in Nov.
8
Other research
• Low noise amplifier design
• On-chip multichannel A/D convertor block
– 12bit Wilkinson ADC
– 10bit, 3.3Msps Successive-approximation ADC
• Waveform sampling techniques
– 8 channel, 32 cells depth, 100Msps waveform sampler/analog Mem
– 1Gsps, 10/12bit high speed waveform sampling R&D
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Silicon Pixel Detector R&D for BAPS
• One of the detector R&Ds in BAPS
• Focusing on Synchrotron Radiation applications
• Project Goal：
– Sensor: no condition for sensor production, to gain experience of sensor
design and measurement from collaboration Project Specification:
– Self designed ASIC readout chip and DAQ
– Bump Bonding: by help of the collaboration
– Self designed mechanical supporting system
• ASIC Specification
Pixel Cell Size
150μm×150μm
Frame rate
100~1kHz
Pixel array
72col×104row
Energy range
8keV~20keV
Operation mode
Counting
Counting depth
20bit
ENC
<200e
Thres. Dispersion
<200e
Estimate power
<50μW/pixel
Total power diss.
400mW
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Pixel ASIC Design—— Pixel Cell
• Analog：
• Digital：
 Charge amp
 Counting chain
 Shaper/amp
 Shift out chain
 discriminator
 Pixel mask
 Local thres. tuning  Bus driver
 Calibration block
 Row/Col Sel.
Pixel Cell 100μm×100μm
On SMIC 0.13μm Technology
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Pixel ASIC Design——Periphery
• Counting data will be shifted out to periphery every frame
• Counter chain and the shift-out chain are independent
DFF chains so that it doesn’t need high speed serializer
• Configuration data is shift-in to every pixel by re-using the
shift chain, so that config data are refreshed every frame
12
Recent Progress
Layout of the ASIC
Sensor & ASIC on beam line for test
Sensor prototype wire
bonded with ASIC
An engineering run for a
1.7cm*1.1cm chip
A 1:1 size chip bump-bonded for
process evaluation
13
ASIC Measurement Result
S-curves before calibration
Thres Distribution after
Calibration=30.1e-
•
•
•
•
•
S-curves after calibration
Noise Histogram: ENC~88e-
A Pixel Readout ASIC with a 20*24 pixel array
Threshold calibration by on-pixel 5bit DAC
Threshold non-uniformity after calibration = 30.1eMeasured ASIC ENC noise about 88e- unbonded
No crosstalk counts found when sys clk goes upto
30MHz
 Estimated frame rate > 1kHz at final array size
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Sensor with ASIC on beam line
Single photon Shaper
and discriminator
output@8keV
Single photon Shaper
and discriminator
output@55Fe (5.9keV)
High counting rate over
1.5MHz/pixel,
Saturation not found
15
Counting vs Threshold @ various energy
18keV
12keV
16keV
10keV
14keV
8keV
Preliminary results
Energy Spectrum@18keV
Energy Peak Position vs Energy
Energy Spectrum@8keV
Counting rate vs Luminosity (measured by
Ionization Chamber)
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和目标芯片指标对比
对比指标
Pilatus I chip Pilatus II chip 本设计
像素尺寸
217μm×217μm
172μm×172μm
150μm×150μm
像素阵列
44×78
60×97
72×104
帧刷新率
10Hz
(Pilatus 1M)
30Hz
(Pilatus 2M)
> 1kHz
( 360k pixels)
读出时钟
10MHz
66.6MHz
> 17MHz
读出死时间
6.7ms/fr
2.85ms/fr
116.7ns/fr@30MHz
最高计数率
10kHz/Pixel
8MHz@low gain
> 1MHz/Pixel
0.9MHz@high gain
能量探测范围
> 4keV
> 4keV
8~20keV
等效输入端噪声
75e- bump bond
123e- bump bond
87.3e- unbond
188e-@1pF wire bond
不一致性
55e-
10e- ~ 13e-
< 60e-
计数深度
15bit
20bit
20bit
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Bump Bonding Candidate Process found
• Evaluated by 1:1 size (74*104 array) readout
ASIC, measuring the Pad-to-Pad capacitance,
based on 3T-like structure
• Engineering run on Global Foundry 0.35um
• Wafers pre-tested by ATE, then delivered to
different institutes for bump-bonding
• Found Process A better than the others, with
rare defects (<0.1%), as the candidate
• Yield of a 1.7cm*1.1cm ASIC ~80%
Candidate process A: after bumpbonding
Candidate process B
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Conclusion
• Experiences on HEP related ASIC design
• Focusing on three types of detectors readout of interests
• Also interested on advanced techniques
– High speed waveform sampling
– Advance packaging
– A/D, PLL/DLL, high speed serializer…
• Most of the staff have experiences of international
collaboration
20
Thank you！
International collaboration activities
• ATLAS silicon pixel detector upgrade
– With CPPM, France on 3D Pixel ASIC readout design
– With LBNL, USA on 65nm FE-I5 chip design and test
• LHAASO PMT readout chip design, with Omega of In2p3,
France
– On PARISROC v1,v2 readout chip design
• High speed digital design with SMU, USA
– On LASER driver chip design on 65nm
– On high speed serializer chip design
• Frontend readout ASICs with Institutes of INFN, Italy
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Several Collaboration Work
PMT Readout ASIC: PARISROC v1, v2 with Omega of IN2P3, France
Co-designed Pixel Chip FEC4_P3 with CPPM, measurement environment & results
Work in ATLAS Pixel Detector Upgrade Collaboration
• Since 2008 with CPPM, LBNL, 6 people involved for more than 4
years in total
• Design and research work:
– Irradiation test environment development and setup
– Building blocks design and measurement
 Low power pixel cell, analog buffer, on-chip calibration pulse generator, lowvoltage current reference…
– Full chip simulation and verification
 Full chip functional verification
 Full chip power network and uniformity verification
– Chip layout, floorplan, &measurement
• Still involved through the regular phone-meeting every week
• Now we are trying to find a good candidate foundry of HV- HRCMOS technology in China
– Visited SMIC foundry in Shanghai several times
– Now a three-party NDA is signing
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Some work in ATLAS Pixel Detector
Control room
Synchronization signals
from the machine
USB
link
DE2 board
Irradiation zone
LVDS to LVTTL translator
LVDS signals
Intermediate board
~20 meters
Irradiated
Sample
In the beam
Single ended
~4 meters
Outside the beam
Power Supply
Design, debugging, layout
Irradiation test environment development & setup
Building blocks design, simulation and tapeout
Full chip simulation, verification and
debugging
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计数率和光斑不均匀性
1
2
3
移动前
4
将母板承接平台进行微调，试图验证入射光斑的非均匀性
左侧两图分别为移动前、后的计数率响应，其他入射条件
均不变
可见对应像素的计数率如预期发生了变化
另外，2、3、4三个之前计数相近的像素在移动位置后计
数依然接近，从实际打线像素的位置也可以看到，三
个像素是空间靠近的
这一方面证明了入射光斑的非均匀性，另一方面也验证了
阵列计数是接收的实际光斑
这也再次说明更精确计数/丢数测试需要精确准直和获知入
射粒子数
1
移动后
3
2
4