n inputs
⭈⭈
⭈
Combinational
circuit
⭈⭈
⭈
m outputs
Fig. 4-1 Block Diagram of Combinational Circuit
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
A
B
C
T2
A
B
C
T1
F1
T3
F⬘2
A
B
A
F2
C
B
C
Fig. 4-2 Logic Diagram for Analysis Example
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
AB
CD
00
00
01
C
C
10
AB
CD
00
1
1
00
1
1
1
1
01
1
1
01
11
01
11
10
B
11
X
X
X
B
X
A
11
X
10
1
X
X
X
X
X
A
10
1
X
X
D
z D
AB
CD
00
00
01
D
y CD CD
C
01
11
10
AB
1
1
1
00
CD
00
01
1
C
01
11
10
1
1
1
B
11
X
X
X
X
A
X
X
X
X
10
1
1
X
X
A
10
1
X
X
D
X BC BD BCD
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
11
D
w A BC BD
Fig. 4-3 Maps for BCD to Excess-3 Code Converter
B
D⬘
D
C
z
CD
y
(C ⫹D)⬘
C ⫹D
B
x
w
A
Fig. 4-4 Logic Diagram for BCD to Excess-3 Code Converter
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
x
y
S
x
x
y
y
x
S
C
C
y
(a) S xy xy
C xy
Fig. 4-5 Implementation of Half-Adder
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
(b) S x y
C xy
x
yz
00
1
11
01
1
0
x
y
10
x
1
1
1
yz
00
y
11
01
1
0
x
1
10
1
1
1
z
z
S xyz xyz xyz xyz
S xy xz yz
xy xyz xyz
Fig. 4-6 Maps for Full Adder
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
x⬘
y⬘
z
x
y
x⬘
y
z⬘
x
S
x
y⬘
z⬘
z
y
x
y
z
z
Fig. 4-7 Implementation of Full Adder in Sum of Products
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
C
x
y
S
C
z
Fig. 4-8 Implementation of Full Adder with Two Half Adders and an OR Gate
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
B3
A3
FA
C4
S3
B2
C3
A2
FA
S2
B1
C2
A1
FA
S1
Fig. 4-9 4-Bit Adder
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
B0
C1
A0
FA
S0
C0
Ai
Pi
Bi
Si
Gi
Ci
Fig. 4-10 Full Adder with P and G Shown
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
Ci ⫹ 1
C3
P2
G2
C2
P1
G1
C1
P0
G0
C0
Fig. 4-11 Logic Diagram of Carry Lookahead Generator
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
C4
B3
A3
P3
P3
C3
G3
B2
A2
C4
P2
P2
C2
G2
S3
S2
Carry
Look ahead
B1
A1
P1
generator
P1
C1
S1
G1
B0
A0
P0
P0
G0
C0
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
C0
Fig. 4-12 4-Bit Adder with Carry Lookahead
S0
B3
A3
B2
A2
B1
A1
B0
A0
M
C4
C
V
FA
S3
C3
FA
S2
C2
FA
S1
Fig. 4-13 4-Bit Adder Subtractor
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
C1
FA
S0
C0
Addend
Carry
out
K
Augend
4- bit binary adder
Z8
Z4
Z2
Z1
Output
carry
0
4- bit binary adder
S8
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
S4
S2
S1
Fig. 4-14 Block Diagram of a BCD Adder
Carry
in
C3
B1
B0
A1
A0
A0B1
A 0B 0
A1B1
A1B0
C2
C1
C0
A0
A1
B1
B1
B0
HA
HA
C3 C2
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
Fig. 4-15 2-Bit by 2-Bit Binary Multiplier
C1
B0
C0
A0
B3
A1
B3
B2
B1
B2
B1
B0
B0
0
Addend
Augend
4-bit adder
Sum and output carry
A2
B3
B2
B1
B0
Augend
Addend
4-bit adder
Sum and output carry
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
C6
C5
C4
C3
C2
C1
Fig. 4-16 4-Bit by 3-Bit Binary Multiplier
C0
A3
x3
B3
A2
x2
B2
(A ⬍ B)
A1
x1
B1
A0
x0
(A ⬎ B)
B0
(A ⫽ B)
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
Fig. 4-17 4-Bit Magnitude Comparator
D 0 xyz
D 1 xyz
z
D 2 xyz
y
D 3 xyz
D 4 xyz
x
D 5 xyz
D 6 xyz
D 7 xyz
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
Fig. 4-18 3-to-8-Line Decoder
D0
D1
A
D2
B
E
A
B
1
0
0
0
0
X
0
0
1
1
X
0
1
0
1
D0 D1 D2 D3
1
0
1
1
1
1
1
0
1
1
D3
E
(a) Logic diagram
Fig. 4-19 2-to-4-Line Decoder with Enable Input
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
(b) Truth table
1
1
1
0
1
1
1
1
1
0
x
y
38
decoder
z
E
D 0 to D 7
w
38
decoder
D 8 to D 15
E
Fig. 4-20 4 16 Decoder Constructed with Two 3 8 Decoders
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
0
1
x
22
y
21
z
20
2
3⫻8
decoder
3
4
5
6
7
Fig. 4-21 Implementation of a Full Adder with a Decoder
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
S
C
D2
00
D2
00
01
11
10
X
1
1
1
1
1
1
01
00
01
11
10
00
X
1
1
1
01
1
1
1
1
D1
1
11
1
D1
1
D0
11
1
1
1
1
1
1
1
D0
10
1
1
1
10
D3
D3
x D2 D 3
y D3 D1D2
Fig. 4-22 Maps for a Priority Encoder
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
D3
y
D2
D1
x
V
D0
Fig. 4-23 4-Input Priority Encoder
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
I0
I0
0
MUX
Y
I1
I1
S
1
S
(a) Logic diagram
(b) Block diagram
Fig. 4-24 2-to-1-Line Multiplexer
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
Y
I0
I1
s1
s0
Y
0
0
1
1
0
1
0
1
I0
I1
I2
I3
Y
(b) Function table
I2
I3
s1
s0
(a) Logic diagram
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
Fig. 4-25 4-to-1-Line Multiplexer
A0
Y0
A1
Y1
A2
Y2
A3
Y3
B0
Function table
B1
B2
E
1
0
0
B3
S
(select)
E
(enable)
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
Fig. 4-26 Quadruple 2-to-1-Line Multiplexer
S
X
0
1
Output Y
all 0's
select A
select B
4 ⫻ 1 MUX
x
0
0
0
0
1
1
1
1
y
0
0
1
1
0
0
1
1
z
0
1
0
1
0
1
0
1
F
0
1
1
0
0
0
1
1
F⫽z
F ⫽ z⬘
F⫽0
y
S0
x
S1
z
0
z⬘
1
0
2
1
3
F⫽1
(a) Truth table
(b) Multiplexer implementation
Fig. 4-27 Implementing a Boolean Function with a Multiplexer
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
F
A
B
C
D
F
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
1
1
1
1
1
8 ⫻ 1 MUX
F⫽D
F⫽D
F ⫽ D⬘
C
S0
B
A
S1
D
0
1
2
F⫽0
F⫽0
0
F⫽D
F⫽1
S2
3
4
5
1
6
7
F⫽1
Fig. 4-28 Implementing a 4-Input Function with a Multiplexer
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
F
Normal input A
Output Y A if C 1
High–impedance if C 0
Control input C
Fig. 4-29 Graphic Symbol for a Three-State Buffer
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
I0
Y
I1
I2
A
Y
I3
Select
B
S1
S0
Enable
Select
(a) 2-to-1- line mux
EN
0
2⫻4
decoder
1
2
3
(b) 4 - to - 1 line mux
Fig. 4-30 Multiplexers with Three-State Gates
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
in
out
control
in
control
bufifl
in
bufif0
out
control
in
out
control
notifl
notif0
Fig. 4-31 Three-State Gates
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
out
out
A
B
select
Fig. 4-32 2-to-1-Line Multiplexer with Three-State Buffers
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
Stimulus module
Design module
module testcircuit
reg TA, TB;
wire TC;
module circuit (A, B, C);
input A, B;
output C;
circuit cr (TA, TB, TC);
Fig. 4-33 Stimulus and Design Modules Interaction
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
A
B
C
T3
T1
F1
T2
T4
D
F2
Fig. P4-1
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
A
F
B
C
G
D
Fig. P4-2
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
a
f
g
b
b
e
d
c
(a) Segment designation
c
(b) Numerical designation for display
Fig. P4-9
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
C1
B0
S0
A0
C0
Fig. P4-17 First Stage of a Parallel Adder
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.