Prince Mohammad Bin Fahd University
COEN 3323: Digital Systems
Assignment#3
LOGIC GATES
AlJohara Al Whamaid
200800085
Question1: Consider the timing diagram shown in Fig. 3-80. Label the five
waveforms A, B, C, D and E from top to bottom.
Answer:
a. Show the output waveform if signals B, C and E are input to a NAND gate.
NAND output
b. Show the output waveform if signals A, B and D are input to a NOR gate.
NOR output
c. Show the output waveform if signals A and E are input to an Exclusive-OR
gate.
Exclusive-OR
output
Question2: Gate A has tPLH=tPHL=15 ns. Gate B has tPLH=tPHL=9 ns. Which gate can
be operated at a higher frequency? Why?
Answer:
Gate B has shorter propagating delay time which means higher speed circuit and
higher frequency at which it can operate.
Question4: In a certain automated manufacturing process, electrical components are
automatically inserted in a PC board. Before the insertion tool is activated, the PC board
must be properly positioned, and the component to be inserted must be in the chamber.
Each of these prerequisite conditions is indicated by a LOW voltage. The insertion tool
requires a HIGH voltage to activate it. Design a circuit to implement this process.
Answer:
Question5: Assume that the enable signal in Fig. 3-16 has the waveform shown in Fig.
3-93. Assume that waveform B is also available. Your task is to devise a circuit that will
produce an active-LOW reset pulse to the counter only during the time that the enable
signal is LOW. First, show how a Negative-OR gate can be used in the design of your
circuit. Then, devise an equivalent circuit that uses a Negative-AND gate.
Answer: