Serial Synchronous Counter
Modular Cell
Basic Model
1
>
Clk
T
>
Q
Q
>
Q
Q
Q0
Hernâni Mergulhão 2014
T
T
>
Q
Q
Q1
>
T
>
Q
Q
Q2
>
T
>
Q
Q
Q
i
T
>
Q
Q
Qn-2
Qn-1
Serial Synchronous Counter
Modular Cell
(T>)
(>T)
T
SET
Q
[ Clk ]
Q
CLR
Qi
Basic Model
1
Clk
>
T
>
Q
Q
>
Q
Q
Q0
Hernâni Mergulhão 2014
T
T
> >
Q
Q
Q1
T
>
Q
Q
Q2
>
T
>
Q
Q
Qi
T
>
Q
Q
Qn-2
Qn-1
Serial Synchronous Counter
Modular Cell
(>T)
T
SET
Q
1
(T>)
[ Clk ]
Y
Q
CLR
0 S
[ Up / Down ]
Qi
Basic Model
1
Clk
>
T
>
Q
Q
>
Q
Q
Q0
Hernâni Mergulhão 2014
T
T
> >
Q
Q
Q1
T
>
Q
Q
Q2
>
T
>
Q
Q
Qi
T
>
Q
Q
Qn-2
Qn-1
Serial Synchronous Counter
Modular Cell
Di
D-type input
(>T)
1
Y
0 S
[ Count / Load ]
T
SET
Q
1
(T>)
[ Clk ]
Y
Q
CLR
0 S
[ Up / Down ]
Qi
Basic Model
1
Clk
>
T
>
Q
Q
>
Q
Q
Q0
Hernâni Mergulhão 2014
T
T
> >
Q
Q
Q1
T
>
Q
Q
Q2
>
T
>
Q
Q
Qi
T
>
Q
Q
Qn-2
Qn-1
Serial Synchronous Counter
Modular Cell
Di
[ Clear ]
D-type input
(>T)
1
Y
0 S
[ Count / Load ]
T
SET
Q
1
(T>)
[ Clk ]
Y
Q
CLR
0 S
[ Up / Down ]
Qi
Basic Model
1
Clk
>
T
>
Q
Q
>
Q
Q
Q0
Hernâni Mergulhão 2014
T
T
> >
Q
Q
Q1
T
>
Q
Q
Q2
>
T
>
Q
Q
Qi
T
>
Q
Q
Qn-2
Qn-1
Serial Synchronous Counter
Modular Cell
Di
[ Clear ]
D-type input
(>T)
1
Y
0 S
[ Count / Load ]
T
SET
Q
1
(T>)
[ Clk ]
Y
Q
CLR
0 S
[ Up / Down ]
Qi
Basic Model
1
Clk
>
T
>
Q
Q
>
Q
Q
Q0
Hernâni Mergulhão 2014
T
T
> >
Q
Q
Q1
T
>
Q
Q
Q2
>
T
>
Q
Q
Qi
T
>
Q
Q
Qn-2
Qn-1
Serial Synchronous Counter
Modular Cell
Di
[ Clear ]
(>T)
1
Y
0 S
[ Count / Load ]
[ Clk_Enable ]
T
SET
Q
1
(T>)
[ Clk ]
Y
Q
CLR
0 S
[ Up / Down ]
Qi
Basic Model
1
Clk
>
T
>
Q
Q
>
Q
Q
Q0
Hernâni Mergulhão 2014
T
T
> >
Q
Q
Q1
T
>
Q
Q
Q2
>
T
>
Q
Q
Qi
T
>
Q
Q
Qn-2
Qn-1
Serial Synchronous Counter
Modular Cell
Di
[ Clear ]
[ Count_Enable ]
(>T)
1
Y
0 S
[ Count / Load ]
[ Clk_Enable ]
T
SET
Q
1
(T>)
[ Clk ]
Y
Q
CLR
0 S
[ Up / Down ]
Qi
Basic Model
1
Clk
>
T
>
Q
Q
>
Q
Q
Q0
Hernâni Mergulhão 2014
T
T
> >
Q
Q
Q1
T
>
Q
Q
Q2
>
T
>
Q
Q
Qi
T
>
Q
Q
Qn-2
Qn-1
Serial Synchronous Counter
Modular Cell
Di
[ Clear ]
[ Count_Enable ]
(>T)
1
Y
0 S
[ Count / Load ]
[ Clk_Enable ]
T
SET
Q
1
(T>)
[ Clk ]
Y
Q
CLR
0 S
[ Up / Down ]
{ Reset }
Qi
Basic Model
1
Clk
>
T
>
Q
Q
>
Q
Q
Q0
Hernâni Mergulhão 2014
T
T
> >
Q
Q
Q1
T
>
Q
Q
Q2
>
T
>
Q
Q
Qi
T
>
Q
Q
Qn-2
Qn-1
Di
{ Parallel_Load }
I
S 0
[ Clear ]
[ Count_Enable ]
Serial Synchronous Counter
Modular Cell
1
(>T)
1
Y
0 S
[ Count / Load ]
[ Clk_Enable ]
T
SET
Q
1
(T>)
[ Clk ]
Y
Q
CLR
0 S
[ Up / Down ]
Qi
Basic Model
1
Clk
>
T
>
Q
Q
>
Q
Q
Q0
Hernâni Mergulhão 2014
T
T
> >
Q
Q
Q1
T
>
Q
Q
Q2
>
T
>
Q
Q
Qi
T
>
Q
Q
Qn-2
Qn-1
Di
{ Parallel_Load }
I
S 0
[ Clear ]
[ Count_Enable ]
Serial Synchronous Counter
Modular Cell
1
(>T)
1
Y
0 S
[ Count / Load ]
[ Clk_Enable ]
T
SET
Q
1
(T>)
[ Clk ]
Y
Q
CLR
0 S
[ Up / Down ]
{ Reset }
Qi
Basic Model
1
Clk
>
T
>
Q
Q
>
Q
Q
Q0
Hernâni Mergulhão 2014
T
T
> >
Q
Q
Q1
T
>
Q
Q
Q2
>
T
>
Q
Q
Qi
T
>
Q
Q
Qn-2
Qn-1
Di
Serial Synchronous Counter
Modular Cell
1
{ Parallel_Load }
I
S 0
[ Clear ]
Most Significant Bit
[ Count_Enable ]
(>T)
1
Y
0 S
[ Count / Load ]
[ Clk_Enable ]
T
SET
Q
1
(T>)
[ Clk ]
Terminal_Count
Y
Q
CLR
0 S
[ Up / Down ]
{ Reset }
Qi
Basic Model
1
Clk
>
T
>
Q
Q
>
Q
Q
Q0
Hernâni Mergulhão 2014
T
T
> >
Q
Q
Q1
T
>
Q
Q
Q2
>
T
>
Q
Q
Qi
T
>
Q
Q
Qn-2
Qn-1
Di
Serial Synchronous Counter
Modular Cell
1
{ Parallel_Load }
I
S 0
[ Clear ]
Most Significant Bit
[ Count_Enable ]
(>T)
1
Y
0 S
[ Count / Load ]
[ Clk_Enable ]
T
SET
Q
1
(T>)
[ Clk ]
Terminal_Count
Y
Q
CLR
0 S
[ Up / Down ]
{ Reset }
Qi
Basic Model
1
Clk
>
T
>
Q
Q
>
Q
Q
Q0
Hernâni Mergulhão 2014
T
T
> >
Q
Q
Q1
T
>
Q
Q
Q2
>
T
>
Q
Q
Qi
T
>
Q
Q
Qn-2
Qn-1
Di
Serial Synchronous Counter
Modular Cell
1
{ Parallel_Load }
I
S 0
[ Clear ]
Most Significant Bit
[ Count_Enable ]
(>T)
1
Y
0 S
[ Count / Load ]
[ Clk_Enable ]
T
SET
Q
1
(T>)
[ Clk ]
Terminal_Count
Y
Q
CLR
0 S
[ Up / Down ]
{ Reset }
Max/min
Clk
Qi
Basic Model
1
Clk
>
T
>
Q
Q
>
Q
Q
Q0
Hernâni Mergulhão 2014
T
T
> >
Q
Q
Q1
T
>
Q
Q
Q2
>
T
>
Q
Q
Qi
T
>
Q
Q
Qn-2
Qn-1
Di
Serial Synchronous Counter
Modular Cell
1
{ Parallel_Load }
I
S 0
[ Clear ]
Most Significant Bit
[ Count_Enable ]
(>T)
1
Y
0 S
[ Count / Load ]
[ Clk_Enable ]
T
SET
Q
1
(T>)
[ Clk ]
Terminal_Count
Y
Q
CLR
0 S
[ Up / Down ]
{ Reset }
Max/min
Clk
Qi
Basic Model
1
Clk
>
T
>
Q
Q
>
Q
Q
Q0
Hernâni Mergulhão 2014
T
T
> >
Q
Q
Q1
T
>
Q
Q
Q2
>
T
>
Q
Q
Qi
T
>
Q
Q
Qn-2
Qn-1
Di
Serial Synchronous Counter
Modular Cell
1
{ Parallel_Load }
I
S 0
[ Clear ]
Most Significant Bit
[ Count_Enable ]
(>T)
1
Y
Terminal_Count
0 S
[ Count / Load ]
[ Clk_Enable ]
T
SET
Q
1
(T>)
[ Clk ]
I
Y
Q
CLR
TC_Up
1
TC_Down
S 0
0 S
[ Up / Down ]
{ Reset }
Qi
Basic Model
1
Clk
>
T
>
Q
Q
>
Q
Q
Q0
Hernâni Mergulhão 2014
T
T
> >
Q
Q
Q1
T
>
Q
Q
Q2
>
T
>
Q
Q
Qi
T
>
Q
Q
Qn-2
Qn-1
Di
Serial Synchronous Counter
Modular Cell
1
{ Parallel_Load }
I
S 0
[ Clear ]
Most Significant Bit
[ Count_Enable ]
(>T)
1
Y
Terminal_Count
0 S
[ Count / Load ]
[ Clk_Enable ]
T
SET
Q
1
(T>)
[ Clk ]
I
Y
Q
CLR
TC_Up
1
TC_Down
S 0
0 S
Max/min
[ Up / Down ]
Carry
{ Reset }
Borrow
Clk
Qi
Basic Model
1
Clk
>
T
>
Q
Q
>
Q
Q
Q0
Hernâni Mergulhão 2014
T
T
> >
Q
Q
Q1
T
>
Q
Q
Q2
>
T
>
Q
Q
Qi
T
>
Q
Q
Qn-2
Qn-1
Di
Serial Synchronous Counter
Modular Cell
1
{ Parallel_Load }
I
S 0
[ Clear ]
Most Significant Bit
[ Count_Enable ]
(>T)
1
Y
Terminal_Count
0 S
[ Count / Load ]
[ Clk_Enable ]
T
SET
Q
1
(T>)
[ Clk ]
I
Y
Q
CLR
TC_Up
1
TC_Down
S 0
0 S
Max/min
[ Up / Down ]
Carry
{ Reset }
Borrow
Clk
Qi
[ xxx ] : shared synchronous signal
{ xxx } : shared asynchronous signal
( > x ) : input signal for concatenation
( x > ) : output signal for concatenation
xxx
: individual signal (specific for each cell)
Hernâni Mergulhão 2014
Basic Model
1
Clk
>
T
>
Q
Q
T
>
Q
Q
Q0
T
> >
Q
Q
Q1
T
>
Q
Q
Q2
>
T
>
Q
Q
Qi
T
>
Q
Q
Qn-2
Qn-1
Di
Serial Synchronous Counter
Modular Cell
1
{ Parallel_Load }
I
S 0
[ Clear ]
Most Significant Bit
[ Count_Enable ]
(>T)
1
Y
Terminal_Count
0 S
[ Count / Load ]
[ Clk_Enable ]
T
SET
Q
1
(T>)
[ Clk ]
I
Y
Q
CLR
TC_Up
1
TC_Down
S 0
0 S
Max/min
[ Up / Down ]
Carry
{ Reset }
Borrow
Clk
Qi
[ xxx ] : shared synchronous signal
{ xxx } : shared asynchronous signal
( > x ) : input signal for concatenation
( x > ) : output signal for concatenation
xxx
: individual signal (specific for each cell)
Hernâni Mergulhão 2014
Basic Model
1
Clk
>
T
>
Q
Q
T
>
Q
Q
Q0
T
> >
Q
Q
Q1
T
>
Q
Q
Q2
>
T
>
Q
Q
Qi
T
>
Q
Q
Qn-2
Qn-1
Di
Serial Synchronous Counter
Modular Cell
1
{ Parallel_Load }
I
S 0
[ Clear ]
Most Significant Bit
[ Count_Enable ]
(>T)
1
Y
Terminal_Count
0 S
[ Count / Load ]
[ Clk_Enable ]
T
SET
Q
1
(T>)
[ Clk ]
I
Y
Q
CLR
TC_Up
1
TC_Down
S 0
0 S
Max/min
[ Up / Down ]
Carry
{ Reset }
Borrow
Clk
Qi
[ xxx ] : shared synchronous signal
{ xxx } : shared asynchronous signal
( > x ) : input signal for concatenation
( x > ) : output signal for concatenation
xxx
: individual signal (specific for each cell)
Hernâni Mergulhão 2014
Basic Model
1
Clk
>
T
>
Q
Q
T
>
Q
Q
Q0
T
> >
Q
Q
Q1
T
>
Q
Q
Q2
>
T
>
Q
Q
Qi
T
>
Q
Q
Qn-2
Qn-1
Di
Serial Synchronous Counter
Modular Cell
1
{ Parallel_Load }
I
S 0
[ Clear ]
Most Significant Bit
[ Count_Enable ]
(>T)
1
Y
Terminal_Count
0 S
[ Count / Load ]
[ Clk_Enable ]
T
SET
Q
1
(T>)
[ Clk ]
I
Y
Q
CLR
TC_Up
1
TC_Down
S 0
0 S
Max/min
[ Up / Down ]
Carry
{ Reset }
Borrow
Clk
Qi
[ xxx ] : shared synchronous signal
{ xxx } : shared asynchronous signal
( > x ) : input signal for concatenation
( x > ) : output signal for concatenation
xxx
: individual signal (specific for each cell)
Hernâni Mergulhão 2014
Basic Model
1
Clk
>
T
>
Q
Q
T
>
Q
Q
Q0
T
> >
Q
Q
Q1
T
>
Q
Q
Q2
>
T
>
Q
Q
Qi
T
>
Q
Q
Qn-2
Qn-1
Di
Serial Synchronous Counter
Modular Cell
1
{ Parallel_Load }
I
S 0
[ Clear ]
D-type input
Most Significant Bit
[ Count_Enable ]
(>T)
1
Y
Terminal_Count
0 S
[ Count / Load ]
[ Clk_Enable ]
T
SET
Q
1
(T>)
[ Clk ]
I
Y
Q
CLR
TC_Up
1
TC_Down
S 0
0 S
Max/min
[ Up / Down ]
Carry
{ Reset }
Borrow
Clk
Qi
[ xxx ] : shared synchronous signal
{ xxx } : shared asynchronous signal
( > x ) : input signal for concatenation
( x > ) : output signal for concatenation
xxx
: individual signal (specific for each cell)
Hernâni Mergulhão 2014
Basic Model
1
Clk
>
T
>
Q
Q
T
>
Q
Q
Q0
T
> >
Q
Q
Q1
T
>
Q
Q
Q2
>
T
>
Q
Q
Qi
T
>
Q
Q
Qn-2
Qn-1
Di
Serial Synchronous Counter
Modular Cell
1
{ Parallel_Load }
I
S 0
[ Clear ]
D-type input
Most Significant Bit
[ Count_Enable ]
(>T)
1
Y
Terminal_Count
0 S
[ Count / Load ]
[ Clk_Enable ]
T
SET
Q
1
(T>)
[ Clk ]
I
Y
Q
CLR
TC_Up
1
TC_Down
S 0
0 S
Max/min
[ Up / Down ]
Carry
{ Reset }
Borrow
Clk
Qi
[ xxx ] : shared synchronous signal
{ xxx } : shared asynchronous signal
( > x ) : input signal for concatenation
( x > ) : output signal for concatenation
xxx
: individual signal (specific for each cell)
Hernâni Mergulhão 2014
Basic Model
1
Clk
>
T
>
Q
Q
T
>
Q
Q
Q0
T
> >
Q
Q
Q1
T
>
Q
Q
Q2
>
T
>
Q
Q
Qi
T
>
Q
Q
Qn-2
Qn-1