FPGA Implementation of H.264
Video Encoder
-BY KUSHAL KUNIGAL UNDER GUIDANCE OF
DR. K.R.RAO.
SPRING 2011,
ELECTRICAL ENGINEERING DEPARTMENT,
UNIVERSITY OF TEXAS AT ARLINGTON
Proposal
 This project is based on the implementation of
H.264 video encoder and the algorithms for
evaluating the Transform and quantization suitable
for high speed implementation on FPGA/ASIC.
Overview
Overview:
To achieve a real-time H.264 encoding solution,
multiple FPGAs and programmable DSPs are
often used[3]. The computational complexity
alone does not determine if a functional module
should be mapped to hardware or remain in
software.
Architectural issues
Fig 1: H.264 encoder block diagram [2].
Architectural issues
 Data Locality: In a synchronous design, the ability
to access memory in a particular order and
granularity while minimizing the number of clock
cycles due to latency, bus contention, alignment,
DMA transfer rate and the types of memory used is
very important. The data locality issue (Figure 1) is
primarily dictated by the physical interfaces between
the data unit and the arithmetic unit (or the
processing engine) [2].
Architectural issues
Computational Complexity: Programmable DSPs
are bounded in computational complexity, as
measured by the clock rate of the processor. Signal
processing algorithms implemented in the FPGA fabric
are typically computationally-intensive. By mapping
these modules onto the FPGA fabric, the host
processor or the programmable DSP has the extra
cycles for other algorithms. Furthermore, FPGAs can
have multiple clock domains in the fabric, so selective
hardware blocks can have separate clock speeds based
on their computational requirements [2].
Modules in H.264 video encoder
Fig 2: Modules in H.264 video encoder [3].
Prediction modes in H.264 standard
Fig 3a: Mode 0: vertical
Fig 3c: Mode 2: DC
Fig 3b: Mode 1: horizontal
Prediction modes in H.264 standard
Fig 3d: Mode 3: diagonal down-left
Fig 3f: Mode 5: vertical-right
Fig 3e: Mode 4: diagonal down-right
Fig 3g: Mode 6: horizontal-down
Prediction modes in H.264 standard
Fig 3h: Mode 7: vertical-left
Fig 3i: Mode 8: horizontal-up
Concept
 By understanding the ideas and importance behind
video compression, it is possible to use the idea and
implement an efficient and high performance
encoder, such that it consumes less power and take
less clock cycles to encode an image frame. The
implementation is considered a lite version of the
H.264 encoder, similar to the MPEG-4 digital video
codec which is known to achieving high data
compression. The same building blocks implemented
in the H.264 encoder will be used in this simple
version with exceptions of a few optimizing
modifications.
Future work
Future work:
Going forward, the motion estimation algorithm will
be analyzed from the hardware perspective along with
the other modules of the encoder.
Websites and References
[1] T. Wiegand, G. J. Sullivan, G. Bjøntegaard, and A. Luthra “Overview of the
H.264/AVC Video Coding Standard”, IEEE Trans. on Circuits and Systems for
Video Technology vol. 13, no. 7, pp.560–576, July 2003.
[2]Data locality description:
http://www.eetimes.com/design/embedded/4007043/How-to-map-the-H264-AVC-video-standard-onto-an-FPGA-fabric.
[3] N. Keshaveni, S. Ramachandran, K. S. Gurumurthy “Design and FPGA
Implementation of Integer Transform and Quantization Processor and Their
Inverses for H.264 Video Encoder”, Advances in Computing, Control, &
Telecommunication Technologies, 2009. ACT 2009. International
Conference on, pp. 646-649, July 2009
[4] I. Richardson, “The H.264 advanced video compression standard”, Wiley,
2nd edition, 2010.
Websites and References
[5] DSP-Enabled efficient motion estimation for Mobile MPEG-4 video
encoding- http://www.techonline.com/community/21066.
[6] T. Wiegand, Gary J. Sullivan, G. Bjontegaard, and A. Luthra,
"Overview of the H.264/AVC Video Coding Standard", IEEE Transactions
on Circuits and Systems for Video Technology, Vol. 13, No. 7, pp. 560-576,
July 2003.
[7] T. Wedi, H. G. Musmann, "Motion- and aliasing-compensated
prediction for hybrid video coding," IEEE Transactions on Circuits and
Systems for Video Technology, Vol. 13, No. 7, pp. 577- 586, July 2003.
Websites and references
[8] H. S. Malvar, A. Hallapuro, M. Karczewicz, L. Kerofsky, "Lowcomplexity transform and quantization in H.264/AVC," IEEE
Transactions on Circuits and Systems for Video Technology, Vol. 13, No.
7, pp. 598- 603, July 2003.