Does Negative Bias Temperature Instability Affect the Soft Error Rate of SRAMs?
M. Bagatin1, S. Gerardin1, A. Paccagnella1, F. Faccio2.
1
2
RREACT Group, Università di Padova, Padova, Italy.
Physics Department, Microelectronics Group, CERN, Geneva, Switzerland.
Padova (Italy) [5].
The samples were then subjected to NBTI stress: high
temperature (125°C) and high voltage (2.5 V), with a fixed
logic checkerboard pattern stored in the cells (stress pattern
‘AA’). At the end of the stress we exposed the memories to
heavy ions. While during the stress the pattern stored in the
cells was always the same (‘AA’), we measured the SEU
rate both with the stress pattern and the complementary
pattern (‘55’). Irradiations and characterization were
performed at room temperature.
We also performed HSPICE simulations of fresh and
aged SRAM cells. The characteristics of aged transistors
were obtained by changing SPICE parameters, using
published data and models [6-8]. The degradation was set
so that the saturation drain current of PMOSFET decreases
by 10% when the PMOS is constantly on for 10 years
(worst-case condition), which is the maximum parameter
drift usually specified by manufacturers.
INTRODUCTION
Integrated circuits operating in space must withstand a
harsh radiation environment [1], but, at the same time, they
are subjected to the same intrinsic degradation mechanisms
that are present on Earth. Aging of MOSFETs is one of the
hottest topics in CMOS research. In fact, due to the ever
increasing electric field, the reliability margin of modern
devices is rapidly decreasing [2]. Negative Bias
Temperature Instability (NBTI), in particular, is considered
one of the most pressing threats nowadays [2]. As the
name suggests, NBTI is active when a negative bias is
applied to an MOS structure (e.g., an ON PMOSFET) at
high temperature. NBTI causes PMOS parameters to
change over time due to trapped charge and interface state
generation. Due to ever increasing concern about wear-out,
several synergetic studies have been carried out to evaluate
possible interactions between radiation effects and aging,
for instance in SRAMs [3] and in Flash memories [4].
In this work we study the implications of NBTI as far as
Single Event Upsets (SEU) are concerned. To this purpose,
we will use a combination of SPICE simulations and
heavy-ion experiments.
RESULTS AND DISCUSSION
We first discuss the simulation results. Figure 1 depicts
the SRAM cell and the simulated combinations of stressed
PMOSFETs and struck nodes we considered in this work.
For simplicity we evaluated only strikes on the OFF
NMOSFET, which is known to be the most sensitive
device. We considered the following scenarios (see fig. 1):
1) The cell stores a fixed pattern for 10 years, the ON
PMOSFET in the cross-coupled inverter pair (P2 in figure
1) is degraded to the maximum level (10%), and the cell
loses its symmetry. Afterwards:
a. the OFF NMOSFET (N2 in figure 1) is struck by the
impinging particle;
EXPERIMENTAL, DEVICES AND SIMULATIONS
For the experimental part of this work we used 16-kbit
SRAMs manufactured in a standard 130-nm CMOS
technology, with supply voltage ranging from 1.25 to
1.5 V. SRAMs were initially electrically characterized.
The SEU rate was assessed on the fresh samples using
heavy ions (LET from 3.16 to 54.7 MeV·cm2/mg) at the
SIRAD line of the Laboratori Nazionali di Legnaro,
WL
WL
P1
fresh
Q
M1
N1
BL
Case
_ 1b)
•Q = 1
•Strike on N1
VDD
P1
aged
P2
aged
M2
M1
Q
N2
Q
N1
BL
BL
VDD
P2
aged
M2
Q
N2
BL
Case 2a)
•Q = 1
•Strike on N2
Case 1a)
•Q = 1
•Strike on N2
Fig. 1. Schematic of a 6-T SRAM cell depicting the NBTI aging and particle strike scenarios analyzed in this paper.
LNL Annual Report
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Appl., Gen. and Interdisc. Phys. Instrumentation
b. the cells is written with the opposite pattern and the
(different) OFF NMOS (N1) is struck;
2) The cell stores ‘0’ for half of the lifetime (5 years),
and ‘1’ for the other half, both the PMOSFETs (P1 and P2)
are degraded to the same level (5%). In this case the cell
remains symmetric. Afterwards:
a. the OFF NMOSFET (N2) is struck.
Figure 3 shows the heavy-ion experimental data. Soft error
measurements were done on fresh samples and after the
whole electrical and temperature stress was delivered to
the device (~150 hours). Error bars for heavy-ion cross
section in figure 3 are smaller than the symbols in the
graph. As seen in the plot, the differences between the
fresh and the stressed devices are small and within the
experimental error, for both the stress pattern ‘AA’ and the
complementary pattern ‘55’. As a result, heavy-ion results
do not contradict the conclusions obtained by means of
simulation.
4%
1.E-07
0%
Bit Cross Section [cm2]
% variation in Qcrit (aged/fresh)
8%
-4%
Q=1, Aged P2, Struck N2
Q=0, Aged P2, Struck N1
Q=1, Aged P1 & P2, Struck N2
-8%
-12%
60
90
120
150
180
210
240
270
1.E-09
Stressed 'AA', Irradiated 'AA'
Stressed 'AA', Irradiated '55'
No stress
1.E-10
Technology node [nm]
0
10
20
30
40
50
60
LET [MeV cm2/mg]
Fig. 2. Simulated percent variation in the critical charge of the
SRAM cell with respect to fresh cell (averaged over several pulse
durations), in the aging and strike scenarios described in figure 1.
Fig. 3. Heavy-ion bit cross section for fresh and stressed samples.
“Stressed ‘AA’, Irradiated ‘AA’” and “Stressed ‘AA’, Irradiated
‘55’” correspond to scenarios 1a) and 1b) in figure 2,
respectively.
Figure 2 shows the variations in the critical charge (Qcrit)
as a function of the cell technology node, for the scenarios
illustrated in figure 1. In some cases Qcrit increases, while
in some others it decreases, but the entity of the changes is
always limited below 8%. Two contrasting factors
contribute to these alterations:
i. the capability of the PMOS to restore the potential at
the struck node is reduced, due the NBTI-induced current
reduction. This has a detrimental effect on the SEU
sensitivity;
ii. the speed of the cell is reduced, which, on the
contrary, improves the SEU sensitivity.
Factor i. is dominant in scenario 1a), causing the critical
charge to decrease; on the other hand, ii. is the driving
factor behind 1b), where the critical charge increases (at
the expense of the cell speed). Finally, in 2a), both factors
are at play and, as a result, the critical charge changes less.
These results are clearly visible in figure 2.
The simulations show that in the stress scenario 1),
NBTI induces a pattern dependence in the SEU sensitivity,
1a) vs 1b). The node to which the degraded PMOS is
connected is more sensitive, because of the lower restoring
current, as just discussed.
Finally, no clear trend is visible in figure 2 concerning
the impact of NBTI on the SEU sensitivity as a function of
the cell feature size.
We now move to the experimental part of this work. We
will focus on scenario 1), since it is the one that should
give the largest variations according to our simulations.
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1.E-08
In conclusion, both simulations and heavy-ion results
show that NBTI degradation does not significantly affect
the soft error rate of SRAM cells in a 130-nm technology,
as long as the parametric drift induced by aging is within
10%. Our simulations point to a moderate increase or
decrease in the critical charge, hence to a moderate
decrease or increase in the soft error tolerance,
respectively, depending on the pattern stored in the
memory during its lifetime. These small variations (< 7%)
are very hard to observe experimentally and, in all the
studied cases, they are within the experimental errors.
According to our findings, neglecting these variations in
single event upset rate calculations is practically of no
consequence. We highlight that the results found in this
work are valid for typical devices with standard operating
voltage, and larger variations may occur with particular
design choices.
[1]
[2]
[3]
[4]
[5]
J.L. Barth et al., IEEE T-NS, 50 (2003) 466.
C. Schlunder, Adv. Radio Sci., 7 (2009) 201.
M.R. Shaneyfelt et al., IEEE T-NS, 44 (1997) 2040.
T.R. Oldham,et al., IEEE T-NS, 56 (2009) 3280.
J. Wyss et al., Nucl. Instr. Meth. Phys. Res., A462 (2001)
426.
[6] K.R. Forbes, P. Schani, IEEE IRPS Proc., (2004) 165.
[7] H. Aono et al., IEEE IRPS Proc., (2004) 23.
[8] M. Denais et al., IEEE T-DMR, 4 (2004) 715.
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