JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.6, DECEMBER, 2016
https://doi.org/10.5573/JSTS.2016.16.6.860
ISSN(Print) 1598-1657
ISSN(Online) 2233-4866
A 285-fsrms Integrated Jitter Injection-Locked Ring PLL
with Charge-Stored Complementary Switch Injection
Technique
Sungwoo Kim, Sungchun Jang, Sung-Yong Cho, Min-Seong Choo, Gyu-Seob Jeong,
Woorham Bae, and Deog-Kyoon Jeong
Abstract—An injection-locked ring phase-locked loop
(ILRPLL) using a charge-stored complementary
switch (CSCS) injection technique is described in this
paper. The ILRPLL exhibits a wider lock range
compared to other conventional ILRPLLs, owing to
the improvement of the injection effect by the
proposed CSCS. A frequency calibration loop and a
device mismatch calibration loop force the frequency
error to be zero to minimize jitter and reference spur.
The prototype chip fabricated in 65-nm CMOS
technology achieves a 285-fsrms integrated jitter at
3.328 GHz from the reference clock of 52 MHz while
consuming 7.16 mW. The figure-of-merit of the
the frequency mismatch fERR between the free-running
fOUT and the injection frequency fREF increases. Second,
the injection lock range fLR becomes narrow for a large
multiplication factor N. In other words, achieving low
jitter becomes more challenging as N increases. To detect
this frequency mismatch, a fine resolution time-to-digital
converter (TDC) is employed in [2] at the cost of
increased power consumption. In addition, using a phase
detector (PD) with a replica delay cell, as proposed in [3],
suffers from the problem of device mismatches.
Moreover, the absence of startup circuits in [2] and [3]
requires the oscillation frequency to be set within the
injection lock range initially. [1] and [3] achieve an
ILRPLL is ‒242.4 dB.
excellent figure-of-merits (FoMs) of less than ‒240 dB
Index Terms—Charge-stored complementary switch
(CSCS), frequency synthesizer, injection-locked
oscillator (ILO), phase-locked loop (PLL)
I. INTRODUCTION
In high-performance clock synthesizers, an injectionlocked oscillator (ILO) has become an attractive solution
because of its superior jitter performance compared to
conventional integer-N phase-locked loops. However, the
ILO commonly suffers from two issues [1]. First, the
phase noise and the spur level performance degrades as
Manuscript received Jun. 8, 2016; accepted Sep. 26, 2016
Inter-University Semiconductor Research Center (ISRC) and the School
of Electrical and Computer Engineering, Seoul National University,
Gwanak-ro, Gwanak-gu, Seoul, Korea (151-59 744)
E-mail : [email protected]
with a small N since achieving the high performance in
ILOs is challenging with a higher N [4]. However,
reducing N is not adequate for practical designs using
crystal oscillators whose operating frequency is often
limited only up to 200 MHz.
In this paper, an injection-locked ring phase-locked
loop (ILRPLL) with N = 64 is presented. The ILRPLL
employs a PLL to initialize the oscillation frequency and
a frequency calibration loop (FCL) for nullifying
frequency mismatch. Additionally, a device mismatch
calibration loop (MCL) runs in the background. A
charge-stored complementary switch (CSCS) injection
technique is proposed as well to achieve a wide lock
range even for a large N.
The remaining parts of this paper is organized as
follows. Section II describes the proposed ILRPLL
architecture. After the experimental results are presented
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.6, DECEMBER, 2016
861
Normal-operation state FCL/MCL
REF
DCC
INJ_P, INJ_N
ILRO
PFD
DLF
Acc. ΔΣ
0
0
ERF 1
FCW
OSC
PLL_DONE
1 ERM
Acc. ΔΣ
MCW
CNT[2]
RST_PLSB
PWC
RSTB
RSTCNT
CNT
CNT[1:0]
CLK_PLSB
UP/DN
RST
CNT
DIV4
EN_PLS
DIV4
ON_PLS
FCW: Frequency Control Word
MCW: Mismatch Control Word
DIV64
Initial state PLL
Fig. 1. Block diagram of the proposed ILRPLL.
in Section III, Section IV concludes the work.
FCW
II. ARCHITECTURE
OSC
OUT
Dummy
INJ_P
The block diagram of the proposed ILRPLL is
illustrated in Fig. 1. It is composed of a phase frequency
detector (PFD), a digital loop filter (DLF), an injectionlocked ring oscillator (ILRO), the FCL, the MCL, and a
duty-cycle corrector (DCC). The ILRO consists of a
pseudo-differential
two-stage
ring-type
digitally
controlled oscillator (DCO) using the merged injection
technique, as shown in Fig. 2. In addition, the DCC
maintains the 50% duty cycle for achieving equally
spaced injection at rising and falling edges.
Fig. 3 shows the operational sequence of the ILRPLL.
At startup, it cannot be assured that fOUT is within fLR due
to relatively narrow fLR compared to the frequency range
of the ILRO under process, supply voltage and
temperature (PVT) variations. To ensure the injection
locking operation, in the initial state, the PLL operates
with the injection, which locks the ILRO. However, with
the PLL locked, PLL_DONE = 1, fOUT is prone to stay
away from the targeted N × fREF, because the PLL cannot
detect the frequency error fERR with the ILRO locked [5].
When PLL_DONE =1, the MCL runs before the FCL
operates so that the device mismatches are minimized.
The device mismatches include the two path mismatches
to the pulse width comparator (PWC), the capacitance/
current mismatches in the PWC. Finally, when the MCW
settles at some value to minimize the device mismatches,
the FCL operates to remove fERR over the PVT variations.
INJ_N
CSCS
OSCB
OUTB
Unit cell
Fig. 2. Schematic of ILRO.
fLR
fOUT
N×fREF
Time
Minimized
mismatch
MCW
Time
PLL ON
MCL OFF
FCL OFF
Startup
Initial
state
OFF
ON
ON
Normal-operation
state
Fig. 3. ILRPLL operation sequence.
1. Charge-stored Complementary Switch Injection
Technique
The lock range analysis proposed in [6] with a phase
domain response (PDR) is valid for both weak and strong
injections. If fERR is nonzero, the injection signal causes
an output phase shift. The lock range is determined by
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SUNGWOO KIM et al : A 285-FSRMS INTEGRATED JITTER INJECTION-LOCKED RING PLL WITH CHARGE-STORED …
producing the suitable injection pulse is challenging [2].
As an alternative to the use of the PG, a complementary
switch (CS) injection technique can be employed [7].
However, it is difficult to obtain a large Ppp because the
injection current flows only during a short transition time.
In order to increase the injection current, the chargestored complementary switch (CSCS) injection technique
is proposed as described in Fig. 4. The charge-storing
capacitor CCS is placed between the center nodes of the
two switches to hold an additional charge. Fig. 5(a)
shows the operation of the CSCS at the transition
moment. When N1 is connected to OSCB, the charge Q
stored in CCS is discharged to OSCB, which makes
OSCB to go the level of OSC. Consequently, it results in
pushing the output phase, as shown in Fig. 5(b). In order
to verify the CSCS, the PDR is determined through
simulation as shown in Fig. 6(a). As shown in Fig. 6(b),
fLR of the CSCS method is proportional to CCS and it
shows about the lock range of 18.92 MHz at CCS = 30 fF,
which is 3 times wider than that of the CS method. In
addition, the measured lock range of prototype chip is
17.25 MHz. As a compromise, the optimum value for
CCS is set to 30 fF to obtain the targeted phase noise
performance with a minimum power overhead. Therefore,
with the aid of the CSCS injection technique, an enhanced
OSC
IC,DC
INJ_P
N1
INJ_N
N2
CCS
INJ_N
INJ_P
OSCB
Fig. 4. Schematic of CSCS.
the range of possible phase shifts: the maximum phase
shift, Pmax, and the minimum phase shift Pmin, while the
ILO maintains in a lock state. Thus, it can be expressed
as
f LR =
f 0 ( Pmax - Pmin )
2p N
=
f 0 Ppp
2p N
,
(1)
where Ppp is the peak-to-peak phase shift of the PDR.
Therefore, the lock range can be maximized by
increasing Ppp and decreasing N. If the reference signals
are injected at both rising and falling edges, it brings an
effect of halving the N.
A single switch injection technique shorting the
differential clock signals is generally employed.
Nonetheless, the design of the pulse generator (PG)
OSC: '1'
INJ_P
N1
OSC: '1'
INJ_P
INJ_N
Q
INJ_N
INJ_P
N1
N2
CCS
INJ_N
Q
INJ_N
N2
CCS
INJ_P
INJ_N
OSCB: '0'
INJ_P
OSCB: '0'
(a)
INJ_P
INJ_N
OSC
OSCB
N1
N2
IC,DC
fERR = 0
fERR < 0, pulling phase
(b)
Fig. 5. CSCS injection technique (a) operation, (b) timing diagram.
fERR > 0, pushing phase
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.6, DECEMBER, 2016
60
20
35
Lock range [MHz]
Phase shift [°]
40
No CCS
10 fF
30 fF
50 fF
40
0
Ppp
-20
-40
-60
-80
-110
863
30
25
20
Measured
lock range
15
10
5
-70
-30
10
50
90
0
0
10
Input phase [°]
20
30
40
50
60
CCS [fF]
(a)
(b)
Fig. 6. (a) PDR, (b) calculated lock range.
REF
RSTB
RSTCNT
INJ_P
Pulling OSC
phase
Half Period
OSC
DIV4
CNT[2:0]
0
1
2
3
4
5
6
7
0
EN_PLS
ON_PLS
CLK_PLSB
RST_PLSB
VEN
VON
UP/DN
Frequency Error UP (ERF)
Mismatch Error UP (ERM)
Fig. 7. Timing diagram of FCL and MCL.
lock range can be achieved.
2. Frequency/Mismatch Calibration Loop
The key concept of detecting fERR in [2] is based on the
phenomenon that the pulse-width difference is
proportional to fERR when the reference clock is injected
into the oscillator. By comparing the two pulse widths,
fERR can be detected and compensated. Our approach is to
simply detect the polarity of fERR using a PD, as in [3]
and [8], which eliminates the use of a power-hungry
TDC. However, the PD alone cannot compare two
successive pulses simultaneously and it suffers from the
offset issues.
As a remedy, the PWC converts the pulse width into
voltage and detects the polarity of fERR [8]. The illustrative
timing diagram of the FCL and the MCL operation and
the detailed implementation of the PWC are shown in Fig.
7 and 8, respectively. The PWC generates the up/down
signal UP/DN by comparing EN_PLS and ON_PLS,
which are generated from the divided-by-4 clock DIV4.
The dividing factor of 4 is chosen to allow a sufficient
time-to-voltage conversion gain and a low power
operation. The counter (CNT) identifies the pulse width
and RSTCNT that are generated from the external reset
RSTB, and resets CNT to 0 before the rising edge of
INJ_P. The pulse width of EN_PLS in CNT = 0 is
proportional to fERR and the width of ON_PLS in CNT = 1
represents the oscillator’s free-running frequency.
Detecting fERR is performed every half period of REF.
Injecting at both rising and falling edges has the effect of
halving N. It is important to note that nonzero value of
fERR makes the EN_PLS in CNT = 0 deviate from the
ON_PLS in CNT = 1, and consequently, the PWC
generates a polarity of difference. After the PWC makes
the decision at rising edge of CLK_PLSB, the VEN and
VON are reset at rising edge of RST_PLSB. Then, 1-bit
information of the fERR is delivered to the DLF.
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SUNGWOO KIM et al : A 285-FSRMS INTEGRATED JITTER INJECTION-LOCKED RING PLL WITH CHARGE-STORED …
MCW
EN_PLS
ON_PLS
VEN
UP/DN
RST_PLSB
VON
CLK_PLSB
Fig. 8. Schematic of PWC.
Block
Power [mW]
ILRO
4.86
DLF
0.68
310um
I2C&DLF
210um
80um
ILRO
PWC
140um
110um
140um
Fig. 10. Measured phase noise.
DCC
PWC,DCC,
DIV, PFD
Total
−40.34dBc
1.62
7.16
Fig. 9. Chip photomicrograph and power breakdown.
Furthermore, both the pulse widths of EN_PLS in
CNT = 4 and ON_PLS in CNT = 5 refers to the
oscillator’s free-running frequency. Comparing the two
same pulse width, the device mismatches are detected.
The mismatches include the mismatches of capacitance
and the charge pump in the PWC. In the remaining half
period, the PWC decides the polarity of the mismatches
and calibrates the mismatches. Therefore, the
implemented FCL and MCL can track and compensate
for frequency deviation over PVT variations.
III. EXPERIMENTAL RESULTS
The ILRPLL is fabricated in a 65-nm CMOS
technology. The active die area of the ILRPLL chip is
0.064 mm2. The chip photomicrograph and the power
breakdown are shown in Fig. 9. The ILRPLL operates at
3.328 GHz and consumes 7.16 mW from a 1.2-V supply
with a 52-MHz reference clock.
The measured phase noise at this frequency with N =
64 is shown in Fig. 10. The phase noise of the free
running DCO without the injection is measured with a
‒85.97 dBc/Hz at the 1-MHz offset frequency. With the
reference clock injection enabled and the PLL locked, the
integrated jitter from 10 kHz–40 MHz is 555 fsrms, which
Fig. 11. Measured spectrum in initial state.
is in the initial state. Without the FCL and the MCL, fERR
is not zero and unpredictable due to the PLL operation
with the ILOs, resulting in poor jitter performance. In the
normal-operation state, the PLL is turned off and the
calibration loops start to operate. The measured phase
noise is ‒120.77 dBc/Hz at the 1-MHz offset frequency
and the measured jitter is 285 fsrms, which means that the
implemented calibration loops are working for the
minimization of fERR.
As shown in Fig. 11 and 12, the reference spur level
measurements are ‒40.3 dBc and ‒50.2 dBc for the
initial state and the normal-operation state, respectively.
Even with a slight degradation in jitter performance, the
spur level increases seriously. Because of this reason, the
calibration loops are essential to achieve the high
performance.
The performance of the implemented ILRPLL is
summarized and compared with the state-of-the-art ILOs
in Table 1. Compared to the ring-type architectures in [1]
and [7], it is noticeable that the proposed ILRPLL
exhibits a better FoM, even with a large multiplication
ratio.
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.6, DECEMBER, 2016
865
Table 1. Performance summary
This work
[1]
[3]
[7]
Technology [nm]
65
65
65
65
Output Freq. [GHz]
3.328
0.5-1.6
0.96-1.44
5
Multiplication ratio
64
4
10
32
RMS jitter [fs]
285
(10k-40 MHz)
700
(10k-40 MHz)
185
(10k-40 MHz)
484
(1k-40 MHz)
Power [mW]
7.16
0.97
9.5
15.4
FoM† [dB]
-242.4
-234.2
-244.9
-234.4
†
FoM = 10log[(σrms/1s)2·(P/1 mW)]
−50.21dBc
[2]
Fig. 12. Measured spectrum in normal-operation state.
[3]
power and low-jitter dual-loop injection locked
PLL using all-digital PVT calibration,” IEEE
Journal of Solid-State Circuits, vol. 49, no. 1, pp.
50–60, Jan. 2014.
B. M. Helal, C.-M. Hsu, K. Johnson, and M. H.
Perrott, “A low jitter programmable clock
multiplier based on a pulse injection-locked
oscillator with a highly-digital tuning loop,” IEEE
Journal of Solid-State Circuits, vol. 44, no. 5, pp.
1391–1400, May 2009.
S. Choi, S. Yoo, and J. Choi, “A 185-fsrmsintegrated-jitter and  ‒ 245dB FOM PVT-robust
V. CONCLUSIONS
A low-jitter ILRPLL with the multiplication ratio of
64 fabricated in 65-nm CMOS technology is proposed.
The prototype chip operates at 3.328 GHz while
consuming 7.16 mW, and it achieves the FoM of ‒242.4
dB. This work has two main contributions to the ILRPLL
design. First, it proposes a novel injection technique to
enhance the injection strength with doubled reference
frequency injection and charge storing capacitor. Second,
the implemented calibration loops successfully address
the performance degradation issue of the ILOs achieving
an outstanding performance.
ACKNOWLEDGMENTS
This paper was result of the research project supported
by SK hynix Inc. and Inter-university Semiconductor
Research Center (ISRC) of Seoul National University.
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ring-VCO-based injection-locked clock multiplier
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Jang, S.-H. Chu, W. Bae, Y. Kim, and D.-K. Jeong,
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H. Kim, Y. Kim, T. Kim, H. Park, and S. Cho, “A
2.4GHz 1.5mW digital MDLL using pulse-width
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Sungwoo Kim received the B.S.
degree in electronic engineering from
the Kyungpook National University,
Daegu, Korea, in 2009, and the M.S.
degrees from the Seoul National
University, Seoul, Korea, in 2011,
where he is currently working toward
the Ph.D. degree. His research interests include phaselocked loop and injection-locked oscillator for highspeed communication.
Sungchun Jang received the B.S.,
M.S., and Ph.D. degrees in electrical
engineering and computer science
from Seoul National University,
Seoul, Korea, in 2008, 2010 and
2015, respectively. He joined SK
hynix, Icheon, Korea, in 2016. His
research interests include high-speed I/O circuits and alldigital PLL/DLL design.
Sung-Yong Cho received the B.S
degree in electrical engineering from
Pohang University of Science and
Technology (POSTECH), Pohang,
Korea, in 2012. He is currently
working toward the Ph.D. degree in
electrical engineering at Seoul
National University, Seoul. His research is focused on
high-speed I/O circuits and architectures.
Min-Seong Choo received the B.S.
degree in electrical engineering and
computer science from Seoul
National University, Seoul, Korea, in
2012. He is currently working
toward the Ph.D. degree in the same
university. His research interests
include high-speed I/O circuits using injection locking
techniques.
Gyu-Seob Jeong received the B.S.
degree in electrical engineering and
computer science from Seoul
National University, Seoul, Korea, in
2012. He is currently working toward
the Ph.D. degree in the same
university. His research interests
include silicon photonics, high-speed I/O circuits.
Woorham Bae received the B.S. and
Ph.D. degrees in electrical and
computer engineering from Seoul
National University, Seoul, Korea, in
2010 and 2016, respectively. He is
currently a Postdoctoral Researcher
at the Inter-University Semiconductor Research Center, Seoul National University. His
current research interests include integrated circuits for
silicon photonics, high-speed I/O circuits and
architectures, and non-volatile memory systems. Dr. Bae
received the Distinguished Ph.D. Dissertation Award
from the Department of Electrical and Computer
Engineering, Seoul National University in 2016, the
IEEE Circuits and Systems Society Pre-Doctoral
Scholarship in 2016, the IEEE Solid-State Circuits
Society STG Award at the Asian Solid-State Circuits
Conference in 2015, and the Best Poster Award at the IC
Design Education Center Chip Design Contest,
International SoC Design Conference, in 2014.
Deog-Kyoon Jeong received the B.S.
and M.S. degrees in electronics
engineering from Seoul National
University, Seoul, Korea, in 1981
and 1984, respectively, and the Ph.D.
degree in electrical where he was a
Member of Technical Staff and
worked on engineering and computer sciences from the
University of California, Berkeley, in 1989. From 1989
to 1991, he was with Texas Instruments, Dallas, TX, the
modeling and design of BiCMOS gates and the singlechip implementation of the SPARC architecture. He
joined the faculty of the Department of Electronics
Engineering and Inter-University Semiconductor Research
Center, Seoul National University, as an Assistant
Professor in 1991. He is currently a Professor in the
School of Electrical Engineering, Seoul National
University. His main research interests include highspeed I/O circuits, VLSI systems design, microprocessor
architectures, and memory systems.