COMPARISON OF PLASMA-INDUCED DAMAGE IN SIO2/TiN AND HFO2/TIN GATE STACKS
C.D. Young, G. Bersuker, F. Zhua, K. Matthewsb, R. Choi, S.C. Song, H.K. Parke, J.C. Leea, and B.H. Leed
[email protected], 512-356-3612 (0), 512-356-3640 (Fax)
SEMATECH and b ATDF
2706 Montopolis Drive, Austin, TX, 78741, U.S.A.
aUniversity of Texas - Austin, U.S.A., 'GIST, Korea, dIBM assignee to SEMATECH
probability distributions of the shifts of the device parameters such as
threshold voltage (Vt), transconductance (gm,max), and subthreshold
swing (SS) caused by the exposure. Then, after two weeks, the
measurements were repeated to study relaxation of the plasmainduced parameter shifts. The high-K samples were also subjected to
a "discharge" stress (under the accumulation bias condition) for 2
sec. to examine any potential "enforced" Vt recovery.
ABSTRACT
SiO2 and HfO2 gate dielectrics with TiN electrodes were
subjected to an aggressive post-fabrication plasma exposure. A
comparison of plate and comb antenna structures before and after
exposure demonstrated that the plate antennae structures demonstrate
evidence of plasma-induced damage while the comb structures did
not. The physical origin of PD in SiO2 devices was found to be the
amphoteric interface states, while the primary effect in HfO2 devices
was charges trapped in the bulk of the high-K film.
RESULTS AND DISCUSSION
Antenna Structure
INTRODUCTION
Two different gate antenna types, plate and comb, were
electrically tested. Devices of the same geometry but with no antenna
(beside the gate probing pad) were used as a control (Fig. 1). Plate
antenna ratios (AR) the ratio of the antenna area to the gate areawere ARI = 23000:1, AR2 = 50000:1, AR3 = 100000:1. To study
electron shading effects in the three comb antenna structures with
different spacing between the comb "fingers," the area antenna ratio
was maintained at 23000:1. Even though total antenna ratios were the
same, the comb structures could be more vulnerable to the gate etch
or spacer process since a larger gate sidewall area was exposed to
plasma. The difference between the two types of antennae is
illustrated by the Vt probability distribution plot (Fig. 2). The plate
antenna structures show a clear AR dependence. The comb
structures, which have the same area as ARI, demonstrate no comb
spacing dependence, but exhibit a Vt shift similar to ARI. This
indicates that there is no evidence of the electron shading effect [2],
most likely because the comb sidewalls were passivated leaving only
the top comb area susceptible to plasma charging. Since the comb
structures did not yield useful information, the focus of this study
became the plate antenna effects.
Plasma-induced damage concerns, which have been an issue in
conventional SiO2/poly transistors [1], appear to subside when the
Sio2 dielectric becomes thinner [2]. However, the introduction of
high-K dielectrics, which are supposed to replace SiO2, again raises
concerns about their susceptibility to plasma-induced charging [3-5].
The complexity of high-K gate stack integration in conjunction with
metal electrodes poses additional challenges since the effects of
plasma-induced damage from the novel processes may not yet be
known [3]. Hafnium-based dielectrics are being widely investigated
as potential candidates for replacing silicon oxide-based dielectrics.
These dielectrics being structurally different from the conventional
thermal SiO2 and SiON may exhibit different sensitivity to plasmainduced electrical stress. In this study, we report on the plasmainduced damage effects in nMOS and pMOS SiO2/TiN and
HfO2/TiN gate stacks in an effort to evaluate the effects of plasma
processing on these materials.
EXPERIMENT
Sample Preparation
High-i/TiN CMOS transistors were fabricated using conventional
semiconductor processing up to metal-1, which included a 1000°C
dopant activation and 485°C post-metal forming gas anneal. An
atomic layer deposited (ALD) HfO2 gate dielectric of 2.5 nm on a
nitrogen-bearing interfacial layer of 1 nm [6] was fabricated with an
equivalent oxide thickness (EOT) of 0.85 nm for the gate stack and
leakage current density (Jg) (flatband voltage [Vfb] - 1) = 3.5 A/cm2.
A 2 nm SiO2/TiN control sample was included for comparison. The
plasma test structures included plate and comb metal-I antennae
attached to the gates of the W/L = 5/0.25 ptm transistors. In the
plasma damage evaluation experiment, these fully processed devices
were subjected to an additional post-process plasma exposure in an
oxygen plasma ashing tool for various times at a fixed plasma
generation power condition.
Gate Antenna
Characterization
Fig. 1. Schematic layout of devices used in this study: (a)
control (no antenna), (b) Plate (c) Comb. Both antenna
structures have 23k antenna ratio in this example.
Drain current-voltage (Id-Vg) was measured on the plasma
damage test structures before and after plasma exposure to extract
1-4244-0919-5/07/$25.00 02007 iEEE
67
EEE 07CH37867 45th Annual international Reliability
Physics Symposium, Phoenix, 2007
100
*
.
80
Ref
AR1
AR2v
AR3 3
0
o
A
A
,
v
r
07
AV
X 40-
Comb2 0
Comb3 .
A
v
v
.Plate Vt
...
0)
>A
t
20k
-a)I
).3
0.4
0.5
0.6
*50)
Comb V
V
t
nMOS
300 W, 30 min
v closed: Post Expose
open: Pre-expose
b) ,
0.8 0.3 0.4
Voltage [V]
0.7
0.5
0.6
0.7
0.8
U~~~0
0.65
Ref
Z
_.1 S
C0D
40-
A
7t
20
v 0.60
0ARi
AR3
A AR2
v ARJ3
-0.5
....I....I.... I.... I....
I.....I.... .
Threshold Voltage @ 50% [V]
Fig. 4. Vt change during relaxation as a function of AR.
Similar Vt values were extracted immediately after the
exposure and after a two-week waiting period.
0.65 .1
Fa)
nMOS Vt
|
pMOS Vt
-0.45
> 0.55
2nmSiO2
0,
I
'5-0
j
0
closed: Post Expose
open: Pre-expose
0.40
-0.55
0.35
pMOS
Exposure Power: 300 W
20
30
40
50
60
0
ItoD
I
2nm SiO2
10
m
Ion
-0.50 s*
ua
ua0
I
0.50
o 0.45
-0 0.55
I- 0.50
-0.40
0.60
0
0.45
Solid: After exposure
-0.5-0.4-0.3-0.2-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6
-0.4
Voltage M
AR1
later
Hashed: Two weeksI....
.I...,I....,I....,I....,I....,
60m in
~300
closed: Post Expose
0open: Pre-expose
-0.6
0,
~v
1
2
by
AR1
A AR2
100
60 V
PMOS
Ref
Fig. 2. a) Plate vs. b) Comb. Evidence of PD is seen in
plate antennae while the comb antennae show no AR
dependence.
0.70
NMOS
AR3
Combl
2.5nm HfO 2 . ,>
0
0
RefC
g~F-
AV
AA v
60._
*
*
nMOS
Exposure Power: 300 W
10
20
Exposure Time [min]
30
40
50
A v.u
'An
60
300W, 60min
AR1 AR2 AR3
nMOS Device Type
Ref
Fig. 3. Time evolution of Vt as a function of AR during
plasma exposure of the SiO2 devices: a) pMOS and b)
nMOS. AR1<AR2<AR3.
Ref AR1 AR2 AR3
pMOS Device Type
-0.60
Fig. 5. Comparison of Vt in SiO2 a) nMOS and b) pMOS
devices illustrating the opposite polarity charging for
nMOS and pMOS devices.
SiO2 Control
to scale) for nMOS (Fig. 8a) and pMOS (Fig. 8b) in inversion. In the
nMOS case, most of the generated interface states would be filled
with electrons since these states are below the Fermi level while the
opposite is true in the pMOS case since most states above the Fermi
level are empty (positively charged). Therefore, the nMOS Vt is
expected to shift to the right, while the pMOS Vt shifts to the left, in
agreement with the data in Fig. 5, thus demonstrating an amphoteric
nature of the generated interface states. This PD-induced effect has
been previously reported for SiO2 [2].
Fig. 3 illustrates the plasma damage (PD) as a function of the
time dependence of the plasma exposure of nMOS and pMOS
devices. Vt values were selected at the 50 percentile (50%) point of
the probability distribution (inset, Fig. 3). The results clearly
demonstrate that the Vt shift is a function of the AR for the given
exposure time condition, which is a signature of the plasma-induced
damage. The absence of Vt recovery over a two-week waiting period
is indicative of possible permanent charging damage, Fig. 4. The
SiO2 sample exhibits negative and positive charging for nMOS and
pMOS, respectively (Fig. 5). To investigate the origin of this polarity
dependence, gm,max and SS were extracted from the same Id-Vg data,
which determined Vt in nMOS (Fig. 6) and pMOS (Fig. 7).
Noticeable degradation of these parameters in both nMOS and
pMOS demonstrates that interface states were generated during the
plasma exposure. Fig. 8 represents the schematic band diagram (not
HfO2
The plasma exposure time dependence for the HfO2 nMOS and
pMOS devices is shown in Fig. 9. Again, the results demonstrate the
Vt shifts as a function of the AR for the given exposure time
condition. The Vt values at 50% (inset, Fig. 9) demonstrate a clear
trend of an increasing Vt shift for nMOS and decreasing Vt shift for
68
100
* AR1
0.85
80
A AR2
V AR3
4
80
*
~40
*
.20
*
*U
60
.0
-0
0o
a.
*
~60-
0
*
0
o 0.80
LO
0
0
100
25
30
35
40
gmm [10 mho]
0
.0
0,
A
*
A
U
I0
nMOS
300 W, 60 min
closed: Post Expose
0 open: Pre-expose
65
70
75
20
I.I
A
2U
A
v
*
v
2n im sio2
80
85
0.75
-g m, max
A
A2\B
e
*
v
V AR3
40
pMOS
300 W, 60 min
closed: Post Expose
Z 60
v
v
v
-0 20 t open: Pre-expos
0.
v
v
-1.0
Voltage [V]
-1.2
0.65
90
-0.8
pMOS
Exposure Power: 300 W
20 30 40 50 60
10
nMOS
Exposure Power: 300 W
10
g6
40
nMOS Vt
U~~~~~
A
40
[10 mho]
v
A
_~~~~~~~~~~~
A
ED
nMOS
300 W, 60 min
v,
closed: Post Expose *v
0
2nm SiO2
open: Pre-expose
65
70
75
80
20
V0
0.75
CD
-0.85 w
0
0.70
v
a)
)F
0
V
s 0.65 jF
*
V
85
Ref
R
AR2
AR3
90
0.60
t1
tio~~~AI
0
0~~~~~
0
to
0D
-0.90'<
closed: Post Expose
0.55
Subtreshold Slope [mV/decade]
300 W, 60 min
2.5nm HfO21-0.95
AR2
AR2
AR1
AR3
Ref
AR3
AR1
pMOS Device Type
nMOS Device Type
open:
Pre-expose
..
Ref
Fig. 10. Comparison of the HfO2 a) nMOS and b) pMOS Vt
changes by the exposure illustrating the same polarity of
charging.
Fig. 7. pMOS: gm,max (inset) and SS degradation as a
function of AR demonstrating interface states are generated
after experiencing a plasma exposure.
a)
60
*V
*
0
.0
50
I~
pMOS Vt b) -0.80
-a)
0
35
40
0.80
V
0
30
30
Fig. 9. Time evolution Vt during plasma exposure for the
HfO2 a) pMOS and b) nMOS devices as a function of AR.
20
25
20
Exposure Time [min]
V
A
f
40 -*
.°
0o
GA
VA
>,60 -
80
a.
v
80-
ARII
,2
0r
0.85
100
ou Ref
*
A A AR2
0
Fig. 6. nMOS: gmmax (inset) and SS degradation as a
function of AR demonstrating interface states are generated
after experiencing a plasma exposure.
100
0
°
-.
0.70
u,
Ref
AR1
AR2
AR3-
*
*
v
v
Subtreshold Slope [mV/decade]
-0
2.5nm HfO2
0
40
60
)F
pMOS with exposure time. Moreover, the nMOS and pMOS Vt
values shift in the same direction (Fig. 10), unlike in the case of SiO2
discussed above (Fig. 5). To explain the origin of PD in this
particular HfO2 sample, the gm,max and SS were extracted. The
results for nMOS and pMOS are shown in Figs. 11 and 12,
respectively. There is no AR dependence of the gm,max shift in either
the nMOS (inset, Fig. 11) and pMOS (inset, Fig. 12) cases after
exposure while the SS shift in the pMOS case (Fig. 12) demonstrates
a slight AR-dependent degradation. These results suggest that no
significant interface state generation occurred in the HfO2 sample.
Since HfO2 is known to readily trap/detrap charges [6], the HfO2
sample was subjected to the relaxation and discharge study. Similar
to SiO2, the high-K sample was remeasured after waiting for two
weeks from the initial exposure. Immediately following these
measurements, a "discharge" stress (under the accumulation bias, for
2 sec) was executed, followed by Id-Vg measurements to determine
whether any charge relaxation occurred. The pMOS devices did
exhibit a complete spontaneous room temperature anneal of the
b)
Fig. 8. PD origin in SiO2: amphoteric interface states are
the a) negatively charged in the nMOS inversion case; b)
positively charged in the pMOS case.
69
r-
100
100
gm,max
,80
Z'
80
60-
0
60
.0
-0
40
0o
20
a.
Ref
AR1
AR2
AR3
0
-2
.
0
10
20
50
30
40
.g. [10 mho]
60
-
A
IL
v
v
0
Ir'
0-1,
0
nMOS
300 W, 60 mi In
closed: Post Exipose
open: Pre-exp(ose
s
2.5nm HfO2
ua
s
I-)
0
45
50
60
55
65
70
75
80
90
85
Subthreshold Slope [mV/decade]
Ref
100
40
X 20
3
20
0
40
f-l4
.0
0
40
a
NCu
r
60
80 -
*60
g
- 80- mmax
V
Ref
AR1
AR2
AR3
80
100 120
g mmax _' mho
2.5nm HfO
2
0
20
40
60
80
Ref
AR1
AR2
nMOS Device Type
AR3
[1] S.-C. Song, S. Filipiak, A. Perera, M. Turner, F. Huang, S. G.
H. Anderson, K. Laegu, M. Byoung, D. Menke, S.
Tukunang, and S. Venkatesan, "Avoiding plasma induced
damage to gate oxide with conductive top film (CTF) on
PECVD contact etch stop layer," presented at VLSI
Symposium Technical Digest, pp. 72-73, 2002.
[2] K. P. Cheung, Plasma Charging Damage: Springer, 2001.
[3] J. S. Suehle, E. M. Vogel, M. D. Edelstein, C. A. Richter, N. V.
Nguyen, I. Levin, D. L. Kaiser, H. Wu, and J. B. Bernstein,
"Challenges of high-k gate dielectrics for future MOS
devices," presented at International Symposium on P2ID,
pp. 90-93, 2001.
[4] P. J. Tzeng, Y. Y. Chang, and K. S. Chang-Liao, "Plasma
charging damage on MOS devices with gate insulator of
high-dielectric constant material," IEEE Electron Device
Letters, vol. 22, pp. 527-529, 2001.
[5] S. C. Song, S. H. Bae, Z. Zhang, J. H. Sim, B. Sassman, G.
Bersuker, P. Zeitzoff, and B. H. Lee, "Impact of Plasma
Induced Damage on PMOSFETs with TiN/Hf-Silicate
Stack," presented at International Reliability Physics
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[6] G. Bersuker, B. H. Lee, and H. R. Huff, "Novel Dielectric
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pp. 221-239, 2006.
140
pMOS
300 W, 60 min
closed: Post Expose
open: Pre-expose
AR3
REFERENCES
A
60
AR2
Fig. 13. Vt change during a) pMOS and b) nMOS
relaxation and discharge as a function of AR. pMOS
devices did exhibit a recovery of the Vt shift while nMOS
devices partially recovered only after a "discharge".
Fig. 11. nMOS: gmmax (inset) and SS changes due to the
plasma exposure demonstrating negligible interface trap
charge generation.
100
AR1
pMOS Device Type
100
Subthreshold Slope [mV/decade]
Fig. 12. pMOS: gm,max (inset) and SS changes due to the
plasma exposure demonstrating negligible interface trap
charge generation.
plasma-induced charges while nMOS devices still show a charging
antenna effect even after a -1.5 V, 2 sec. discharge (Fig. 13).
Therefore, one may conclude that in this HfO2 gate stack the plasmarelated charges, which cause the Vt shift, were trapped in the bulk of
the high-K film, away from the dielectric/Si substrate interface.
SUMMARY
SiO2 and HfO2 gate dielectrics with TiN electrodes were
subjected to an aggressive post-fabrication plasma exposure. The
plate antennae structures demonstrate evidence of plasma-induced
damage. The physical origin of PD in SiO2 devices was found to be
the amphoteric interface states, while the primary effect in HfO2
devices was charges trapped in the bulk of the high-K film.
70