US 20050124174A1
(19) United States
(12) Patent Application Publication (10) Pub. No.: US 2005/0124174 A1
Ahn et al.
(54)
(43) Pub. Date:
LANTHANIDE DOPED TIOX DIELECTRIC
Jun. 9, 2005
Publication Classi?cation
FILMS BY PLASMA OXIDATION
(51)
Int. Cl.7 ...................... .. H01L 21/336; H01L 21/31;
(52)
US. Cl. ............................................................ .. 438/785
(75) Inventors: Kie Y. Ahn, Chappaqua, NY (US);
Leonard Forbes, Corvallis, OR (Us)
Correspondence Address:
(57)
ictltmjepglglan’(ilungberglgsv?fssner & Kluth’ P'A'
A dielectric ?lm containing lanthanide doped TiOX and a
P OH‘B
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method of fabricating such a dielectric ?lm produce a
reliable gate dielectric having an equivalent oxide thickness
.
(73)
21
( )
(22)
H01L 21/469
_
.
ABSTRACT
thinner than attainable using SiO2. A dielectric ?lm is
formed by ion assisted electron beam evaporation of Ti,
Asslgnee' Mlcron Technology’ Inc‘
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11 031 289
pp
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Filed:
Jam 7 2005
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electron beam evaporation of a lanthanide selected from a
group consisting of Nd, Tb, and Dy, and oxidation of the
evaporated Ti/lanthanide ?lm in a Kr/oXygen plasma. The
groWth rate is controlled to provide a dielectric ?lm having
a lanthanide content ranging from about ?ve to about forty
percent of the dielectric ?lm. These dielectric ?lms contain
Related US Application Data
(62)
Division of application No, 10/219,870, ?led on Aug,
15, 2002, noW Pat. No. 6,884,739.
ing lanthanide doped TiOX are amorphous and thermody
namically stable such that the lanthanide doped TiOX Will
have minimal reactions With a silicon substrate or other
structures during processing.
SOS
EVAPORATE Ti SOURCE AT A FIRST
RATE USING A FIRST ELECTRON GUN
BIO
EI/APORATE A LANTHANIDE SOURCE
AT A SECOND RATE USING A
SECOND ELECTRON GUN
1../
CONTROL THE FIRST RATE AND
THE SECOND RATE TO DEPOSIT A
FILM ON A SUBSTRATE, THE FILM
CONTAINING Ti DOPED WITH THE
LANTHANIDE
52D
OXIDIZE THE FILM USING ATOMIC
OXYGEN GENERATED IN A PLASMA
Patent Application Publication
Jun. 9, 2005 Sheet 1 0f 10
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Jun. 9, 2005 Sheet 3 0f 10
Fig.3
US 2005/0124174 A1
Patent Application Publication
Jun. 9, 2005 Sheet 4 0f 10
' m5
EVAPORATE A Ti SOURCE AT A FIRST
RATE TO DEPOSIT Ti ON A SUBSTRATE
AIO
EVAPORATE A LANTHANIDE SOURCE
AT A SECOND RATE TO DEPOSIT
LANTHANIDE ON THE SUBSTRATE
AIS
OXIDIZE THE DEPOSITED Ti AND
LANTHANIDE USING ATOMIC OXYGEN
GENERATED IN A PLASMA
Big. A
SOS
EVAPORATE Ti SOURCE AT A FIRST
RATE USING A FIRST ELECTRON GUN
BIO
EVAPORATE A LANTHANIDE SOURCE
AT A SECOND RATE USING A
SECOND ELECTRON GUN
SI?)
CONTROL THE FIRST RATE AND
THE SECOND RATE TO DEPOSIT A
FILM ON A SUBSTRATE, THE FILM
CONTAINING Ti DOPED WITH THE
LANTHANIDE
DXIDIZE THE FILM USING ATOMIC
OXYGEN GENERATED IN A PLASMA
Rig. ‘5
US 2005/0124174 A1
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CONTROL AN ENVIRONMENT OF A
REACTION CHAMBER
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CONTROL EVAPORATION OF A Ti
SOURCE IN THE REACTION CHAMBER
AT A FIRST RATE
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CONTROL EVAPORATION OF A
LANTHANIDE SOURCE IN THE REACTION
CHAMBER AT A SECOND RATE
CONTROL THE FIRST RATE AND THE
SECOND RATE TO DEPOSIT A FILM ON
A SUBSTRATE, THE FILM CONTAINING
Ti DOPED WITH THE LANTHANIDE
CONTROL OXIDATION OF THE FILM
USING ATOMIC OXYGEN GENERATED
IN A PLASMA TO FORM A
DIELECTRIC FILM CONTAINING TiOx
DOPED WITH THE LANTHANIDE
Fig.7
Patent Application Publication
Jun. 9, 2005 Sheet 7 0f 10
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US 2005/0124174 A1
LANTHANIDE DOPED TIOX DIELECTRIC FILMS
BY PLASMA OXIDATION
RELATED APPLICATIONS
[0001]
The present application is a divisional of US.
application Ser. No. 10/219,870, ?led Aug. 15, 2002, Which
is incorporated herein by reference.
[0002]
This application is related to the following com
monly assigned applications, incorporated herein by refer
ence:
docket no. 150.01200101 entitled “Formation of
Metal Oxide Gate Dielectric,” noW issued as US.
[0009] In fabricating transistors to be smaller in siZe and
reliably operating on loWer poWer supplies, one important
design criteria is the gate dielectric 140. The mainstay for
forming the gate dielectric has been silicon dioxide, SiO2.
Pat. No. 6,495,436;
Thermally groWn amorphous SiO2 provides an electrically
[0003] US. application Ser. No. 09/779,959, attorney
[0004] US. application Ser. No. 09/908,767, attorney
and thermodynamically stable material, Where the interface
of a SiO2 layer With an underlying Si provides a high quality
docket no. M1122-1530 entitled “Methods for Form
interface as Well as superior electrical isolation properties. In
ing Dielectric Materials and Methods for Forming
typical processing, use of SiO2 on Si has provided defect
charge densities on the order of 101O/cm2, midgap interface
state densities of approximately 101O/cm2 eV, and break
doWn voltages in the range of 15 MV/cm. With such
Semiconductor Devices,” noW issued as US. Pat.
No. 6,534,420; and
[0005] US. application Ser. No. 10/219,878, attorney
docket no. 1303.070US1 entitled “Lanthanide doped
TiOX Dielectric Films,” noW issued as US. Pat. No.
6,790,791.
FIELD OF THE INVENTION
[0006] The invention relates to semiconductor devices and
device fabrication. Speci?cally, the invention relates to gate
dielectric layers of transistor devices and their method of
fabrication.
BACKGROUND OF THE INVENTION
[0007]
qualities, there Would be no apparent need to use a material
other than SiO2, but With increased scaling, other require
ments for gate dielectrics create the need to ?nd other
dielectric materials to be used for a gate dielectric.
[0010] What is needed is an alternate dielectric material
for forming a gate dielectric that has a high dielectric
constant relative to SiO2, and is thermodynamically stable
With respect to silicon such that forming the dielectric on a
silicon layer Will not result in SiO2 formation, or diffusion of
material, such as dopants, into the gate dielectric from the
underlying silicon layer.
SUMMARY OF THE INVENTION
The semiconductor device industry has a market
driven need to improve speed performance, improve its loW
static (off-state) poWer requirements, and adapt to a Wide
range of poWer supply and output voltage requirements for
it silicon based microelectronic products. In particular, in the
fabrication of transistors, there is continuous pressure to
reduce the siZe of devices such as transistors. The ultimate
goal is to fabricate increasingly smaller and more reliable
integrated circuits (ICs) for use in products such as proces
sor chips, mobile telephones, or memory devices such as
DRAMs. The smaller devices are frequently poWered by
batteries, Where there is also pressure to reduce the siZe of
the batteries, and to extend the time betWeen battery charges.
This forces the industry to not only design smaller transis
tors, but to design them to operate reliably With loWer poWer
supplies.
[0008]
located betWeen source region 120 and drain region 130, the
body region 132 de?ning a channel of the transistor With a
channel length 134. A gate dielectric, or gate oxide 140 is
located on the body region 132 With a gate 150 located over
the gate dielectric. Although the gate dielectric can be
formed from materials other than oxides, the gate dielectric
is typically an oxide, and is commonly referred to as a gate
oxide. The gate may be fabricated from polycrystalline
silicon (polysilicon) or other conducting materials such as
metal may be used.
[0011] A solution to the problems as discussed above is
addressed in embodiments of the present invention. In
accordance With an embodiment of the present invention, a
method of forming a dielectric ?lm includes evaporating a Ti
source at a ?rst rate to deposit Ti on a substrate, evaporating
a lanthanide source at a second rate to deposit a lanthanide
on the substrate, controlling the ?rst rate and the second rate
to form a lanthanide doped Ti ?lm (a Ti/lanthanide ?lm), and
oxidiZing the Ti/lanthanide ?lm to groW a dielectric ?lm on
a substrate, Where the dielectric ?lm contains TiOX doped
With the lanthanide. In one embodiment, the lanthanide
includes evaporating a lanthanide selected from a group
consisting of Nd, Tb, and Dy.
[0012]
Currently, the semiconductor industry relies on the
ability to reduce or scale the dimensions of its basic devices,
primarily, the silicon based metal-oxide-semiconductor ?eld
effect transistor (MOSFET). A common con?guration of
such a transistor is shoWn in FIG. 1. While the folloWing
In one embodiment, the Ti and the lanthanide are
evaporated using electron beam evaporation. In another
embodiment, the evaporation of Ti and lanthanide is assisted
by ion beam bombardment of the substrate surface during
deposition. The evaporation of the Ti and the lanthanide is
folloWed by oxidation using a Kr/oxygen plasma.
discussion uses FIG. 1 to illustrate a transistor from the prior
[0013]
art, one skilled in the art Will recogniZe that the present
invention could be incorporated into the transistor shoWn in
FIG. 1 to form a novel transistor according to the invention.
The transistor 100 is fabricated in a substrate 110 that is
taining lanthanide doped TiOX has a larger dielectric con
stant than silicon dioxide, a relatively small leakage current,
and good stability With respect to a silicon based substrate.
Embodiments according to the teachings of the present
typically silicon, but could be fabricated from other semi
invention include forming transistors, capacitors, memory
devices, and electronic systems having dielectric layers
containing lanthanide doped TiOX. Other embodiments
conductor materials as Well. The transistor 100 has a source
region 120 and a drain region 130. A body region 132 is
A gate dielectric formed as a dielectric ?lm con
Jun. 9, 2005
US 2005/0124174 A1
include structures for transistors, capacitors, memory
devices, and electronic systems With gate dielectrics con
taining lanthanide doped TiOX. Such gate dielectrics provide
a signi?cantly thinner equivalent oXide thickness compared
With a silicon oXide gate having the same physical thickness.
Alternatively, such gate dielectrics provide a signi?cantly
thicker physical thickness than a silicon oXide gate dielectric
having the same equivalent oXide thickness.
[0014] These and other embodiments, aspects, advan
tages, and features of the present invention Will be set forth
[0025]
[0026] FIG. 10 illustrates a schematic vieW of an embodi
ment of a central processing unit incorporating devices
according to the teachings of the present invention.
[0027] FIG. 11 illustrates a schematic vieW of an embodi
ment of a DRAM memory device, according to the teachings
of the present invention.
in part in the description Which folloWs, and in part Will
DETAILED DESCRIPTION OF THE
PREFERRED EMBODIMENTS
become apparent to those skilled in the art by reference to
the folloWing description of the invention and referenced
draWings or by practice of the invention. The aspects,
advantages, and features of the invention are realiZed and
attained by means of the instrumentalities, procedures, and
combinations particularly pointed out in the appended
claims.
FIG. 9 shoWs an embodiment of a personal com
puter incorporating devices according to the teachings of the
present invention.
[0028] In the folloWing detailed description of the inven
tion, reference is made to the accompanying draWings Which
form a part hereof, and in Which is shoWn, by Way of
illustration, speci?c embodiments in Which the invention
may be practiced. In the draWings, like numerals describe
substantially similar components throughout the several
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] FIG. 1 shoWs a common con?guration of a tran
sistor in Which an embodiment of a gate dielectric can be
formed, according to the teachings of the present invention.
[0016] FIG. 2 illustrates an embodiment of an evaporation
system for forming a ?lm containing Ti doped With a
lanthanide, according to the teachings of the present inven
tion.
[0017]
FIG. 3 illustrates an embodiment of a plasma
oxidation system for forming a dielectric ?lm containing
lanthanide doped TiOX, according to the teachings of the
present invention.
[0018] FIG. 4 illustrates a How diagram of elements for an
embodiment of a method for processing a dielectric ?lm
containing lanthanide doped TiOX, according to the teach
ings of the present invention.
vieWs. These embodiments are described in suf?cient detail
to enable those skilled in the art to practice the invention.
Other embodiments may be utiliZed and structural, logical,
and electrical changes may be made Without departing from
the scope of the present invention.
[0029]
The terms Wafer and substrate used in the folloW
ing description include any structure having an eXposed
surface With Which to form the integrated circuit (IC)
structure of the invention. The term substrate is understood
to include semiconductor Wafers. The term substrate is also
used to refer to semiconductor structures during processing,
and may include other layers that have been fabricated
thereupon. Both Wafer and substrate include doped and
undoped semiconductors, epitaXial semiconductor layers
supported by a base semiconductor or insulator, as Well as
other semiconductor structures Well knoWn to one skilled in
the art. The term conductor is understood to include semi
conductors, and the term insulator or dielectric is de?ned to
include any material that is less electrically conductive than
[0019] FIG. 5 illustrates a How diagram of elements for an
embodiment of a method for processing a dielectric ?lm
the materials referred to as conductors.
containing lanthanide doped TiOX using electron beam
evaporation folloWed by plasma oxidation, according to the
[0030] The term “horizontal” as used in this application is
de?ned as a plane parallel to the conventional plane or
surface of a Wafer or substrate, regardless of the orientation
teachings of the present invention.
of the Wafer or substrate. The term “vertical” refers to a
[0020] FIG. 6A shoWs an embodiment of a layer of Ti
doped With a lanthanide deposited on a substrate, according
to the teachings of the present invention.
[0021] FIG. 6B shoWs an embodiment of a partially
oXidiZed Ti layer doped With lanthanide on a substrate,
according to the teachings of the present invention.
direction perpendicular to the horiZontal as de?ned above.
Prepositions, such as “on”, “side” (as in “sideWall”),
“higher”, “loWer”, “over” and “under” are de?ned With
respect to the conventional plane or surface being on the top
surface of the Wafer or substrate, regardless of the orienta
tion of the Wafer or substrate. The folloWing detailed
description is, therefore, not to be taken in a limiting sense,
doped TiOX ?lm substantially completely oXidiZed and
and the scope of the present invention is de?ned only by the
appended claims, along With the full scope of equivalents to
[0022]
FIG. 6C shoWs an embodiment of a lanthanide
formed on a substrate, according to the teachings of the
Which such claims are entitled.
present invention.
[0031] A gate dielectric 140 of FIG. 1, When operating in
[0023] FIG. 7 illustrates a How diagram of elements for an
embodiment of a computeriZed method for processing a
a transistor, has both a physical gate dielectric thickness and
dielectric ?lm containing lanthanide doped TiOX, according
an equivalent oXide thickness (teq). The equivalent oXide
thickness quanti?es the electrical properties, such as capaci
to the teachings of the present invention.
tance, of a gate dielectric 140 in terms of a representative
physical thickness. teq is de?ned as the thickness of a
[0024]
theoretical SiO2 layer that Would be required to have the
same capacitance density as a given dielectric, ignoring
leakage current and reliability considerations.
FIG. 8 shoWs an embodiment of a con?guration of
a transistor capable of being fabricated according to the
teachings of the present invention.
Jun. 9, 2005
US 2005/0124174 A1
[0032] A SiO2 layer of thickness, t, deposited on a Si
surface as a gate dielectric Will have a teq larger than its
[0037] The thinner equivalent oxide thickness required for
loWer transistor operating voltages and smaller transistor
thickness, t. This teq results from the capacitance in the
dimensions may be realiZed by a signi?cant number of
surface channel on Which the SiO2 is deposited due to the
materials, but additional fabricating requirements makes
formation of a depletion/inversion region. This depletion/
inversion region can result in teq being from 3 to 6 Ang
stroms (A) larger than the SiO2 thickness, t. Thus, With the
semiconductor industry driving to someday scale the gate
dielectric equivalent oxide thickness to under 10 A, the
physical thickness requirement for a SiO2 layer used for a
gate dielectric Would be need to be approximately 4 to 7
[0033] Additional requirements on a SiO2 layer Would
depend on the gate electrode used in conjunction With the
SiO2 gate dielectric. Using a conventional polysilicon gate
Would result in an additional increase in teq for the SiO2
layer. This additional thickness could be eliminated by using
a metal gate electrode, though metal gates are not currently
used in complementary metal-oxide-semiconductor ?eld
effect transistor (CMOS) technology. Thus, future devices
Would be designed toWards a physical SiO2 gate dielectric
layer of about 5 A or less. Such a small thickness require
ment for a SiO2 oxide layer creates additional problems.
[0034] Silicon dioxide is used as a gate dielectric, in part,
due to its electrical isolation properties in a SiO2—Si based
structure. This electrical isolation is due to the relatively
large band gap of SiO2 (8.9 eV) making it a good insulator
from electrical conduction. Signi?cation reductions in its
determining a suitable replacement for SiO2 dif?cult. The
current vieW for the microelectronics industry is still for Si
based devices. This requires that the gate dielectric
employed be groWn on a silicon substrate or silicon layer,
Which places signi?cant restraints on the substitute dielectric
material. During the formation of the dielectric on the silicon
layer, there exists the possibility that a small layer of SiO2
could be formed in addition to the desired dielectric. The
result Would effectively be a dielectric layer consisting of
tWo sublayers in parallel With each other and the silicon
layer on Which the dielectric is formed. In such a case, the
resulting capacitance Would be that of tWo dielectrics in
series. As a result, the teq of the dielectric layer Would be the
sum of the SiO2 thickness and a multiplicative factor of the
thickness of the dielectric being formed, Written as
t€q=tSi02+(KOX/K)t'
[0038] Thus, if a SiO2 layer is formed in the process, the
teq is again limited by a SiO2 layer. In the event that a barrier
layer is formed betWeen the silicon layer and the desired
dielectric in Which the barrier layer prevents the formation
of a SiO2 layer, the teq Would be limited by the layer With the
loWest dielectric constant. HoWever, Whether a single dielec
tric layer With a high dielectric constant or a barrier layer
band gap Would eliminate it as a material for a gate dielec
With a higher dielectric constant than SiO2 is employed, the
tric. As the thickness of a SiO2 layer decreases, the number
of atomic layers, or monolayers of the material in the
layer interfacing With the silicon layer must provide a high
quality interface to maintain a high channel carrier mobility.
thickness decreases. At a certain thickness, the number of
[0039] In a recent article by G. D. Wilk et al., Journal of
Applied Physics, vol. 89: no. 10, pp. 5243-5275 (2001),
material properties of high dielectric materials for gate
monolayers Will be suf?ciently small that the SiO2 layer Will
not have a complete arrangement of atoms as in a larger or
bulk layer. As a result of incomplete formation relative to a
bulk structure, a thin SiO2 layer of only one or tWo mono
layers Will not form a full band gap. The lack of a full band
gap in a SiO2 gate dielectric Would cause an effective short
betWeen an underlying Si channel and an overlying poly
dielectrics Were discussed. In this article, a number of oxides
Were identi?ed as possible candidates to replace SiO2 as a
gate dielectric. The list of possible candidates included the
folloWing:
silicon gate. This undesirable property sets a limit on the
physical thickness to Which a SiO2 layer can be scaled. The
minimum thickness due to this monolayer effect is thought
to be about 7-8
Therefore, for future devices to have a teq
less than about 10 A, other dielectrics than SiO2 need to be
considered for use as a gate dielectric.
[0035] For a typical dielectric layer used as a gate dielec
tric, the capacitance is determined as one for a parallel plate
capacitance: C=KeOA/t, Where K is the dielectric constant, 60
is the permittivity of free space, Ais the area of the capacitor,
and t is the thickness of the dielectric. The thickness, t, of a
material is related to teq for a given capacitance With the
dielectric constant of SiO2, KOX=3.9, associated With teq, as
Dielectric Constant
Band gap
Material
(K)
Eg (eV)
SiO2
Si3N4
A1203
3.9
7
9
8.9
5.1
8.7
Amorphous
Amorphous
Amorphous
Crystal Structure(s)
YZO3
La2O3
Ta2O3
15
30
26
5.6
4.3
4.5
Cubic
Hexagonal, Cubic
Orthorhombic
TiO2
80
3.5
Tetrag. (rutile,
HfO2
ZrO2
25
25
5.7
7.8
anatase)
Mono., Tetrag, Cubic
Mono., Tetrag, Cubic
desired equivalent oxide thickness. For example, an alter
[0040] One of the advantages using SiO2 as a gate dielec
tric has been that the formation of the SiO2 layer results is
an amorphous gate dielectric. Having an amorphous struc
ture for a gate dielectric avoids high leakage paths associ
ated With grain boundaries in polycrystalline gate dielec
nate dielectric material With a dielectric constant of 10 could
trics. Additionally, grain siZe and orientation changes
have a thickness of about 25.6 A to provide a teq of 10 A, not
throughout a polycrystalline gate dielectric can cause varia
tions in the ?lm’s dielectric constant. From above, the
materials having the advantage of a high dielectric constants
relative to SiO2 also have the disadvantage of a crystalline
form, at least in a bulk con?guration. The best candidates for
[0036] Thus, materials With a dielectric constant greater
than that of SiO2, 3.9, Will have a physical thickness that can
be considerably larger than a desired teq, While providing the
including any depletion/inversion layer effects. Thus, the
reduced equivalent oxide thickness of transistors can be
realiZed by using dielectric materials With higher dielectric
constants than SiO2.
Jun. 9, 2005
US 2005/0124174 A1
replacing SiO2 as a gate dielectric are those With high
[0046] Material evaporated using the electron gun devices
dielectric constant, Which can be fabricated as a thin layer
230, 235 and ions from ion gun 240 travel to substrate 210
through an ioniZer ring 245 and shutter 250. IoniZer ring 245
With an amorphous form.
[0041] Based solely on the siZe of the dielectric constant,
titanium oxide, TiO2, appears to be an excellent candidate
for replacing SiO2. HoWever, TiO2 does not provide the
electrical properties generally desired for integrated circuits,
such as, high electric ?eld breakdoWn and loW leakage
current. Dielectric ?lms substituting various cations into
amorphous TiOX ?lms by magnetron sputtering Were found
to provide improved electric ?eld breakdoWn and leakage
current With respect to undoped TiO2 ?lms. See, R. B.
Dover, Applied Physics Letters, vol. 74: no. 20, pp. 3041
3043 (2001).
[0042] HoWever, another consideration for selecting the
provides supplemental oxygen for processes that require
additional oxygen due to lost of oxygen in the evaporation
of target materials. For target materials substantially void of
oxygen, ioniZer ring 245 provides initial oxygen to a ?lm
deposited on substrate surface 212 that is to undergo a
subsequent oxidation process. Shutter 250 is used in con
junction With the control of electron gun devices 230, 235 to
control the groWth rate of a ?lm on substrate 210. The
groWth rate is determined using quartZ crystal monitors 255,
260. The quartZ crystal monitors 255, 260 are coupled to a
thickness/rate control 265, typically located outside reaction
chamber 205.
[0047]
Also located outside reaction chamber 205 is the
material and method for forming a dielectric ?lm for use in
electronic devices and systems concerns the roughness of a
dielectric ?lm on a substrate. Surface roughness of the
dielectric ?lm has a signi?cant effect on the electrical
oZone gas source 270 including a mass-?oW controller 275,
and an ion gas source 280. Mass-?oW controller 275 controls
the How of oZone into reaction chamber 205. Gas for the ion
properties of the gate oxide, and the resulting operating
gun 240 is controlled by an ion gun controller 285 including
characteristics of the transistor. The leakage current through
a mass-?oW controller 290. Further, a vacuum pump 295
With mass ?oW controller 298 maintains the overall atmo
a physical 1.0 nm gate oxide increases by a factor of 10 for
every 0.1 increase in the root-mean-square (RMS) rough
ness.
[0043] During a conventional sputtering deposition pro
cess stage, particles of the material to be deposited bombard
the surface at a high energy. When a particle hits the surface,
some particles adhere, and other particles cause damage.
High energy impacts remove body region particles creating
pits. The surface of such a deposited layer can have a rough
contour due to the rough interface at the body region.
[0044] An embodiment of the teachings of the present
invention includes dielectric ?lms containing TiOX doped
With a lanthanide formed by ion assisted electron beam
sphere of evaporation system 200 at desired levels prior to,
during, and after evaporation.
[0048] Electron gun device 230 can include an electron
gun and receptacle for a target material that is to be
evaporated. Target material placed in the target receptacle of
electron gun device 230 is heated by impact from an electron
beam from its associated electron gun. The electron beam is
generated With an intensity and duration With Which to
evaporate the material in the target receptacle of electron
gun device 230. The evaporated material then distributes
throughout the reaction chamber 205. The evaporated mate
rial and pre-evaporation contaminants are prevented from
evaporation folloWed by plasma oxidation. Dielectric ?lms
depositing on substrate surface 212 in an unWanted manner
formed on a substrate in such a manner Will have a surface
by shutter 250. Electron gun device 235 is similar to electron
that is smoother than a ?lm formed in another fashion such
as sputtering. This increased smoothness, or decreased
incorporate multiple target receptacles. Further, electron gun
roughness, is due in part to the use of high purity target
materials for evaporation. Further, With ion bombardment
during deposition by electron beam evaporation, additional
energy is provided for activation at the deposition interface
to provide for increased packing density of the dielectric
?lm. As a result of the ion bombardment during deposition,
the dielectric ?lm is not only smoother, but is more durable
in a humid environment. In addition, oxidation in a micro
Wave-excited plasma system using a radial line slotted
antenna provides for the formation of a uniform oxide layer.
[0045] FIG. 2 illustrates an embodiment of an evaporation
system 200 for forming a ?lm containing Ti doped With a
lanthanide, according to the teachings of the present inven
gun device 235. In one embodiment, these devices can
devices 230, 235 can be realiZed using commercially avail
able devices as are knoWn to those skilled in the art.
[0049] Ion gun 240 is a typical ion gun as is knoWn in the
art. In one embodiment, ion gun 240 provides an ion beam
With an incident angle that is Within +40° to —40° relative to
the substrate surface 212. In one embodiment, ion gun 240
is a ?lament-type ion gun With a relatively large diameter
ranging from 7.6 cm to 10 cm, Which uses a hot ?lament to
ioniZe gas from gas source 280. Alternately, a cold catheter
discharge gun can be used. Commercial ion guns are avail
able as is knoWn to those skilled in the art. Ion gun 240
regulated by ion gun controller 285 provides ions that are
directed at the substrate surface 212. The impact of the ions
tion. Evaporation system 200 includes a reaction chamber
205 in Which is located a substrate 210 having a surface 212
that is to be processed. Substrate 210 rests on substrate
holder 215 and its temperature can be raised above room
temperature using a heater 220 With its associated re?ector
225. Evaporation system 200 also includes a ?rst electron
212. In addition, to passing through an opened shutter 250,
the ions also pass through ioniZer ring 245 as they travel to
gun device 230 regulated by electron gun controller 232 and
a second electron gun device 235 regulated by electron gun
[0050] IoniZer ring 245 provides oxygen necessary to
compensate for loss of oxygen in the evaporated target
controller 237 for depositing material on substrate surface
212. To assist in the deposition of material onto substrate
surface 212, an ion gun 240 is provided in evaporation
material, or to add initial oxygen for subsequent oxidation
processing. In one embodiment, it includes a ring With a
system 200.
direct oZone ?oWing to ioniZer ring 245 from oZone gas
provides activation energy for the formation of a dielectric
?lm as evaporated material interacts With substrate surface
substrate surface 212.
center axis. The ring has a plurality of openings adapted to
Jun. 9, 2005
US 2005/0124174 A1
source 270 towards substrate surface 212. Ozone is uni
docket no. MI122-1530, Ser. No. 09/908,767, Which is
formly distributed to substrate surface 212 by ionizer ring
245 positioned generally parallel to substrate 210. Further,
incorporated herein by reference. The use, construction and
fundamental operation of a plasma oxidation system for
forming oxide ?lms are understood by those of ordinary skill
ioniZer ring 245 has a siZe that does not inhibit the ion beam
directed at substrate surface 212.
[0051] An evaporation system is described in co-pending,
commonly assigned US. patent application: entitled “For
mation of Metal Oxide Gate Dielectric,” attorney docket no.
15001200101, Ser. No. 09/779,959, Which is incorporated
herein by reference. The use, construction and fundamental
operation of reaction chambers for deposition of ?lms are
understood by those of ordinary skill in the art of semicon
ductor fabrication. The embodiments of the present inven
tion can be practiced on a variety of such reaction chambers
Without undue experimentation. Furthermore, one of ordi
nary skill in the art Will comprehend the necessary detection,
measurement, and control techniques in the art of semicon
ductor fabrication upon reading the disclosure.
in the art of semiconductor fabrication. The embodiments of
the present invention can be practiced on a variety of such
plasma oxidation systems Without undue experimentation.
Furthermore, one of ordinary skill in the art Will comprehend
the necessary detection, measurement, and control tech
niques in the art of semiconductor fabrication upon reading
the disclosure.
[0056] These elements of evaporation system 200 and
plasma oxidation system 300 can be controlled by a com
puter. To focus on the use of evaporation system 200 and
plasma oxidation system 300 in the various embodiments of
the present invention, the computer is not shoWn. Those
skilled in the art can appreciate that the individual elements
Evaporation system 200 can be used to evaporate
such as pressure control, temperature control, deposition rate
control, electron gun operation, ion gun operation, and
microWave generation Within evaporation system 200/
oxide material or non-oxygen material. When forming a
plasma oxidation system 300 can be under computer control.
[0052]
dielectric ?lm containing an oxide from the evaporation of
a substantially pure metal, evaporation system 200 is used in
conjunction With another system for oxidiZing a metallic
?lm formed on a substrate in evaporation system 200. Such
a oxidation system that can be used folloWing processing in
evaporation system 200 is a plasma oxidation system.
[0053]
FIG. 3 illustrates an embodiment of a plasma
In one embodiment, instructions stored in a computer read
able medium are executed by a computer to accurately
control the integrated functioning of the elements of evapo
ration system 200/plasma oxidation system 300 to form a
dielectric ?lm containing TiOX doped With a lanthanide.
[0057] FIG. 4 illustrates a How diagram of elements for an
embodiment of a method for processing a dielectric ?lm
oxidation system 300 for forming a dielectric ?lm contain
containing lanthanide doped TiOX, according to the teach
ing lanthanide doped TiOX, according to the teachings of the
ings of the present invention. In this embodiment, a method
present invention. Plasma oxidation system 300 includes a
reaction chamber 305 in Which is located a substrate 310
having a surface 312 that is to be processed. Substrate 310
of forming a dielectric ?lm includes evaporating a Ti source
at a ?rst rate to deposit Ti on a substrate, at block 405,
evaporating a lanthanide source at a second rate to deposit
rests on substrate holder 315 and its temperature can be
raised above room temperature using a heater 320. Plasma
lanthanide on the substrate, at block 410, and oxidiZing the
oxidation system 300 also includes a microWave generator
325, a co-axial Waveguide 330, a radial line slot antenna
335, and a microWave radiation plate 340 for generating a
microWave excited plasma. To focus on the use of plasma
oxidation system 300 in the various embodiments of the
is selected from a group consisting of Nd, Tb, and Dy.
[0058] In one embodiment, Ti is evaporated by electron
beam evaporation. Additionally, the lanthanide can also be
present invention, detailed elements of the plasma oxidation
Ti and/or the lanthanide can be evaporated by other pro
system are not shoWn. For example, gas inlets, vacuum
ports, and various control apparatus, as are knoWn to those
skilled in the art, are not shoWn.
[0054] Plasma oxidation system 300 provides circularly
deposited Ti and lanthanide using atomic oxygen generated
in a plasma, at block 415. In one embodiment, the lanthanide
evaporated using electron beam evaporation. Alternately, the
cesses including thermal evaporation. Also, during evapo
ration of the Ti and the lanthanide, the substrate surface is
bombarded With ions to facilitate the deposition of the Ti and
the lanthanide. Argon ions can be used in the ion bombard
polariZed microWaves that emanate from radial line slot
ment, or alternately xenon ions.
antenna 335, having been generated by microWave generator
325 and transmitted through co-axial Waveguide 330. The
[0059] The Ti and the lanthanide can be evaporated at
substantially the same time With different rates of evapora
microWaves interact With gases to produce a plasma. An
oxidation process using this system employs a mixture of
lanthanide dispersed throughout the ?lm prior to oxidiZing
oxygen an inert gases. Typically, the gas mixture can include
an oxygen concentration from about 2% to about 4% by
volume of the gas mixture. Suitable inert gases can include
krypton and helium. MicroWave interaction is effective to
form atomic oxygen that can readily interact With the surface
312 of a substrate 310. Further, use of a radial line slot
antenna gives rise to superior uniformity of the oxide across
substrate surface 312 as Well as high plasma density and loW
tion to insure that a ?lm formed on a substrate surface has
With a plasma. In one embodiment, oxidiZing With a plasma
can be accomplished With atomic oxygen generated in a
Krypton/oxygen plasma. Alternately, the plasma can be
generated using helium.
[0060] In one embodiment, prior to the plasma oxidation
process, oxygen is supplied during the evaporation of the Ti
and the lanthanide to provide a small seed amount of oxygen
into the ?lm prior to oxidation. This initial supply of oxygen
electron temperature.
is provided using an ioniZer ring. Alternately, the ioniZer ring
[0055]
is effectively turned off to provide a substantially oxygen
free ?lm for plasma oxidation.
[0061] In an embodiment, the ?rst rate for evaporating Ti
and the second rate for evaporating lanthanide is controlled
A plasma oxidation system is described in co
pending, commonly assigned US. patent application:
entitled “Methods for Forming Dielectric Materials and
Methods for Forming Semiconductor Devices,” attorney
Jun. 9, 2005
US 2005/0124174 A1
to provide a ?lm containing Ti doped With a predetermined
percentage of the lanthanide. In one embodiment, the Ti ?lm
can be doped in the range from about 10% to about 30% of
lanthanide. Subsequently, oxidizing the Ti/lanthanide ?lm
produces a dielectric ?lm doped in the range from about 5%
to about 40% of lanthanide. Further, controlling the ?rst and
second rate alloWs the dielectric ?lm to be formed having a
dielectric constant ranging from about 50 to about 110.
[0062] FIG. 5 illustrates a How diagram of elements for an
embodiment of a method for processing a dielectric ?lm
containing lanthanide doped TiOX using electron beam
evaporation folloWed by plasma oxidation, according to the
teachings of the present invention. In this embodiment, a
method of forming a dielectric ?lm includes evaporating a Ti
source at a ?rst rate using a ?rst electron gun, at block 505,
evaporating a lanthanide source at a second rate using a
second electron gun, at block 510, controlling the ?rst rate
and the second rate to deposit a ?lm on a substrate, the ?lm
containing Ti doped With the lanthanide, at block 515, and
oxidiZing the ?lm material using atomic oxygen generated in
can be used as a dopant in an amorphous TiOX ?lm. Addi
tionally, a Ti source of less purity can also be used in an
embodiment.
[0065] Reaction chamber 205 is evacuated to a loW pres
sure to maintain the substrate surface clean and in condition
for processing. In one embodiment, reaction chamber is
brought to and maintained at a pressure of about 2x10“7 Torr
prior to evaporating the Ti target and evaporating the lan
thanide target. While, in one embodiment, during the evapo
ration process, reaction chamber 205 is maintained at a
pressure of about 2x10‘6 Torr during deposition. The pres
sure in reaction chamber 205 is controlled by vacuum pump
295 through mass-?oW controller 298.
[0066]
The environment of reaction chamber 205 is fur
ther prepared by raising the temperature of substrate 210
using heater 220 and its associated re?ector 225. In one
embodiment, the substrate temperature is raised to and
maintained at a temperature ranging from about 100° C. to
about 200° C. prior to and during the formation of the ?lm
containing Ti and the lanthanide.
a plasma, at block 520. An embodiment of this method can
[0067]
be realiZed using evaporation system 200 of FIG. 2 and
plasma oxidation system 300 of FIG. 3.
tion chamber 205 have been attained, the evaporation pro
cess can begin. Electron gun device 230, regulated by
electron gun controller 232, evaporates Ti into reaction
chamber 205 Where it is distributed throughout. During the
[0063] An embodiment of a formation of a lanthanide
doped TiOX dielectric ?lm includes forming such a ?lm as a
gate dielectric of a transistor. Evaporation system 200 is
prepared by locating a substrate 210 on substrate holder 215.
Substrate 210 is a material used for forming a transistor such
as a silicon or silicon containing material. In other embodi
ments, germanium, gallium arsenide, silicon-on-sapphire
substrates, or other suitable substrates may be used. This
preparation process includes cleaning of the substrate 210
and forming layers and regions of the substrate, such as
drains and sources of a metal oxide semiconductor (MOS)
transistor, prior to forming a gate dielectric. The sequencing
of the formation of the regions of the transistor being
processed folloWs typical sequencing that is generally per
formed in the fabrication of a MOS transistor as is Well
knoWn to those skilled in the art. Included in the processing
prior to forming a gate dielectric is the masking of substrate
regions to be protected during the gate dielectric formation,
as is typically performed in MOS fabrication. In this
embodiment, the unmasked region includes a body region of
Once the desired environmental conditions fo reac
Ti evaporation, the selected lanthanide is evaporated using
electron gun device 235 regulated by electron gun controller
237, co-mingling the evaporated lanthanide With the evapo
rated Ti. The evaporated material is deposited on substrate
surface 212. The rates for forming the layer of Ti and
lanthanide groWn on substrate surface 212 is regulated using
thickness/rate control 265 that receives groWth information
from quartZ crystal monitors 255, 260.
[0068] Alternately, the Ti evaporation and the lanthanide
can be performed With one electron gun device having
multiple target receptacles that can be shielded from each
other. The electron gun device can further include either tWo
electron guns individually controlled or one electron gun
Whose electron beam can be multiply controlled providing
tWo beams directed individually in tWo directions. In such
cases, the electron gun device acts as tWo electron guns,
Where one generated beam de?nes a ?rst electron gun and a
second generated beam de?nes a second electron gun.
a transistor, hoWever one skilled in the art Will recogniZe that
other semiconductor device structures may utiliZe this pro
[0069] During the Ti and lanthanide evaporation, oxygen
cess. Additionally, the substrate 210 in its ready for process
ing form is conveyed into a position in reaction chamber 205
to undergo an ion assisted electron beam evaporation pro
245. OZone is supplied from oZone gas source 270 with How
cess.
[0064] Evaporation system 200 is also prepared by loading
a Ti target, or Ti source, into electron gun device 230 and
loading a lanthanide target, or lanthanide source, into elec
tron gun device 235. The lanthanide is used to provide a
dopant for a TiOX ?lm to be groWn on substrate surface 212.
The lanthanide can be selected from a group consisting of
Nd, Tb, and Dy. In one embodiment, the Ti source can
include Ti slugs, Where the Ti slugs are at least 99.9999%
pure. The lanthanide source can include a lanthanide that is
at least 99.999% pure. Typically, the lanthanide dopant
source material can be in the form of a poWder. In other
embodiments, other materials of varying degrees of purity
can be supplied at the substrate surface 212 by ioniZer ring
controlled by mass-?oW controller 275 through the openings
in ioniZer ring 245. In one embodiment, the partial pressure
of ozone in reaction chamber 205 is in the range of about
2x10 torr to about 8x10‘5 torr. Parameters for oZone partial
pressure can be determined from measuring oxygen content
in the deposited ?lm using the quartZ crystal monitors 255,
260. The oxygen can be supplied to provide an initial
amount of oxygen dispersed throughout the lanthanide
doped Ti ?lm (the Ti/lanthanide ?lm) to assist subsequent
plasma oxidation. Alternately, the oZone How can be main
tained in an off state to provide a Ti/lanthanide ?lm that is
substantially oxygen free prior to plasma oxidation.
[0070] Evaporation of the Ti and the lanthanide including
supplementing With oxygen provides the initial start material
for forming an amorphous TiOX dielectric layer doped With
Jun. 9, 2005
US 2005/0124174 Al
the lanthanide. To assist in the formation of this dielectric
layer, substrate surface is bombarded With argon ions. The
ion bombardment is initiated shortly after beginning the
evaporation process so that at least an initial monolayer or
so of Ti doped With the lanthanide is formed. In one
embodiment, an argon beam is directed at substrate surface
212 at about one to tWo seconds after the evaporation
process is initiated. Ion gun controller 285 regulates the How
of argon gas through mass-?oW controller 290 providing an
argon beam density in the range of about 0.5 ma/cm2 to
about 1 ma/cm2. In other embodiments, inert gases used in
the ion beam process can include xenon and krypton at
various beam densities.
[0071] Use of the electron gun controllers 232, 237 in
conjunction With thickness/rate control 265 alloWs the Ti to
be evaporated at a ?rst rate, and the lanthanide to be
evaporated at a second rate. By controlling the ?rst rate and
the second rate, a lanthanide doped Ti ?lm can be formed on
substrate surface 212 With the Ti ?lm doped in the range
from about 10% to about 30% of the lanthanide. Controlling
the evaporation rates alloWs the lanthanide to be selectively
doped in the Ti ?lm Within a predetermined range for the
percentage of the lanthanide in the ?lm. Further processing
to form an oxide results in a dielectric ?lm of TiOX doped
With the lanthanide, Where the dielectric ?lm can be selec
tively groWn, doped in the range from about 5% to about
40% of the lanthanide. Further, controlling the ?rst rate and
the second rate provides for groWing on substrate 210 an
amorphous TiOX ?lm doped With a lanthanide, Where the
[0074]
FIG. 6B shoWs an embodiment of a partially
oxidiZed Ti/lanthanide layer 650 on substrate 600, according
to the teachings of the present invention. In FIG. 6B, the
Ti/lanthanide layer 610 is in the process of being oxidiZed.
In one embodiment, the oxidation process includes a kryp
ton/oxygen mixed plasma oxidation process. The mixed
plasma process generates atomic oxygen or oxygen radicals
in contrast to molecular oxygen or 02 used in conventional
thermal oxidation. The atomic oxygen is introduced to the
layer from all exposed directions as indicated by arroWs 640,
creating an oxide portion 650. The atomic oxygen continues
to react With the layer and creates an oxidation interface 622.
As the reaction progresses, atomic oxygen diffuses through
the oxide portion 650 and reacts at the oxidation interface
622 until the layer is completely converted to an oxide of the
deposited material layer.
[0075]
FIG. 6C shoWs an embodiment of a lanthanide
doped TiOX substantially completely oxidiZed and formed
on substrate 600, according to the teachings of the present
invention. FIG. 6C shoWs the resulting oxide layer 650
Which spans a physical thickness 652 from the outer surface
630 to the interface 620. The overall thickness 652 of the
lanthanide doped TiOX layer in FIG. 6C has increased from
that of the Ti/lanthanide layer deposited on substrate 600 in
FIG. 6A, due to the oxidation of the Ti/lanthanide layer.
[0076]
In an embodiment, the processing variables for the
mixed plasma oxidation include a loW ion bombardment
energy of less than about 7 eV, a high plasma density above
1012/cm3 and a loW electron temperature beloW about 1.3 eV.
In another embodiment, the substrate temperature is main
dielectric ?lm has a dielectric constant ranging from about
50 to about 110. The ?rst evaporation rate can also be
controlled such that the Ti can be evaporated at a rate
ranging from about 0.2 nm/sec to about 0.5 nm/sec. Addi
tionally, the second rate can be controlled such that the
lanthanide is evaporated at a rate ranging from about 0.2
nm/sec to about 0.5 nm/sec.
3% is used at a pressure of about 1 Torr. In one embodiment,
microWaves having a frequency of about 8.3 GHZ and a
poWer density of about 4 W/cm2 are used. The oxidation
process can provide a groWth rate of about 1.5 nm/min.
[0072]
[0077] The loW temperature mixed plasma oxidation pro
Once the Ti ?lm doped With a lanthanide is formed
on the substrate 210, the ?lm is processed by plasma
oxidation. The plasma oxidation system 300 of FIG. 3 can
be included as part of an overall processing system including
evaporation system 200 of FIG. 2. To avoid contamination
of the surface of the Ti/lanthanide ?lm, plasma oxidation
system 300 can be connected to evaporation system 200
using sealable connections to maintain the substrate, Which
is substrate 210 in FIG. 2 and substrate 310 of FIG. 3, in an
tained at about 400° C. In another embodiment, a mixed gas
consisting of krypton and oxygen With the oxygen content at
cess described above alloWs the deposited layer to be
oxidiZed at a loW temperature. The mixed plasma process in
one embodiment is performed at approximately 400° C. in
contrast to prior thermal oxidation processes that are per
formed at approximately 1000° C.
[0078] A dielectric ?lm of TiOX doped With the lanthanide
appropriate environment betWeen Ti/lanthanide evaporation
can be selectively groWn With lanthanide doping in the range
from about 5% to about 40% of the lanthanide. Further,
controlling the ?rst rate and the second rate of evaporation
processing and plasma oxidation. Other means as are knoWn
to those skilled in the art can be employed for maintaining
groWing on substrate 210 an amorphous TiOX ?lm doped
an appropriate environment betWeen different processing
folloWed by oxidation by a Kr/oxygen plasma provides for
procedures.
With a lanthanide, Where the dielectric ?lm has a dielectric
constant ranging from about 50 to about 110.
[0073] FIGS. 6A-6C shoW a loW temperature plasma
oxidation process using plasma oxidation system 300 of
lanthanide doped TiOX dielectric ?lm includes evaporating a
FIG. 3 in one embodiment to form a layer of lanthanide
Ti source at a ?rst rate using a ?rst electron gun, evaporating
doped TiOX. FIG. 6A shoWs an embodiment of a Ti/lan
thanide layer 610 deposited on a substrate 600 having an
gun, controlling the ?rst rate and the second rate to deposit
substrate interface 620, according to the teachings of the
present invention. Ti/lanthanide layer 610 is deposited on
substrate 600 by electron beam evaporation, as discussed
above, providing a ?lm With an outer surface 630. Layer 610
is deposited over a body region of a transistor, hoWever the
layers may be deposited on any surface Within the scope of
the invention.
[0079]
In another embodiment, a method for forming a
a lanthanide source at a second rate using a second electron
a ?lm on a substrate, bombarding a surface of the substrate
With ions during evaporation of the Ti and the lanthanide,
and oxidiZing the ?lm using atomic oxygen generated in a
plasma, Wherein the dielectric ?lm contains lanthanide
doped TiOX. The lanthanide can be selected from a group
consisting of Nd, Tb, and Dy. In one embodiment, the
dielectric ?lm is groWn With a predetermined percentage of
Jun. 9, 2005
US 2005/0124174 A1
lanthanide doping. After an initial Waiting period, bombard
ing substrate surface 212 With ions during the Ti evaporation
and/or the lanthanide evaporation includes bombarding sub
strate surface 212 during any part of the Ti and the lan
thanide evaporation process. The various operating param
at substrate surface 212 by regulating the amount of oZone
directed to ioniZer 245 by controlling the mass-?oW con
troller 275.
eters of the embodiments discussed above can be realized in
further embodiments that do not use an ioniZer ring to
reactor chamber 205 in Which a ?lm is being formed on
supplement the substrate surface With oxygen.
[0080]
In another embodiment, a method for forming a
addition, the computer can regulate supplementing oxygen
[0084]
The computer can also control the environment of
substrate 210. The computer regulates the pressure in reac
tion chamber 205 Within a predetermined pressure range by
controlling vacuum pump 295 and mass-?oW controller 298.
gun, controlling the ?rst rate and the second rate to deposit
The computer also regulates the temperature range for
substrate 210 Within a predetermined range by controlling
heater 220. Further, the computer controls unWanted mate
rial from reaching the substrate surface 212 by controlling
a ?lm on a substrate, supplementing With oxygen using an
shutter 250.
lanthanide doped TiOX dielectric ?lm includes evaporating a
Ti source at a ?rst rate using a ?rst electron gun, evaporating
a lanthanide source at a second rate using a second electron
ioniZer ring during the deposition of the Ti and the lan
thanide, and oxidiZing the ?lm using atomic oxygen gener
ated in a plasma, Where the dielectric ?lm contains lan
thanide doped TiOX. The lanthanide can be selected from a
group consisting of Nd, Tb, and Dy. In one embodiment, the
dielectric ?lm is groWn With a predetermined percentage of
lanthanide doping. The various operating parameters of the
embodiments discussed above can be realiZed in further
embodiments that do not use ion assistance in the formation
of the Ti/lanthanide ?lm.
[0081] The lanthanide doped TiOX dielectric layer groWn
according to these various embodiments Will provide
smoother surfaces than expected from other current meth
ods, Which translates to higher breakdown electric ?elds and
loWer leakage currents. Additionally, the oxide formation
across the substrate is more uniform than With other meth
ods.
[0082]
[0085] Receiving information from thickness/rate control
265, and controlling electron gun devices 230, 235, ion gun
240, and ioniZer 245, the computer controls a ?rst rate for Ti
evaporation and a second rate for lanthanide evaporation to
selectively groW a Ti ?lm doped in the range from about
10% to about 30% of the lanthanide. Further, the computer
can control the ?rst rate and the second rate such that
subsequent oxidation results in the groWth of an amorphous
TiOX ?lm doped With a lanthanide in the range of about 5%
to about 40% of the lanthanide, Where the TiOX ?lm has a
dielectric constant ranging from about 50 to about 110. The
computer can also control the elements of evaporation
system 200 to achieve the operating parameters as previ
ously discussed in the embodiments for forming a Ti/lan
thanide ?lm.
[0086]
Once the Ti/lanthanide ?lm is processed, the sub
strate 210 of FIG. 2 becomes substrate 310 to be oxidiZed
FIG. 7 illustrates a How diagram of elements for an
embodiment of a computeriZed method to process a dielec
tric ?lm containing lanthanide doped TiOX, according to the
teachings of the present invention. In this embodiment, a
computeriZed method of forming a dielectric ?lm includes
controlling an environment of a reaction chamber, at block
705, controlling evaporation of a Ti source in the reaction
chamber at a ?rst rate, at block 710, controlling evaporation
of a lanthanide source in the reaction chamber at a second
rate, at block 715, controlling the ?rst rate and the second
rate to deposit a ?lm on a substrate, Where the ?lm contains
Ti doped With the lanthanide, at block 720, and controlling
oxidation of the ?lm using atomic oxygen generated in a
plasma to form a dielectric ?lm containing TiOX doped With
the lanthanide, at block 725. Controlling the evaporation
rates alloWs the lanthanide to be selectively doped into the
Ti ?lm Within a predetermined range for the percentage of
the lanthanide in the ?lm. An embodiment of this method
can be realiZed using evaporation system 200 of FIG. 2 and
in the microWave excited plasma oxidation system 300 of
FIG. 3. Further, as With evaporation system 200, in one
embodiment, the elements of plasma oxidation system 300
are controlled by the computer that controls evaporation
system 200. Alternately, plasma oxidation system 300 can be
controlled by a separate computer.
[0087] The computer controls microWave generator 325
that supplies the microWaves in reaction chamber 305. It
also regulates heater 320 to control the temperature of
substrate 310. Though the gas inlets and vacuum ports With
their associated mass-?oW controllers are not shoWn in FIG.
3, these elements are regulated by the computer to control
the plasma parameters and pressure in reaction chamber 305.
[0088]
For convenience, the individual control lines to
elements of evaporation system 200, and plasma oxidation
system 300, as Well as a computer, are not shoWn in FIGS.
2 and 3. The above descriptions of the computer control in
conjunction With FIGS. 2, 3 provide information for those
plasma oxidation system 300 of FIG. 3, Where the controls
for the individual elements of evaporation system 200 and
dielectric layer containing lanthanide doped TiOX using a
the individual elements of plasma oxidation system 300 are
computeriZed method as described herein.
coupled to a computer, not shoWn in FIG. 200 or FIG. 300.
[0083] The computer provides control of the Ti evapora
tion by regulating the operation of electron gun device 230
by controlling electron gun control 232. Likewise, the
computer provides control of the lanthanide evaporation by
regulating the operation of electron gun device 235 by
controlling electron gun control 237. Further, the computer
skilled in the art to practice embodiments for forming a
[0089] A computer for controlling the elements of evapo
ration system 200 of FIG. 2 and plasma oxidation system
300 of FIG. 3 operates under computer-executable instruc
tions to perform a method for forming a dielectric ?lm that
can include controlling an environment of a reaction cham
ber, controlling evaporation of a Ti source in the reaction
chamber at a ?rst rate, controlling evaporation of a lan
can control ion gun controller 285 and mass-?oW controller
thanide source in the reaction chamber at a second rate,
290 to regulate the ion beam generated by ion gun 240. In
controlling the ?rst rate and the second rate to deposit a ?lm
Jun. 9, 2005
US 2005/0124174 A1
on a substrate, Where the ?lm contains Ti doped With the
[0093] The doping of the TiOX layer With a lanthanide
lanthanide, and controlling oxidation of the ?lm using
occurs as a substitution of a lanthanide atom for a Ti atom.
atomic oxygen generated in a plasma to form a dielectric
The resultant doped TiOX layer is a layer of amorphous
?lm containing lanthanide doped TiOX. Controlling the
Ti1_yLyOX, Where L is a lanthanide. Controlling the evapo
ration of Ti, the evaporation of the selected lanthanide, and
the plasma oxidation alloWs a Ti1_yLyOX, or lanthanide
doped TiOX, dielectric layer to be formed Where the lan
thanide, L, can range from about 5% to about 40% of the
evaporation rates alloWs the lanthanide to be selectively
doped into the Ti ?lm Within a predetermined range for the
percentage of the lanthanide in the ?lm. Using a computer
to control parameters for groWing the dielectric ?lm pro
vides for processing the dielectric ?lm over a Wide range of
parameters alloWing for the determination of an optimum
parameter set for the evaporation system/plasma oxidation
system used. The computer-executable instructions can be
provided in any computer-readable medium. Such com
puter-readable medium includes, but is not limited to, ?oppy
disks, diskettes, hard disks, CD-ROMS, ?ash ROMS, non
volatile ROM, and RAM.
[0090]
The embodiments described herein provide a pro
cess for groWing a dielectric ?lm having a Wide range of
useful equivalent oxide thickness, te
associated With a
dielectric constant in the range from about 50 to about 110.
The teq range in accordance With embodiments of the present
invention are shoWn in the folloWing:
Physical
Physical
Physical
Physical
Thickness
Thickness
Thickness
Thickness
t=1.0 nrn
t=5.0 nrn
t=100.0 nm
t=350 nrn
(1.0 X 101 A)
(5.0 X 101 A)
(1 X 103 A)
(3.5 X 103 A)
K
teq (A)
tag (A)
tag (A)
tag (A)
50
75
100
110
0.78
0.52
0.39
0.35
3.90
2.60
1.95
1.77
78.00
52.00
39.00
35.45
273.00
182.00
136.50
124.09
dielectric layer formed. Such TiOX layers doped With Nd, Tb,
or Dy formed by ion bean assisted electron beam evapora
tion folloWed by plasma oxidation can provide the reduced
leakage current and increased breakdoWn electric ?elds
mentioned above.
[0094] A transistor 100 as depicted in FIG. 1 can be
formed by forming a source region 120 and a drain region
130 in a silicon based substrate 110 Where the source region
120 and the drain region 130 are separated by a body region
132. The body region 132 separated by the source 120 and
the drain 130 de?nes a channel having a channel length 134.
Ti is evaporated using an electron gun at a controlled rate.
Alanthanide selected from a group consisting of Nd, Tb, and
Dy is evaporated using a second electron gun at a second
controlled rate. Evaporating the lanthanide source is begun
substantially concurrent With evaporating Ti, forming a ?lm
140 containing Ti and lanthanide on the body region, While
the body region is bombarded With Ar ions shortly after the
deposition of Ti on the body region has begun. Film 140, or
layer 140, is oxidiZed using a Kr/oxygen plasma. A gate is
formed over the gate dielectric 140. Typically, forming the
gate includes forming a polysilicon layer, though a metal
gate can be formed in an alternative process. Forming the
substrate, source region, drain region, and the gate is per
formed using standard processes knoWn to those skilled in
the art. Additionally, the sequencing of the various elements
of the process for forming a transistor is conducted With
[0091] The relatively large dielectric constant for material
layers of lanthanide doped TiOX alloWs for the engineering
standard fabrication processes, also as knoWn to those
skilled in the art.
of dielectric ?lms having a physical thickness in the 100 nm
[0095] The method for forming a lanthanide doped TiOX in
Further,
(1000 groWing
range, While
ultra-thin
achieving
layers,a or
teq ?lms,
of lessofthan
lanthanide
100
various embodiments can be applied to other transistor
structures having dielectric layers. FIG. 8 shoWs an embodi
ment of a con?guration of a transistor 800 capable of being
doped TiOX provides for teq in the range of several mono
layers. From above, it is apparent that a ?lm containing
lanthanideodoped OTiOX can be attained With a teq ranging
from 1.5 A to 5 A. Further, such a ?lm can provide a teq
signi?cantly less than 2 or 3 A, even less than 1.5 A.
[0092] Further, dielectric ?lms of lanthanide doped TiOX
formed by ion assisted electron beam evaporation folloWed
plasma oxidation can provide not only ultra thin teq ?lms, but
also ?lms With relatively loW leakage current. In addition to
using ion assisted electron beam evaporation, attainment of
relatively loW leakage current is engineered by doping With
lanthanides selected from a group consisting of Nd, Tb, and
Dy. Though a layer of undoped TiOX is typically amorphous,
Which assists the reduction of leakage current, evaporating
these lanthanides during the evaporation of the Ti layer
provides a layer for oxidation that subsequently yields a
doped amorphous TiOX With enhanced leakage current char
fabricated, according to the teachings of the present inven
tion. In the embodiment of FIG. 8, transistor 800 includes
a silicon based substrate 810 With a source 820 and a drain
830 separated by a body region 832. The body region 832
betWeen the source 820 and the drain 830 de?nes a channel
region having a channel length 834. Located above the body
region 832 is a stack 855 including a gate dielectric 840, a
?oating gate 852, a ?oating gate dielectric 842, and control
gate 850. The gate dielectric 840 can be formed as described
above With the remaining elements of the transistor 800
formed using processes knoWn to those skilled in the art.
Alternately, both the gate dielectric 840 and the ?oating gate
dielectric 842 can be formed as dielectric layers containing
lanthanide doped TiOX in various embodiments as described
herein.
acteristics. Leakage currents on the order of 10'7 A/cm2 or
[0096] The embodiments of methods for forming lan
thanide doped TiOX dielectric ?lms can also be applied to
smaller in TiOX layers doped With Nd, Tb, or Dy can be
forming capacitors in various integrated circuits, memory
attained, Which are orders of magnitude smaller than for
undoped TiOX. Further, the breakdoWn electric ?elds are
devices, and electronic systems. In one embodiment for
forming a capacitor, a method can include forming a ?rst
conductive layer, evaporating a Ti source at a ?rst rate,
evaporating a lanthanide source at a second rate, controlling
several factors larger for layers of TiOX doped With Nd, Tb,
or Dy than for layers of undoped TiOX.