3/10/2013
EECS 498/598: Nanocircuits and Nanoarchitectures
Lecture 1: Introduction to Nanotelectronic Devices (Sept. 5)
Lectures 2: ITRS Nanoelectronics Road Map (Sept 7)
Lecture 3: Nanodevices; Guest Lecture by Prof. Lu (Sept. 12)
EECS 498/598: Nanocircuits and
Nanoarchitectures
Lecture 4: Overview of Photonics Device; Guest Lecture by Prof. Ku (Sept. 14)
Lectures 5: Quantum Device Modeling for Nano-CAD (Sept 19)
Lectures 6-8: RTD-Based Digital Circuit Design (Sept 21, 26, 28)
Lectures 9-12: Class Presentations (ITRS) (Sept. 30, Oct. 3, Oct. 5, Oct. 10)
Instructor: Prof. Pinaki Mazumder
Tuesday and Thursday @ 3:00 – 4:30 p.m.
Lecture 1: Introduction to Nanoelectronics
Fall 2006
Prof. P. Mazumder
Lecture 13: Cellular Nonlinear Network Nanoarchitectures (Oct 12)
Lecture 14: Quantum-Dot Based Logic and Local Computational Models (Oct 19)
Lectures 15 & 16: Molecular Electronics Circuits (Oct 24, Oct 26)
Lectures 17-21: Class Presentations (Oct. 31, Nov 2, Nov 7, Nov 9, Nov 14)
Lecture 22: Nano Tube/Nano Wire Based Digital Logic Design (Nov 16)
Lectures 23 & 24: Quantum Cellular Array Based Logic Circuits (Nov 21, Nov 28)
Lectures 25: Miscellaneous Topics like Photonics, Plasmonics, Quantum Computing, etc. (Nov 28)
Lectures 26-29: Project Presentations (Dec 1, Dec 5, Dec 7, Dec 12)
Fall 2006
Prof. P. Mazumder
Fall 2006
Prof. P. Mazumder
Lecture #1
How small is Nano? (A movie)
What is Nanotechnology?
What is Nanoelectronics?
What are Emerging Devices?
About the Course
Fall 2006
Prof. P. Mazumder
1
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Power of 10
A sense of
nanoscale
X0.1
x1
x.001
x.01
X1
Fall 2006
Prof. P. Mazumder
Fall 2006
Prof. P. Mazumder
Courtesy Mark Rattner
Definition of Nanotechnology
“Working at the atomic, molecular, supermolecular levels, in the length scale
approximately 1-10 nm range, in order to
understand and create materials, devices and
systems with fundamentally new properties
and functions because of their small
structure”
--- Mike Roco, National
Nanotechnology Initiative (NNI).
However, Intel prefers the range from 1-100 nm so
that conventional CMOS devices (< 90 nm) are part
of Nanoelectronics Evolution.
Fall 2006
Prof. P. Mazumder
Fall 2006
Prof. P. Mazumder
2
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Multiple Perspectives of
Roadmap for Nanoelectronics
Intel Device
Roadmap
• Intel Perspective (shrinking driven)
 Nano-scale CMOS, Nanowire FET,
Carbon Nano Tube (CNT) FET
• Brick Wall Perspective  Post
CMOS Devices in post-shrinking era
• Concurrent Advancements (ITRS
Roadmap)
• Evolutionary v. Revolutionary Devices
Fall 2006
Prof. P. Mazumder
Fall 2006
Intel keeps startling the
Nano world by inventing
yet smaller CMOS FET’s
Fall 2006
Prof. P. Mazumder
10,000 times faster
than CMOS
Prof. P. Mazumder
Fall 2006
Prof. P. Mazumder
3
3/10/2013
DARPA Si Nanoelectronics Research Vision
1000
Cost (uc/device)
Silicide,
Local
interconnect
Cu
100
100
Low k
SOI
QMOS
10
10
Feature Size
Production Yr.
1
Vgs = 5
Vgs = 4
250
1997
INTEL Model
“No known solutions”
-SIA ‘97
180
1999
150
2001
130
2003
Delay x Power (fJ/device)
1000
1
90
2006
60
2009
40
2012
Change of Electronic Transport Mode
Prof. P. Mazumder
V =3
Fall 2006
gs
Fall 2006
Prof. P. Mazumder
Fall 2006
Prof. P. Mazumder
Vgs = 2
Vgs = 1
1
2
3
Brick Wall Perspective
RTD
Single Electronics
1/Size
RTD
Vertical Gate
Structure
RTD
Molecular Switch
Bulk
CMOS
SOI
Brick-wall
Model
Today
Fall 2006
2020
Prof. P. Mazumder
Nanotubes
2040
Source: TI, Denny Buss, ICECS2001
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CONCURRENT ADVANCEMENTS
Evolution of CMOS and
Revolutionary Devices
Concurrent Model of the Roadmap
Intel Tri-gate FET
Fall 2006
Fall 2006
Prof. P. Mazumder
Prof. P. Mazumder
Fall 2006
Fall 2006
Prof. P. Mazumder
Prof. P. Mazumder
ITRS
IBM researchers use a single
carbon nanotube bundle (blue)
to fashion a logic circuit on a
substrate patterned with three
gold electrodes (yellow). By
selectively removing part of
a protective polymer coat (PMMA),
the group is able to form the needed
p-type and n-type transistors within
the single nanotube bundle.
5
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Prof. P. Mazumder
Fall 2006
Outer
Barriers
Prof. P. Mazumder
Fall 2006
Quantum Cellular Array (QCA)
 Each cell is occupied by two electrons.
 There are two ground-state configurations,
Quantum Cellular Array (QCA)
Quantum Dots can be configured into various types of logic blocks
Like the majority gate, full adder, memory, registers, etc.
corresponding to “polarizations” of +1 and –1.
Inter-dot
Barriers
Cell (Square) and Quantum Dot (Circle)
 Majority logic of QCA is used
cell 1
cell 2
cell 5
cell 4
Fall 2006
P= -1
Logic 0
Prof. P. Mazumder
P= +1
Logic 1
cell 3
Fall 2006
Prof. P. Mazumder
Diagram by P. Wu
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Fall 2006
Prof. P. Mazumder
Fall 2006
Prof. P. Mazumder
Fall 2006
Prof. P. Mazumder
Fall 2006
Prof. P. Mazumder
7
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EECS 498/598: Nanocircuits and Nanoarchitectures
Evaluation Criteria:
Lecture 1: Introduction to Nanotelectronic Devices (Sept. 5)
Lectures 2: ITRS Nanoelectronics Road Map (Sept 7)
Lecture 3: Nanodevices; Guest Lecture by Prof. Lu (Sept. 12)
Lecture 4: Overview of Photonics Device; Guest Lecture by Prof. Ku (Sept. 14)
Lectures 5: Quantum Device Modeling for Nano-CAD (Sept 19)
Lectures 6-8: RTD-Based Digital Circuit Design (Sept 21, 26, 28)
Lectures 9-12: Class Presentations (ITRS) (Sept. 30, Oct. 3, Oct. 5, Oct. 10)
Lecture 13: Cellular Nonlinear Network Nanoarchitectures (Oct 12)
1.
2.
3.
In-class presentation (2)
Written assignment related to presentation
Final project  To be discussed
Final Report
Presentation
Grading: Average grade: A- (undergrad)
Average grade: A  A- (grad)
Lecture 14: Quantum-Dot Based Logic and Local Computational Models (Oct 19)
Lectures 15 & 16: Molecular Electronics Circuits (Oct 24, Oct 26)
Lectures 17-21: Class Presentations (Oct. 31, Nov 2, Nov 7, Nov 9, Nov 14)
Lecture 22: Nano Tube/Nano Wire Based Digital Logic Design (Nov 16)
Lectures 23 & 24: Quantum Cellular Array Based Logic Circuits (Nov 21, Nov 28)
Lectures 25: Miscellaneous Topics like Photonics, Plasmonics, Quantum Computing, etc. (Nov 28)
Lectures 26-29: Project Presentations (Dec 1, Dec 5, Dec 7, Dec 12)
Fall 2006
Prof. P. Mazumder
END OF LECTURE 1
Points Allocation: Two presentations (30%)
Two assignments (20%)
Final Project
(50%)
(distribution is subject to change)
Fall 2006
Prof. P. Mazumder
EECS 498/598: Nanocircuits and
Nanoarchitectures
Instructor: Prof. Pinaki Mazumder
Tuesday and Thursday @ 3:00 – 4:30 p.m.
Lecture 2: ITRS Roadmap & Nano Devices
Fall 2006
Prof. P. Mazumder
Fall 2006
Prof. P. Mazumder
8
3/10/2013
Nanotechnology Industry Segmentation
ITRS ROADMAP FOR
EMERGINE MODELS
& TECHNOLOGIES
Information
Technology
20%
Hybrid Materials
34%
Semiconductor
17%
Other
10%
Medical/Healthcare
8%
• MEMORY ARRAYS
• LOGIC CIRCUITS
• ARCHITECTURES
Nano MEMS
11%
Fall 2006
Prof. P. Mazumder
RISK & PAYOFF;
OPPORTUNITIES
Prof.&
P. Mazumder
Fall 2006CHALLENGES
Fall 2006
Prof. P. Mazumder
Fall 2006
ITRS 2005 Road Map
Prof. P. Mazumder
9
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< 30 =  (PC*RC)
< 40
<50
>50
Fall 2006
Prof. P. Mazumder
Prof. P.2Mazumder
Fall 2006
Performance
Criterion (PC): 3  better,
 comparable, 1  worse than CMOS
Risk Criterion (RC): 3  Low Risk, 2  Moderate Risk, 1  High Risk
Evaluation Criteria for
an Emergent Technology
< 30 =  (PC*RC)
< 40
<50
>50
Scalability
CMOS Architecture
Compatibility
CMOS Compatibility
Prof.to,
P. 2Mazumder
superior
 comparable
Criteria: 3 
with, 1  inferior to CMOS
Risk Criteria: 3  Low Risk, 2  Moderate Risk, 1  High Risk
Fall
2006
Performance
Fall 2006
Performance
RTD
& QD
Energy Efficiency
Room Temperature
Operation
Prof. P. Mazumder
Operational Reliability
10
3/10/2013
Evaluation Criteria for
an Emergent Technology
Scalability
CMOS Architecture
Compatibility
Performance
Molecular
Spin FET
CMOS Compatibility
RTD
& QD
Energy Efficiency
CNT
Fall 2006
Fall 2006
Room Temperature
Operation
Operational
Reliability
Prof.
P. Mazumder
Prof. P. Mazumder
SET
Fall 2006
Prof. P. Mazumder
Fall 2006
Prof. P. Mazumder
11
3/10/2013
Fall 2006
Prof. P. Mazumder
Fall 2006
Prof. P. Mazumder
Fall 2006
Prof. P. Mazumder
Fall 2006
Prof. P. Mazumder
12
3/10/2013
State 0
State 1
Prof. P. Mazumder
Fall 2006
Fall 2006
Prof. P. Mazumder
Fall 2006
Prof. P. Mazumder
Silicon Nanoelectronics — Nano-CMOS
Silicon Story
(nm)
10000
1.E+15
1015
DRAM
1.4 Times/Year
Gate Length
800
500
350
250 180
100
64GB
(2015)
130 100
70
50
1.E+12
1012
Neuron Number
in Brain
35
25 18
Increasing Technology difficulty
10
1.E+13
1013
1.E+11
1011
1.E+10
1010
1.E+09
109
1.E+08
108
1.E+07
107
1.E+06
106
1
1989
Fall 2006
1990
1993
1996
1999
2002
2005
2008
2011
2014
2017
2020
2023
1.E+05
105
Transistor Number per chip
1000
1.E+14
1014
1TB1 TB
(2023)
(2023)
2026
Prof.year
P. Mazumder
Source: IEEE C&D Mag. 2001
13
3/10/2013
Silicon Nanoelectronics — Nano-CMOS
CPU with Multimedia Capability
100b
Number of transistors
on a chip in thousands
10b
100-billion
transistors
Moore’s law prediction
processors
1b
100,000
1-billion
transistors
10,000
1,000
Pentium
III Xeon
80386
80286
80486
100
4004
8086
10
Pentium III
Pentium II
Pentium Pro
Pentium
8080
1
Fall 2006
'70
'75
'80
'85
'90
'00
'05
Prof. '95
P. Mazumder
'10
Nanoelectronics and Gigascale Systems Lab.
'15
‘20
‘25
‘30
Fall 2006
Prof. P. Mazumder
Fall 2006
Prof. P. Mazumder
Courtesy: P. Wu
Nanoarchitectures
Fall 2006
Prof. P. Mazumder
14
3/10/2013
Fall 2006
Prof. P. Mazumder
Prof. P. Mazumder
Fall 2006
Evaluation Criteria for
an Emergent Technology
Scalability
CMOS Architecture
Compatibility
Performance
Molecular
Spin FET
CMOS Compatibility
RTD
& QD
Energy Efficiency
CNT
Fall 2006
Prof. P. Mazumder
Fall 2006
Room Temperature
Operation
Operational
Reliability
Prof.
P. Mazumder
SET
15
3/10/2013
Evaluation Criteria for
an Emergent Technology
Monochromatic Image Processor
1.0
R
V(fm,fn)/I B
Scalability
CMOS Architecture
Compatibility
0.5
Performance
0.0
0.5
0.4
0.1
0.3
0.2
fn
Molecular
Spin FET
RTD
& QD
CMOS Compatibility
Fall 2006
0.2
0.4
0.1
fm
0.5
V ( z m , z n )  Z-transform of a QD pair =
Energy Efficiency
I R12
2 1  cos 2 f m   2 1  cos 2 f n   
CNT
Room Temperature
Operation
Operational
Reliability
Prof.
P. Mazumder
0.3
Connecting Resistance Defines the
Mutual Voltage between a pair of QD’s
SET
Fall 2006
Prof. P. Mazumder
Nanoscale
Nonlinear Circuit Theory
Edge Detection by QDA
Gray  Binary
Conversion
0 ns
1 ns
2 ns
Vertical Line Detection (VLD)
0 ns
Fall 2006
6 ns
Prof. P. Mazumder
5 ns fabricated and tested
6 ns
Image Processor is being
under a NIRT project
Fall 2006
Prof. P. Mazumder
16
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Fall 2006
Prof. P. Mazumder
17