Minimum Dynamic Power
CMOS Circuits
Vishwani D. Agrawal
Rutgers University, Dept. of ECE
Piscataway, NJ 08854
http://cm.bell-labs.com/cm/cs/who/va
Collaborators: M. L. Bushnell and T. Raja, Rutgers University
(Support from NSF)
May 28, 2003
Minimum Dynamic Power CMOS
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Power in a CMOS Gate
VDD = 5V
IDD
Ground
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Problem Statement
• Design a digital circuit for minimum
transient energy consumption by
eliminating hazards
Ref: Agrawal (`97), Agrawal et al. (`99)
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Theorem 1
• For correct operation with minimum
energy consumption, a Boolean gate
must produce no more than one
event per transition
Ref: Agrawal, et al., Proc. VLSI Design’99
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Theorem 2
• Given that events occur at the input of a gate
(inertial delay = d ) at times t1 < . . . < tn , the
number of events at the gate output cannot
exceed
tn – t1
min ( n , 1 + -------d
)
tn - t1 + d
t1
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t2
t3
d
tn
Minimum Dynamic Power CMOS
tn +
time
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Minimum Transient Design
• Minimum transient energy condition
for a Boolean gate:
| t i - tj | <
d
Where ti and tj are arrival times of input
events and d is the inertial delay of gate
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Linear Program (LP)
• Variables: gate and buffer delays
• Objective: minimize number of
buffers
• Subject to: overall circuit delay
• Subject to: minimum transient
condition for multi-input gates
• AMPL, MINOS 5.5 (Fourer, Gay and
Kernighan)
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Limitations of This LP
• Constraints are written by path
enumeration.
• Since number of paths in a circuit is
exponential in circuit size, the
formulation is infeasible for large
circuits.
• Example: c880 has 6.96M constraints.
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A New LP Model
• Introduce two new variables per gate
output:
• ti Earliest time of signal transition at gate i.
• Ti Latest time of signal transition at gate i.
t1, T1
.
.
.
ti, Ti
tn, Tn
Ref: Raja et al. (`03)
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New Linear Program
• Gate variables d4 . . . d12
• Buffer Variables d15 . . . d29
• Corresponding window variables t4 . . . t29
and T4 . . . T29.
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Multiple-Input Gate Constraints
For Gate 7:
Input windows:
t5
T5
t6
T5+d7
t6+d7 T6+d7
T6
T7 > T5 + d7;
T7 > T6 + d7;
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Output
t5+d7
windows:
t7
t7 < t5 + d7;
t7 < t6 + d7;
Minimum Dynamic Power CMOS
T7
d7 > T7 - t7;
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Single-Input Gate Constraints
Buffer 19:
T16 + d19 = T19 ;
t16 + d19 = t19 ;
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Overall Delay Constraints
T11 < maxdelay
T12 < maxdelay
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Why New Model is Superior?
• Path constraints from old model:
•
•
2 × 2 × … 2 = 2n paths between an I/O pair
For new model, a single constraint per PO
controls I/O delay.
For new model, number of minimum energy
constraints for each gate depends on gate
inputs.
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Number of constraints
Comparison of Constraints
6.96x106
3,611
c880
Number of gates in circuit
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Results: 1-Bit Adder
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Estimation of Power
• Circuit is simulated by an event-driven
simulator for both optimized and unoptimized gate delays.
• All transitions at a gate are counted
as Events[gate].
• Power consumed  Events[gate] x #
of fanouts.
• Ref: “Effects of delay model on peak
power estimation of VLSI circuits,”
Hsiao, et al. (ICCAD`97).
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Color codes for number of transitions
Original 1-Bit Adder
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Color codes for number of transitions
Optimized 1-Bit Adder
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Benchmark Circuits
Circuit
Maxdel.
(gates)
No. of
Buffers
Normalized Power
Average
Peak
C432
17
34
95
66
0.72
0.62
0.67
0.60
C880
24
48
62
34
0.68
0.68
0.54
0.52
C6288
47
94
294
120
0.40
0.36
0.36
0.34
c7552
43
86
366
111
0.28*
0.26*
0.24*
0.22*
* Corrected data
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Results: 4-Bit ALU
maxdelay
Buffers inserted
7
10
12
15
5
2
1
0
Power Savings :
Peak = 33 %,
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Average = 21 %
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Physical Design
Gate
Gate
Gate
l/w
l/w
l/w
Gate
l/w
Gate delay modeled as a linear function of gate size, total load
capacitance, and fanout gate sizes (Berkelaar and Jacobs, 1996).
Layout circuit with some nominal gate sizes.
Enter extracted routing delays in LP as constants and solve for gate
delays.
Change gate sizes as determined from a linear system of equations.
Iterate if routing delays change.
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Power Dissipation of ALU4
Energy in nanojoules
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1 micron CMOS, 57 gates, 14 PI, 8 PO
100 random vectors simulated in Spice
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Original ALU
delay ~ 3.5ns
5
4
3
Minimum energy ALU
delay ~ 10ns
2
1
0
0.0
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0.5
1.0
microseconds
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1.5
2.0
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ALU: Original and Optimized
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•
•
•
•
•
•
•
References
R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling
Language for Mathematical Programming, South San
Francisco: The Scientific Press, 1993.
M. Berkelaar and E. Jacobs, “Using Gate Sizing to Reduce
Glitch Power,” Proc. ProRISC Workshop, Mierlo, The
Netherlands, Nov. 1996, pp. 183-188.
V. D. Agrawal, “Low Power Design by Hazard Filtering,” Proc.
10th Int’l Conf. VLSI Design, Jan. 1997, pp. 193-197.
M. Hsiao, E. M. Rudnick and J. H. Patel, “Effects of Delay Model
in Peak Power Estimation of VLSI Circuits,” Proc. ICCAD, Nov.
1997, pp. 45-51.
V. D. Agrawal, M. L. Bushnell, G. Parthasarathy and R.
Ramadoss, “Digital Circuit Design for Minimum Transient
Energy and Linear Programming Method,” Proc. 12th Int’l Conf.
VLSI Design, Jan. 1999, pp. 434-439.
V. D. Agrawal, “Low Power Circuits Through Hazard Pulse
Suppression,” US Patent 5,983,007, Nov. 9, 1999.
T. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum Dynamic
Power CMOS Circuit Design by a Reduced Constraint Set
Linear Program,” Proc. 16th Int’l Conf. VLSI Design, Jan. 2003.
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Conclusion
•
Obtained an LP constraint-set that is linear in the
size of the circuit. LP solution:
• Eliminates glitches at all gate outputs,
• Holds I/O delay within specification, and
• Combines path-balancing and hazard-filtering to
minimize the number of delay buffers.
•
New LP produces results exactly identical to old
LP requiring exponential constraint-set.
•
Results show peak power reduction up to 78% and
average power savings up to 74%.
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