Review of Module1 1 BINA RAMAMURTHY [email protected] B.Ramamurthy 5/16/2013 Items 2 Please complete exercise #1, activity #1, and exercise #2; enclosed are those slides for your convenience Lab1 formal statement is available; lets review it. Form groups of 2: We need to pair up people who have accounts on Buffalo machine to people who do not have accounts as of now. Claim your ubit account: http://www.buffalo.edu/ubit/service-guides/accounts/your-ubitnameaccount/getting-started-with-your-account/claiming-your-account1.html Lets review the interrupt levels from a sample processor as indicated by Sharat. Lets review the details of thread programming. This skill is required for understanding Embedded Xinu multi-threaded kernel. B.Ramamurthy 5/16/2013 Exercise#1 3 Lets identify 10 embedded systems, realtime systems and realtime/embedded system I will begin with Arduino Uno Example B.Ramamurthy Type; justification 5/16/2013 Activity#1 4 Identify some ECUs in a modern automobile and a possible qualitative requirement. Example B.Ramamurthy Justification 5/16/2013 Exercise #2 5 Automatic vending machine money counter Embedded system (Rs.5 counter) Coins: 1, 2 and 5 rupees: Think of your example 2 S1 S3 1 5 1 5 S2 2 2 S4 5 1 1 2,5 1 2 S0 5 S5+ S5 B.Ramamurthy 5/16/2013 Operating System 6 An general purpose OS can be defined by its functions as: Process/execution manager (Process: unit of schedulabilty) Interface manager Resources / hardware manager Memory Management unit (MMU) IO manager File system manager Each of these units have their own set of “exceptions” or interrupts defined Result is a well-defined set of interrupts and handlers for addressing exceptional situations. B.Ramamurthy 5/16/2013 Operating system Modular View 7 Virtual Mem Comm. Prmtvs Application Server User Processes Shell Hardware + interrupts Directories File sys. Process + primitives Web Server Devices Application Clients B.Ramamurthy Web Clients 5/16/2013 Interrupt Levels (contd.) 8 Class 3 — Context Management 1 FCD Synch. HW Free Context List Depletion (FCX = LCX). 2 CDO Synch. HW Call Depth Overflow. 3 CDU Synch. HW Call Depth Underflow. 4 FCU Synch. HW Free Context List Underflow (FCX = 0). 5 CSU Synch. HW Call Stack Underflow (PCX = 0). 6 CTYP Synch. HW Context Type (PCXI.UL wrong). 7 NEST Synch. HW Nesting Error: RFE with non-zero call depth. Class 4 — System Bus and Peripheral Errors 1 PSE Synch. HW Program Fetch Synchronous Error. 2 DSE Synch. HW Data Access Synchronous Error. 3 DAE Asynch. HW Data Access Asynchronous Error. Class 5— Assertion Traps 1 OVF Synch. SW Arithmetic Overflow. 2 SOVF Synch. SW Sticky Arithmetic Overflow. Class 6 — System Call SYS Synch. SW System Call. Class 7 — Non-Maskable Interrupt 0 NMI Asynch. HW Non-Maskable Interrupt. B.Ramamurthy 5/16/2013 Interrupt Levels 9 Class 0 — MMU 0 VAF Synch. HW Virtual Address Fill. 1 VAP Synch. HW Virtual Address Protection. Note: For VAF and VAP, see also MMU Traps. Class 1 — Internal Protection Traps 1 PRIV Synch. HW Privileged Instruction. 2 MPR Synch. HW Memory Protection Read. 3 MPW Synch. HW Memory Protection Write. 4 MPX Synch. HW Memory Protection Execution. 5 MPP Synch. HW Memory Protection Peripheral Access. 6 MPN Synch. HW Memory Protection Null Address. 7 GRWP Synch. HW Global Register Write Protection. Class 2 — Instruction Errors 1 IOPC Synch. HW Illegal Opcode. 2 UOPC Synch. HW Unimplemented Opcode. 3 OPD Synch. HW Invalid Operand specification. 4 ALN Synch. HW Data Address Alignment. 5 MEM Synch. HW Invalid Local Memory Address. B.Ramamurthy 5/16/2013 How to build “robust” systems? 10 Identify potential faults and exceptions Handle them deterministically by implementing fault/exception/interrupt handlers Also have a default handler for those unknown anomalies In fact, a robust system will have a set of exception handlers, several types for each major module of a system. B.Ramamurthy 5/16/2013 Some Logistics 11 B.Ramamurthy 5/16/2013 Status of connectivity to Buffalo 12 Our first step is to get connectivity to CSE systems Access timberlake.cse.buffalo.edu using putty (secure shell) Next step is to access nexos.cse.buffalo.edu from timberlake This will allow us to do kernel programming Final step is to get full access to UB resources (if that is possible without a 16-digit ID) B.Ramamurthy 5/16/2013 Student Portfolio 13 We will collect all the work that you do for this class as a portfolio. This will be a part of your evaluation. Also once CSE account is ready, you can submit all the work to the CSE submit feature (somewhat like a backup or cloud) You can compile all the items you created in this class and assemble this portfolio. B.Ramamurthy 5/16/2013
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