Circuits
Circuits
• We will build circuits for addition, multiplication and other arithmetic
operations.
• This is actually used! Everywhere!
From a truth table to a formula
p
q
r
output
0
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
From a truth table to a formula
p
q
r
output
0
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
• Let us focus entirely on the rows that output 1!
p
q
r
output
0
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
Focusing on the
st
1
row…
p
q
r
output
0
0
0
1
• Write a formula that is ’1’ only on inputs p =0, q = 0, r = 0.
p
q
r
output
0
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
Focusing on the
st
1
row…
p
q
r
output
0
0
0
1
• Write a simple formula that is ’1’ only on inputs p =0, q = 0, r = 0.
~𝑝 ∧ ~𝑞 ∧ ~𝑟
p
q
r
output
0
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
Focusing on the
th
4
row…
p
q
r
output
0
1
1
1
• Same deal
p
q
r
output
0
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
Focusing on the
th
4
row…
p
q
r
output
0
1
1
1
• Same deal
~𝑝 ∧ 𝑞 ∧ 𝑟
p
q
r
output
0
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
Focusing on the
th
5
row…
p
q
r
output
1
0
0
1
𝑝 ∧ ~𝑞 ∧ ~𝑟
p
q
r
output
0
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
Focusing on the
th
8
row…
p
q
r
output
1
1
1
1
𝑝∧𝑞∧𝑟
How do we combine those simple formulae?
~𝑝 ∧ ~𝑞 ∧ ~𝑟
~𝑝 ∧ 𝑞 ∧ 𝑟
𝑝 ∧ ~𝑞 ∧ ~𝑟
𝑝∧𝑞∧𝑟
How do we combine those simple formulae?
(~𝑝 ∧ ~𝑞 ∧ ~𝑟)
∨
(~𝑝 ∧ 𝑞 ∧ 𝑟) ∨
(𝑝 ∧ ~𝑞 ∧ ~𝑟) ∨
(𝑝 ∧ 𝑞 ∧ 𝑟)
p
q
r
output
0
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
• Outputs 1 if and only if the truth table outputs 1!
How do we combine those simple formulae?
(~𝑝 ∧ ~𝑞 ∧ ~𝑟)
∨
(~𝑝 ∧ 𝑞 ∧ 𝑟) ∨
(𝑝 ∧ ~𝑞 ∧ ~𝑟) ∨
(𝑝 ∧ 𝑞 ∧ 𝑟)
p
q
r
output
0
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
• Outputs 1 if and only if the truth table outputs 1!
• We want to do this in hardware!
Logical gates
• The smallest pieces of hardware that we will examine are called
logical gates.
• Every gate that we encounter will take bits as inputs and will emit one
bit as output.
𝐼1
𝐼2
𝐼𝑛
Gate
𝑂𝑢𝑡
• Those gates can connect to each other in various different ways in
order to create more complex circuits
Our first gate
𝑨
𝒐𝒖𝒕
0
1
1
0
• This gate is known as the inverter.
• It corresponds exactly to the negation operation in propositional logic!
• Where 1, set True.
• Where 0, set False
Our second gate
𝑝
𝑟
𝑞
𝒑
𝒒
𝒓
0
0
0
0
1
0
1
0
0
1
1
1
• Corresponds to:
Conjunction
Disjunction
Our second gate (AND gate)
𝑝
𝑟
𝑞
𝒑
𝒒
𝒓
0
0
0
0
1
0
1
0
0
1
1
1
• Corresponds to:
Conjunction
Disjunction
Our third gate (OR gate)
𝑝
𝑟
𝑞
• Corresponds to logical disjunction (OR)
𝒑
𝒒
𝒓
0
0
0
0
1
1
1
0
1
1
1
1
Exercises
• For the following logical circuits, vote on the Boolean functions of
their inputs to which they correspond.
𝑝
𝑠
𝑟
𝑞 ≡ 𝑝∨𝑠 ∧𝑟
𝑞 ≡ 𝑝∧𝑠 ∨𝑟
𝑞
𝑞 ≡ 𝑝∧𝑠 ∧𝑟
𝑞 ≡ 𝑝∨𝑠 ∨𝑟
Exercises
• For the following logical circuits, vote on the Boolean functions of
their inputs to which they correspond.
𝑝
𝑠
𝑟
𝑞 ≡ 𝑝∨𝑠 ∧𝑟
𝑞 ≡ 𝑝∧𝑠 ∨𝑟
𝑞
𝑞 ≡ 𝑝∧𝑠 ∧𝑟
𝑞 ≡ 𝑝∨𝑠 ∨𝑟
Exercises
𝑎
𝑏
𝑟
𝑞 ≡∼ 𝑎 ∨ 𝑏 ∨ 𝑟
𝑞 ≡∼ 𝑎 ∧ 𝑏 ∧ 𝑟
𝑞
𝑞 ≡ 𝑎∧𝑏 ∧𝑟
𝑞 ≡ 𝑎∨𝑏 ∨𝑟
Exercises
𝑎
𝑏
𝑟
𝑞 ≡∼ 𝑎 ∨ 𝑏 ∨ 𝑟
𝑞 ≡∼ 𝑎 ∧ 𝑏 ∧ 𝑟
𝑞
𝑞 ≡ 𝑎∧𝑏 ∧𝑟
𝑞 ≡ 𝑎∨𝑏 ∨𝑟
Exercises
𝑎
𝑏
𝑟
𝑞 ≡ 𝑎 ∧ ∼ (𝑏 ∨ 𝑟)
𝑞 ≡ 𝑎 ∨ ∼ (𝑏 ∧ 𝑟)
𝑞
𝑞 ≡ 𝑎 ∧ ∼ (𝑏 ∧ 𝑟)
𝑞 ≡ 𝑎 ∧ (∼ 𝑏 ∧ ∼ 𝑟)
Exercises
𝑎
𝑏
𝑟
The circuit above is equivalent to one
where b and r are inverted before an
AND gate!
Watch out for De
Morgan’s law!
𝑞 ≡ 𝑎 ∧ ∼ (𝑏 ∨ 𝑟)
𝑞
𝑞 ≡ 𝑎 ∨ ∼ (𝑏 ∧ 𝑟)
𝑞 ≡ 𝑎 ∧ ∼ (𝑏 ∧ 𝑟)
𝑞 ≡ 𝑎 ∧ (∼ 𝑏 ∧ ∼ 𝑟)
Coming back to our original truth table…
(~𝑝 ∧ ~𝑞 ∧ ~𝑟)
∨ (~𝑝 ∧ 𝑞 ∧ 𝑟) ∨ (𝑝 ∧ ~𝑞 ∧ ~𝑟) ∨ (𝑝 ∧ 𝑞 ∧ 𝑟)
Coming back to our original truth table…
(~𝑝 ∧ ~𝑞 ∧ ~𝑟)
∨ (~𝑝 ∧ 𝑞 ∧ 𝑟) ∨ (𝑝 ∧ ~𝑞 ∧ ~𝑟) ∨ (𝑝 ∧ 𝑞 ∧ 𝑟)
• For each small formula we have a circuit, and we will combine with a 4-input OR gate!
Coming back to our original truth table…
(~𝑝 ∧ ~𝑞 ∧ ~𝑟)
∨ (~𝑝 ∧ 𝑞 ∧ 𝑟) ∨ (𝑝 ∧ ~𝑞 ∧ ~𝑟) ∨ (𝑝 ∧ 𝑞 ∧ 𝑟)
• For each small formula we have a circuit, and we will combine with a 4-input OR gate!
Circuit 1
Circuit 2
Circuit 3
Circuit 4
Circuit 1
(~𝑝 ∧ ~𝑞 ∧ ~𝑟)
𝑝
𝑞
𝑟
Circuit 2
(~𝑝 ∧ 𝑞 ∧ 𝑟)
𝑝
𝑞
𝑟
Circuit 3
(𝑝 ∧ ~𝑞 ∧ ~𝑟)
𝑝
𝑞
𝑟
Circuit 4
(𝑝 ∧ 𝑞 ∧ 𝑟)
𝑝
𝑞
𝑟
Building Adder Circuits
• We want to build circuits that add arbitrarily large binary numbers.
• E.g
10011001
Inputs
+00110011
Output
11001100
Half-Adder
• A half-adder is a circuit that adds two bits together!
𝑋
+𝑌
𝐶𝑆
• (Remember: 𝐶 is the carry bit.)
• Let’s try to build a circuit that computes both S and C!
Truth table
X
Y
S
C
0
0
?
?
0
1
?
?
1
0
?
?
1
1
?
?
Truth table
X
Y
S
C
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
Truth table
X
Y
S
C
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
X
Y
C
S
Truth table
X
Y
S
C
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
X
Y
X
Y
C
S
S
XOR Gate
(“Exclusive OR)
Half-Adder
𝑋
𝐶
𝑌
𝑆
Abstraction: We can now consider the half-adder as a black box
that receives two inputs and emits two outputs.
Abstraction!
𝑋
𝐶
Half-Adder
𝑌
𝑆
Full-Adder
• Now, let’s consider the complete case, where we want to build a
circuit that computes the sum of two 2-digit binary numbers:
PQ
+WX
C S1 S2
• To do this, we also need the ability to add 3 digits, because:
C1
PQ
+WX
C S1 S2
Full-Adder
• Now, let’s consider the complete case, where we want to build a
circuit that computes the sum of two 2-digit binary numbers:
PQ
+WX
C S1 S2
• To do this, we also need the ability to add 3 digits, because:
C1
We will call a circuit
PQ
that adds 3 digits a
full adder
+WX
C S1 S2
We could do the truth table….
PQ
+WX
C S1 S2
P
Q
W
X
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
C
S1
S2
We could do the truth table….
PQ
+WX
C S1 S2
P
Q
W
X
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
C
S1
S2
But it’s time
consuming and we
are all busy people
Constructing a Full-Adder in another way
• We need to build a circuit that computes the sum of 3 digits, e.g P + Q
+R
P
+ Q
• Step 1: Compute C1S1 with a half-adder:
𝑃
𝑄
Half-Adder
𝐶1
𝑆1
Constructing a Full Adder
𝑃
𝐶1
Half-Adder
𝑄
S1
• Step 2: Compute + R
C2S
𝑃
𝑄
𝑅
𝑆1
with another half-adder:
Half-Adder
𝐶1
𝐶2
𝑆1
Half-Adder
𝑆
Constructing a full-adder
𝑃
𝑄
𝑅
𝐶1
𝐶
Half-Adder
𝐶2
𝑆1
Half-Adder
𝑆
• Step 3: Combine 𝐶1 and 𝐶2 with an OR gate to yield the final carry bit
𝐶.
• Think: Why did we choose an OR gate?
Constructing a full-adder
𝑃
𝑄
𝑅
𝐶1
𝐶
Half-Adder
𝐶2
𝑆1
Half-Adder
𝑆
• Step 3: Combine 𝐶1 and 𝐶2 with an OR gate to yield the final carry bit
𝐶.
• Think: Why did we choose an OR gate?
Abstraction
time!
Full Adder Black Box
• 3 inputs, 2 outputs
𝑃
𝑄
𝑅
Full Adder
𝑆
𝐶
2-bit adder
• However, we still have not solved our original problem, which is to
construct a circuit that adds 2-bit numbers!
PQ
+WX
C S1 S2
• So, we need a circuit that takes 4 inputs and emits 3 outputs:
𝑄
𝑋
𝑃
𝑊
𝐶
2-bit adder
𝑆1
𝑆2
Constructing a 2-bit adder
• Step 1: Take care of the right-most column with a half-adder:
C1
PQ
+WX
C S1 S2
𝑄
𝑋
𝑆2
Half-Adder
𝐶1
Constructing a 2-bit adder
• Step 1: Take care of the right-most column with a half-adder:
C1
PQ
+WX
C S 1 S2
𝑄
𝑋
𝑃
𝑊
𝑆2
Half-Adder
𝐶1
Full-Adder
𝑆1
𝐶
• Step 2 (and final): Connect Half-Adder and new inputs to Full-adder
appropriately to produce final circuit.
Constructing a 2-bit adder
• Step 1: Take care of the right-most column with a half-adder:
C1
PQ
+WX
C S 1 S2
𝑄
𝑋
𝑃
𝑊
2-bit adder 𝑆
2
Half-Adder
𝐶1
Full-Adder
• Step 2 (and final): Connect Half-Adder and new inputs to Full-adder
appropriately to produce final circuit.
𝑆1
𝐶
Constructing a 3-bit adder (messy)
C2 C1
APQ
+ BWX
C3 S1S2 S3
𝑄
𝑋
𝑃
𝑊
𝐴
𝐵
Half-Adder
𝑆3
𝐶1
Full-Adder
𝑆2
𝐶2
Full-Adder
𝑆1
𝐶3
Constructing a 3-bit adder (neat)
C2 C1
APQ
+ BWX
C3 S1S2 S3
𝑄
𝑋
𝑃
𝑊
𝐴
𝐵
𝑆3
2-bit adder
𝑆2
𝐶2
Full-Adder
𝑆1
𝐶3
Constructing an n-bit adder (messy)
𝐴1
HA
𝐵1
𝐴2
𝐵2
𝑆1
𝐶1
FA
⋮
𝑆2
𝐶2
• 𝒏 − 𝟏 full adders
• 𝟐 𝒏 − 𝟏 + 𝟏 = 𝟐𝒏 − 𝟏 half-adders
⋮
𝐴𝑛−1
𝐵𝑛−1
𝐴𝑛
𝐵𝑛
𝐶𝑛−1
⋮
𝑆𝑛−1
FA
𝐶𝑛
FA
𝑆𝑛
𝐶
Constructing an n-bit adder (neat)
𝐴1
𝑆1
𝐵1
𝐴2
𝑆2
𝐵2
⋮
(n-1)-bit adder
⋮
𝐴𝑛−1
𝐵𝑛−1
𝐴𝑛
𝐵𝑛
𝑆𝑛−1
𝐶𝑛
FA
𝑆𝑛
𝐶
Other numeric functions
• Addition (have done)
• Multiplication
• Division
• Primality test (test whether a number is prime)
• There are circuits for all of these!
• Computers actually work this way at the base level: they consist of gates.
Fun exercise
• Input: number in binary
• Output: number in unary (!)
𝑩𝟏
𝑩𝟎
𝑼𝟐
𝑼𝟏
𝑼𝟎
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
1
1
1
1
1
𝐵1
𝐵0
Circuit
𝑈2
𝑈1
𝑈0
First micro-circuit
𝑩𝟏
𝑩𝟎
𝑼𝟐
𝑼𝟏
𝑼𝟎
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
1
1
1
1
1
𝑼𝟐 = 𝑩𝟏 ∧ 𝑩𝟎
𝑩𝟏
𝑩𝟎
𝑼𝟐
Second micro-circuit
𝑩𝟏
𝑩𝟎
𝑼𝟐
𝑼𝟏
𝑼𝟎
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
1
1
1
1
1
𝑼𝟏 = (𝑩𝟏 ∧∼ 𝑩𝟎 ) ∨ (𝑩𝟏 ∧ 𝑩𝟎 )
Second micro-circuit
𝑩𝟏
𝑩𝟎
𝑼𝟐
𝑼𝟏
𝑼𝟎
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
1
1
1
1
1
𝑼𝟏 = (𝑩𝟏 ∧∼ 𝑩𝟎 ) ∨ (𝑩𝟏 ∧ 𝑩𝟎 ) = 𝑩𝟏
(from distributive law of conjunction over disjunction!)
𝑩𝟏
𝑼𝟏
Third micro-circuit
𝑩𝟏
𝑩𝟎
𝑼𝟐
𝑼𝟏
𝑼𝟎
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
1
1
1
1
1
𝑼𝟎 = (∼ 𝑩𝟏 ∧ 𝑩𝟎 ) ∨ (𝑩𝟏 ∧∼ 𝑩𝟎 ) ∨ (𝑩𝟏 ∧ 𝑩𝟎 )
Third micro-circuit
𝑩𝟏
𝑩𝟎
𝑼𝟐
𝑼𝟏
𝑼𝟎
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
1
1
1
1
1
𝑼𝟎 = (∼ 𝑩𝟏 ∧ 𝑩𝟎 ) ∨ (𝑩𝟏 ∧∼ 𝑩𝟎 ) ∨ (𝑩𝟏 ∧ 𝑩𝟎 ) = (∼ 𝑩𝟏 ∧ 𝑩𝟎 ) ∨ 𝑩𝟏
𝑩𝟏
𝑩𝟎
𝑼𝟎
Final circuit
𝑩𝟏
𝑩𝟎
𝑼𝟐
𝑼𝟏
𝑼𝟎
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
1
1
1
1
1
𝑼𝟎
𝑩𝟏
𝑩𝟎
𝑼𝟏
𝑼𝟐
Final circuit
𝑩𝟏
𝑩𝟎
𝑼𝟐
𝑼𝟏
𝑼𝟎
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
1
1
1
1
1
𝑼𝟎
𝑼𝟏
𝑩𝟏
𝑩𝟎
𝑼𝟐
2-to-3 binary to
unary decoder!