CSCI206 Activity 40: Introduction to memory
​Name:________________________________
In this problem consider a computer system with a 1
GHz MIPS CPU with a 5-stage pipeline and base CPI =
1 (that is, all instructions besides loads & stores have
the ideal CPI of 1). The latency to access main memory
is 100 ns (for both read and write). The instruction mix
of SPEC CPU2006 is given in Table 1.
1) Assume there is no cache and the CPU stalls in the
Mem stage while waiting for main memory. How many
clock cycles does the mem stage now take?
2) Using the same assumptions from question 1, compute the effective CPI for both ​bzip2 ​and
hmmer​ (including stalls due to memory accesses).
3) Assume we add a cache to the system described in problem 1. It takes 1 cycle to check the cache
for the data. On a cache hit there is no additional delay (a cache hit takes 1 cycle). On a miss the
main memory access begins in the next clock cycle (so cache misses take 1 more clock cycle than in
problems 1 & 2). Assume the cache hit rate is 85% (for loads and stores) and compute the CPI for
both ​bzip2 ​and ​hmmer​.
4) What is the speedup achieved from adding the cache for both ​bzip2 ​and ​hmmer​?